GB2180715A

GB2180715A - Storing colour image

Info

Publication number: GB2180715A
Application number: GB08522910A
Authority: GB
Inventors: David Charles Yeomans; David Blythman; Laurence Ailbe Fitzgerald
Original assignee: GRAFTEL Ltd
Current assignee: GRAFTEL Ltd
Priority date: 1985-09-17
Filing date: 1985-09-17
Publication date: 1987-04-01
Also published as: GB8522910D0

Abstract

A method of storing a colour image in digital form, the image being derived from a plurality of identical frames of video data each comprising colour pixels supplied line-by-line for use by a raster-scan refresh display device comprises providing a source (20) of clock signals having a frequency substantially higher than the pixel rate in the video data, counting the clock signals by means of a counter (29) from the start of each line containing pixels required to form the stored image, entering successive pixels of each said line in digital form into a pixel register (25 to 27) under control of the clock signals, and reading out into a digital store the pixel currently in the register (25 to 27) when the counter (29) has counted a predetermined number of clock signals. The predetermined number of clock signals for each line is set at a different value in respect of successive frames, the different values being selected as a function of the pixel rate such that a different pixel is read out to the store during each frame. The result is that the stored image comprises the accumulation of different pixels read out from the register (25 to 27) into the store during a plurality of frames of the video data. <IMAGE>

Description

SPECIFICATION Method and apparatus for storing a colour image This invention relates to a method and apparatus for storing a colour image in digital form, particularly but not exclusively for subsequent print out on a matrix colour printer, the image being derived from a plurality of identical frames of video data each comprising colourpixels supplied line-by-linefor use by a raster-scan refresh display device.

Apparatusforforminga hard copy output of a displayed image is not particularly difficult to construct where the format of the video data (e.g.

frame rate, line frequency, number of pixels per line) is fixed and known in advance. In otherwords, if such apparatus is dedicated to a particularfixed format of video data itis in principal simpleto acquire the pixel information for storage and subsequent output to a matrix printer by using a clock signal synchronised to the pixel rate.

However, when it is desired to provide an apparatus which can operate with a variety of different formats of video data, the problem arises of synchronisingthe internal clock of the apparatus to the pixel rate in each different case.

It is therefore an object of the invention to provide an apparatusforstoring acolourimage inwhichthe need forexact synchronisation of a clock signal with the pixel rate is avoided.

Accordingly, the invention provides a method for storing a colour image in digital form, the image being derived from a plurality of identical frames of video data each comprising colour pixels supplied line-by-line for use by a raster-scan refresh display device, the method comprising: providing a source of clock signals having a frequency substantially higherthan the pixel rate in the video data, counting the clocksignalsfrom the start of each line containing pixels required to form the stored image, entering successive pixels of each said line in digital form into a pixel register means under control ofthe clock signals, reading out into a digital store the pixel currently in the register means when a predetermined number of clock signals have been counted, and setting the said predetermined number of clock signalsforeach said lineata differentvaluein respect of successive frames, the different values being selected as a function ofthe pixel rate such that a different pixel is read outto the digital store during each said frame, whereby the stored image comprises the accumulation of different pixels read out from the register means into the digital store during a plurality of framers ofthe video data.

Preferably each different value forthe predetermined number of clock signals is selected as a function ofthe video data format by calculating each value as the nearest integer the quantity N1 + (n+1/2)N2 where N1 is the number of clock signals from the start of each line period containing image data to thefirst pixel ofthe line, N2 is the number of clock signals per pixel period, n is an integer in the range from zero to (P-l) inclusive, and P isthetotal number of pixels per line, n being different in respect of successive frames.

The invention also provides an apparatus constructed to operate according to the above method.

The advantage of the invention is that the requirement to provide exact synchronisation between the clock signals of the apparatus and the pixel rate is avoided by providing clock signals having a substantially higherfrequencythan the pixel rate normally excountered in commercial displays, and in effect by selecting a subset ofthese high frequency clock signals, as a function ofthe video data format, which are in sufficiently approximate synchronism with the input pixels to ensure that each pixel required forforming the stored image is reliably acquired.

While the embodiment of the invention provides a stored image which contains every pixel in the display, this is not strictly necessary and it is possible to store pixels corresponding to a subsetofthe displayed image. For example, by acquiring pixels from alternate lines one can obtain a stored image having lower resolution in the vertical direction, and by aquiring alternate pixels in each line one can obtain a stored image with lower resolution in the horizontal direction. If both techniques are used the stored image will be of reduced resolution in both directions compared to the image on the display device. One may also store any desired sub-area of the displayed image if desired.All these possibilities may be achieved by suitable selection of the lines from which pixels are acquired and, for each frame, of the predetermined number of clock signals for each ofthese lines which define the current pixel in the register means for read out to the digital store.

An embodiment ofthe invention will now be described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is an overall system block diagram of an embodiment ofthe apparatus according to the invention, Figure2 is a timing diagram to assist in explaining the principles of operation ofthe apparatus, Figure 3 is a schematic diagram of a frame of video data showing various parameters used in operation of the apparatus, Figure4is a block diagram ofthe pixel sampling hardware of Figure 1, and Figures 5to 7areflow diagrams illustrating the operation of the apparatus.

Referring to Figure 1, the apparatus is under overall control of a micrprocessor 10 having main system random access memory (RAM) 11. The apparatus also includes an auxiliary RAM 12 which, as will be described, contains parameters relating to the particularformatof inputvideo data forwhichthe apparatus is set up in any given case. The RAM 12 is battery-supported so that these parameters are retained even when the power system is switched off; thus it is only necessary to perform the setting up procedure once for any given video data format. The microprocessor control program and various operating routines for initial set up, pixel acquisition (sampling), and printer output control are stored ina read only memory (ROM) 13.System communication is via a bidirectional bus 14.

For initial set up, i.e. determination of video data format and storage of corresponding parameters in RAM 12, the apparatus receives format data such as whetherthe image is interlaced or non-interlaced, and the number of pixels both horizontally and vertically, via an RS 232 interface and universal asynchronous receiver/transmitter UART2. The video data itself, which is supplied atterminals 16 to 19 is assumed to be derived from a raster-scan refresh video display terminal, or from a computer driving such a terminal, and therefore comprises frames of digitally coded colour pixels supplied line-by-line in generaily conventional manner.In the present apparatus it is assumed that the video data is non-interlaced and that each colour pixel comprises red, green and blue primary components each coded as a binary 1 oreo so that each primary is either on or offforeach pixel thus defining eightcolours including black and white for each pixel. However, as will be described, the invention may be extended to interlaced video data (i.e. two fields perframe) andto pixels whose primary colour components have multiple levels of intensity, Figure 2, line a, shows the bi-level pixel data provided to the system for one of the primary colour components ofthe video data.In this case a simplified data sequence is shown, wherein the primary colour is alternately on and offfor successive pixel periods. Naturally, three such data sequences are provided in synchronism, each corresponding to a different primary colour, so that in each pixel period a corresponding pixel is completely defined in terms of its three primary colour components.

This pixel data is supplied from the terminal with the red, green and blue pixel data in parallel form on input lines 16,17 and 18 respectively, with line and frame sync pulses on input line 19. The input on each ofthe lines 16to 18 is generally oftheform shown in Figure 2, line a, and the input data is in synchronism on each ofthe lines 16to 18; in otherwords during a given pixel period the bi-level values ofthe primary colourcomponents presentatthe input lines 16to 18 relate to the same pixel.

Pixel acquisition is performed using pixel sampling hardware 15, Figure 1. The hardware 15 contains an oscillator 20 which provides clock signals atafrequencysubstantiallyhigherthanthepixel rate, the latter being defined as the reciprocal ofthe pixel period. In general, sincethe apparatus is designed for use with different terminals with different video data formats, there will rarely be an exact synchronism between the clock signals ofthe oscillator 20 and the pixel rate, and in practice the clocksignal frequency should be chosen to be at least three times the pixel rate likely to be encountered in most commercial display terminals.

Figure 2, line b, shows clock signals which have a frequency of between three and four times the pixel rate. The operation ofthe sampling hardware 15will be described later with respect to Figures 4 and 6, and the initial set up operation will be described with reference to Figures 3 and 5.

Pixels acquired by the hardware 15 are entered into the main system RAM ii via the bus 14 until a complete image has been stored. At anytime after this the image may be read out for matrix printing in a generally conventional fashion, either via a buffer 21 to a parallel (Centronics) interface or via a UART 1 to an RS 232 serial interface, according to printer type.

The initial setupfora particularvideo data format will now be described with reference to Figures 3 and 5. In Figure 3 a non-interlaced video frame is indicated at 40, and the actual image containing part oftheframe is indicated at41, it being recognised that in general each frame contains in the vertical direction a numberof blank lines before and afterthe actual image information, and in the horizontal direction a blank part of each line before and afterthe image information. The object of the initial set-up procedure is to determine the following parameters: L1: the number of lines from frame sync to thefirst image-containing line (frame dead time).

L2: the depth ofthe image in terms ofthe number of lines.

N1: the numberofclock pulses ofthe oscillator 20 from line sync to the left hand edge ofthe image (line dead time).

N2: the pixel width (pixel period) in terms of a number of clock signals ofthe oscillator 20. This will generally be a non-integral number.

N3: the number of clock signals ofthe oscillator20 from linesynctothe right hand edge ofthe image.

T: the number of clocksignalsfrom line syncto the centre ofthefirst pixel in each line.

These parameters are determined by the microprocessor 10 according to the method shown in the flow diagram illustrated in Figure 5. The basic technique is to put up an all-white image area (block 50 of the flow diagram) and then directly measurethe parameters L1, L2, N1 and N3 by examining the green data, as indicated in blocks 51 to 54 of the flow diagram, it being recognised that in an all-white image every pixel will contain a green component (in addition to red and blue components). The parameters N2 and Tare calculated from the measured parameters using the equations indicated in flow diagram blocks 55 and 56. The sync and pixel data input to the system during set-up is via the inputs 16to 19; however,duringthis operation pixel acquisition by the hardware 15 is inhibited.

The parameters thus determined are stored in the battery-supported RAM 12. In orderto allowforsmall variations in these parameters it is advisable to make several measurements for Nq and N3 and take an average, as indicated.

The routine for performing the above set-up procedure is stored in the ROM 13 as previously mentioned, and is called up by an appropriate operator input on a keyboard associated with the display terminal via UART 2. It is to be recognised thatifonlya partofthetotal image area isto be acquired for storage, only the corresponding part of the screen need be whitened before the measurements begin.

Having determined the particularterminal video data format parameters as above, the acquisition of pixels for storage occurs as follows. The bi-level red, green and blue (R,G,B) components of successive pixels are supplied in synchronism to the inputs i6to 18 of hardware 15 as described above, and the line and framesyncs are supplied tothe input 19.

From the inputs 16 to 18, the bilevel R,G,B components of successive pixels are supplied to respective threshold devices (comparators) 22 to 24 for signal shaping and, if necessary, level conversion. However, the basic form ofthe signals from 22 to 24 is still as in Figure 2, line a, exceptthat the voltage difference between binary 0 and binary 1 may be different from the input voltage difference to adapt to the characteristics ofthe following hardware.

The bilevel R,G,B signals output from the comparators 22 to 24 are entered into a pixel register comprising individual colour component registers 25 to 27 by the clock pulses from the oscillator 20. It is to be noted that since the clock frequency is much higherthan the pixel rate, the contents ofthe registers 25to 27 do notchangeforeveryclocksignal but only in respect ofthe leading edge ofthefirst clock signal after a change of pixel data present atthe input ofthe registers. These points are indicated by the small arrows 28 in Figure2.

While successive pixels are being clocked into the pixel register 25 to 27, a horizontal position counter 29 simultaneously counts the clock signals down from a predetermined countvaluewhich is loaded into the counter prior to line sync, countdown beginning when a line sync pulse is received from a syne separator 30 connected to input 19. When the countvaluein counter29 reacheszero,asignal is provided on output line 31 which freezes the current contents ofthe registers 25to 27. The pixel thus frozen in the pixel register is subsequently read out to the system bus 14 by enabling bus drivers 32.In a mannerto be described with reference to Figure 6, the predetermined count value loaded into the counter 29 is selected such that the point at which the contents ofthe registers 25to 27 are frozen corresponds to the leading edge of a clock pulse nearest to the centre of a pixel period. Typical points at which the pixel data may be frozen are indicated by the long arrows 33 in Figure 2, although from the following description it will be understood that only one pixel is frozen in any given line period.

For a single frame of input video data the above sequence of events, i.e. loading the counter 29, counting down to zero, freezing the pixel register contents, and reading outto the system bus 14, occurs onceforeach line containing image data.

Furthermore, the count value loaded into the counter 29 is fixed for any given frame. The result is that after one frame period a single column of pixels has been read outdo the system bus 14. Such a column is indicated schematically at 34 in Figure 3. The pixels read outto the system bus 14 are entered into a digital store which is conveniently the main system RAM 11. The pixels may be entered individually into the RAM ii as they are read out from the registers 25 to 27, or a plurality of pixels may be accumulated in a buffer and loaded into the RAM 11 as a block.

From the foregoing it is apparent that in orderto accumulate a full image in the RAM 11, each different column of image pixels must be read out from the registers 25to 27, and this is effected during a number offrames equal to the desired number of columns by providing adifferentcountvalueforthe counter 29 in respect of each such frame. In particular, the countvalue is selected to samplethe first pixel in each line during a first frame, the second pixel in each line during the next frame, and soon, until the last pixel in each line is sampled during the Pth frame, where P is the number of pixels in a line.At this point it should be noted that during the initial setting up procedure, Figure 5, the registers 25to 27 arenotfrozen atanypointalong each line in orderto enable the parameter N3 and consequently N2to be determined, the contents of the registers being made continuously available to the system bus 14 by enabling the bus drivers 32.

The method of performing pixel acquisition as described above is controlled by the microprocessor 10, the appropriate program routing being stored in the RAM 13 and being called up byan appropriate operator input the flow diagram of the operation is illustrated in Figure 6.

Referring to Figure6,in block60thestored parameterTisreadfrom RAM 20. Blocks 61 to 63 round the value of Tto the nearest integer, and after waiting forthe line period L1 afterthe nextframe sync pulse (blocks 64 and 65), this being the line immediately beforethefirst line containing image information, the parameterTis loaded into the counter 29 (block 66).

Now the counter 29 waits forthe next line sync pulse from the sync separator 30 (block 67), after which the counter is decremented by the clock signalsfrom the oscillator20 (block68). When the count reaches zero (block 69) the registers 25 to 27 are frozen bya signal on line 31 (block 70) and the register contents are read to the RAM 11 via the bus drivers 32 (block 71). It isto be recognised that blocks 67to 70 ofthe flow diagram are performed entirely by the hardware ofthe pixel sampler 15, with no microprocessor intervention.

Having now read out a single pixel to the RAM 11, block 72 tests whether the current line is the last containing image information. Since we have so far dealt with onlythefirst line in thefirstframe,the answer is NO and the sequence loops back to block 66. Steps 66 to 71 are repeated for the second and subsequent lines until the line count is (L1 +L2). At this stagethefirstcolumn of pixels has been read into the RAM 11.

Block 73 tests whetherthe last column has been stored (note that thevalue given forTin block 73 defines the centre of the last pixel of a line). Since we have so far only processed one frame, the answer is NO and Tis incremented by N2 (block 74). Steps 61 to 72 are now repeated for each frame, incrementing T by N2 each time, until decision block 73 gives YES. At this point all columns of pixels have been processed and entered into the main system RAM 1 1,which now contains a complete image.

The presentation ofthe store image to the matrix printer is fairly conventional, and is performed under control ofthe microprocessor 10 according to the method illustrated in the flow diagram of Figure 7. It is believed thatthisflowdiagram is self-explanatory and therefore no detailed explanation is given. For the avoidance of confusion, however,theterm "column" in Figure7 refers to a column of pixels of sufficient depth forfull utilisation ofthe print head during one pass, and not to a full column ofthe image as previously described.

Various modifications ofthe above apparatus are possible andwithin the scope ofthe invention. For example, it has been assumed that each R,G,B component of each pixel is bi-level, i.e. either ON or OFF. However, each R,G,B component could be multi-level so asto define an intensity scale for each primary colour. For example, if each R,G,B component could take relative values of 0,1/3,2/3 and 1,then a scale of four intensity levels would be defined. In such a case, for any given R,G,B component currently atone ofthe inputs 16to 18, the particularlevel could be readily determined by thresholding,andtheoutputfrom each of 22to24 would be a two bit binary number presented in parallel to the corresponding register 25 to 27.

Furthermore, the invention is also applicable to interlaced video data, requiring only minor modifications to the flow diagrams of Figures 5 and 6 well within the capabilities of those skilled in the art.

Claims

1. A methodforstoring a colour image in digital form, the image being derivedfrom a plurality of identical frames ofvideo data each comprising colour pixels supplied line-by-line for use by a raster-scan refresh display device, the method comprising:: providing a source ofclocksignals having a frequency substantially higherthan the pixel rate in the video data, counting theclocksignals from the start of each line containing pixels required to form the stored image, entering successive pixels of each said line in digital form into a pixel register means under control ofthe clock signals, reading out into a digital store the pixel currently in the register means when a predetermined number of clock signals have been counted, and setting the said predetermined number of clock signalsforeachsaid line atadifferentvalue in respect of successive frames, the different values being selected as a function ofthe pixel rate such that a different pixel is read out to the digital store during each said frame, wherebythestoredimagecomprisesthe accumulation of different pixels read out from the register means into the digital store during a plurality offrames ofthe video data.

2. A method according to claim 1, wherein each differentvalueforthe predetermined number of clock signals is selected as a function of the video data format by calculating each value as the nearest integer to the quantity Nr + (n+1/2)N2 where N1 is the number ofclocksignalsfromthestart of each line period containing image data to the first pixel ofthe line, N2 is the number ofclock signals per pixel period, n is an integer in the range from zero to (P-1) inclusive, and P is the total number of pixels per line, n being different in respect of successive frames.

3. A method for storing a colour image in digital form,the image being derived from a plurality of identical frames of video data each comprising colour pixels supplied line-by-line for use bya raster-scan refresh display device, the method comprising: providing a source of clock signals having a frequencysubstantiallyhigherthanthe pixel rate in the video data, for each of a plurality of frames counting the clock signals from the sta rt of each line containing pixels required to form the stored image, entering successive pixels of each said line in digital form into a pixel register means under control ofthe clock signals, reading out intoadigital storethe pixel currentlyin the registermeanswhen a predetermined number of clock signals have been counted, and setting the said predetermined number of clock signals at a different fixed value in respect of each of the said plurality of frames, the different values being selected as a function ofthe pixel rate such that a different column of pixels is read out to the digital store during each frame, whereby the stored image comprises the accumulation of a pluralityofdifferentcolumnsof pixels read out from the register means into the digital store during the said plurality of frames of the video data.

4. Amethod according to claim 3, wherein the different values for the predetermined numberof clock signals are selected as a function of the video data format by determining the number N1 of clock signalsfromthestartofeach line period containing image data to the first pixel ofthe line, determining the number N2Of clock signals per pixel period, and calculating each value as the nearest integer to the quantity N, + (n+1/2)N2 where n is an integer in the range from zero to (P-l) inclusive, and P is the total number of pixels per line, n being fixed for each said frame but differing in respect of different frames.

5. A method according to claim 4, wherein n is stepped through the said range changing by one for each successive frame whereby consecutive columns of pixels are entered into the digital store.

6. A method according to any preceding claim, wherein the predetermined number of clock signals is counted by setting a counterto the said predetermined numberatthe start of each line period and decrementing the counter by one for each clocksignal,the pixel read outdo the digital store being that pixel in the register means when the counter reaches zero.

7. Anapparatusforstoring acolourimagein digital form, the image being derived from a plurality of identical frames of video data each comprising colour pixels supplied line-by-line for use by a raster-scan refresh display device, the apparatus comprising:: a source of clock signals having a frequency substantially higher than the pixel rate in the video data, a counterforcounting the clock signals, from the start of each line containing pixels required to form the stored image, pixel register means into which successive pixels of each said line are entered in digital form under control ofthe clock signals, meansforreading outintoa digital storethe pixel currently in the register means when the counter has counted a predetermined number of clock signals, and meanssettingthesaid predetermined numberof clocksignalsatadifferentvaluein respectof successive frames, the different values being selected as a function ofthe pixel rate such that a different pixel is read out to the digital store during each said frame, whereby the stored image comprises the accumulation of different pixels read out from the register means into the digital store during a plurality offrames of the video data.

8. An apparatus and method for storing a colour image in digital form, substantially as described herein with reference to the accompanying drawings.

Amendments to the claims have been filed, and havethefollowing effect: New ortextually amended claims have been filed asfollows: CLAIMS

1. Amethodforstoring a colour image in digital form, the image being derived from a plurality of identical frames of video data each comprising colour pixels supplied line-by-line for use by a raster-scan refresh display device, the method comprising:: providing a source of clock signals having a frequency substantially higherthan the pixel rate in the video data, counting the clock signals from the start of each line containing pixels required to form the stored image, entering successive pixels of each said line in digital form into a pixel register means under control of the clock signals, reading outintoa digital storethe pixel currentlyin the register means when a predetermined number of clock signals have been counted, and setting the said predetermined number of clock signals for each said line at a different value in respect of successive frames, the different values defining a subset ofthe clock signals as a function of the pixel rate such that a different pixel is read outto the digital store during each said frame, whereby the stored image comprises the accumulation of different pixels read out from the register means into the digital store during a plurality offrames ofthe video data.

2. A method according to claim 1, wherein each differentvalueforthepredetermined numberof clock signals is selected as a function of the video data format by calculating each valueasthe nearest integer to the quantity N, + (n+1/2)N2 where N1 is the number of clock signals from the start of each line period containing image data tothefirst pixel ofthe line, N2 is the number ofclocksignals per pixel period, n is an integer in the range from zero to (P-1) inclusive, and P is the total number of pixels per line, n being different in respect of successive frames.

3. A methodforstoring a colour image in digital form, the image being derived from a plurality of identical frames of video data each comprising colour pixels supplied line-by-line for use by a raster-scan refresh display device, the method comprising: providing a source of clock signals having a frequency substantially higherthan the pixel rate in the video data, for each of a plurality offrames counting the clock signals from the start of each line containing pixels required to form the stored image, entering successive pixels of each said line in digital form into a pixel register means under control ofthe clock signals, reading out into a digital store the pixel currently in the register meanswhen a predetermined number of clock signals have been counted, and setting the said predetermined number of clock signals at a different fixed value in respect of each of the said plurality of frames, the different values defining a subset ofthe clocksignals as a function of the pixel rate such that a different column of pixels is read out to the digital store during each frame, whereby the stored image comprises the accumulation of a plurality of different columns of pixels read out from the register means into the digital store during the said plurality of frames of the video data.

4. A method according to claim 3, wherein the differentvaluesforthepredetermined numberof clocksignals are selected asafunctionofthevideo data format by determining the number N1 of clock signals from the start of each line period containing image data to the first pixel of the line, determining the number N2ofclocksignals per pixel period, and calculating each value asthe nearest integer to the quantity N1 + (n+1/2)N2 wheren is an integer in the range from zero to (P-1) inclusive, and P isthetotal number of pixels per line, n being fixed for each said frame but differing in respect of different frames.

6. A method according to any preceding claim, wherein the predetermined number of clock signals is counted bysetting a counter the said predetermined number atthe start of each line period and decrementing the counter by one for each clock signal, the pixel read out to the digital store being that pixel in the register means when the counter reaches zero.

7. An apparatusforstoring a colour image in digital form,the image being derived from a plurality of identical frames of video data each comprising colour pixels supplied line-by-line for use by a raster-scan refresh display device, the apparatus comprising: a source of clock signals having a frequency substantially higherthan the pixel rate in the video data, a counterforcounting the clock signals, from the startofeach line containing pixels required to form the stored image, pixel register means into which successive pixels of each said line are entered in digital form under control ofthe clock signals, means for reading out into a digital store the pixel currently in the register means when the counter has counted a predetermined numberofclocksignals, and means setting the said predetermined number of clock signals at a different value in respect of successive frames, the different values defining a subset ofthe clock signals as a function ofthe pixel rate such that a different pixel is read out to the digital store during each said frame, whereby the stored image comprises the accumulation of different pixels read out from the register means into the digital store during a plurality offrames of the video data.