RU1833858C - Device for graph information output - Google Patents

Abstract

Usage: computer technology, raster multicolor video systems. The inventive device contains 1 control unit (1), 3 data buffers

Description

The invention relates to the field of computer technology and can be used to create multi-color raster information display systems operating in a multi-screen mode, with enhanced dynamic characteristics and high image resolution.

The purpose of the invention is to increase the information capacity of the device and improve the quality of input information by increasing the number of image decomposition points per line.

In FIG. 1 shows a structural diagram of a device; in FIG. 2 - formats of descriptors codra, strip (2A) and cells (26).

The device comprises a control unit 1, a first data buffer 2, a first memory unit 3, a first register 4. a first counter 5, a block of 6 registers, a second register 7, an adder 8, third through seventh registers 9-13, second 14, third 15 and the fourth 16 counters, a bottom 17 bus, a format converter 18, an address bus 19, a synchronization unit 20, a decoder 21, a fifth counter 22, a digital-to-analog converter 23 (DAC).

24 indicates the clock input of the device.

The device comprises sixth 25 and seventh 26 counters, a multiplexer 27, a first 28, a second 29 and a third 30 comparison blocks, a second memory block 31, a second 32 and a third 33 bottom buffers.

Numbers 34-40 indicate the outputs of the synchronization unit 20.

The control unit 1 comprises a programmable counter 41 and a switch 42. synchronization pulses.

Descriptors are 32-bit words in which are encoded: the number of lines in the strip M, the number of cells in the strip N. The repetition rate of the lines (vertical scale, MB), bits wide (C /)

WITH

00 CA OJ 00 SEA 00

no address (RA), priority P, number of bits per image element (pixel) (PSU), palette number (Nfl), horizontal enlargement coefficient (MG horizontal scale, cell length on screen L, address offset n0, and go to the next line cell S, the number of the pixel from which the screen starts in the first layer of the cell and the number of the pixel that ends with the screen to display the last word of the cell K.

Priority field Information can be displayed at a given point on the screen, containing in various cells of the video memory, and displayed in various modes. Display modes are contained in the respective descriptor fields of a frame, strip, or cell. Each of these decryptors has priority bits, the combination of values of which determines from which descriptor (frame) of the strip or cell) the display modes are taken.

Address extension field. This field allows you to work with video memory, for which 32 bits of the video word are not enough. By setting various field values, information can be displayed on the screen from various segments of the video memory. In fact, these are high bits of the extended address, the use of which depends on the total amount of video memory.

Palette number field. Each color code and video wordlist can have several colors or shades of color. Several variants of color tables for each of the modes are contained in block 31, and the number of the table actually used in this cell is set by the field number of the palette. Physically, the field is the high order bits of the address of block 31.

Field scale horizontally. This field sets the magnification factor of the image within the given cell.

Depending on the field value, each image point within a given cell is repeated several times on the screen.

The device operates as follows.

The image bitmap consists of the required number of fragments arbitrarily located in the video memory block 3.

At the same time, a table of descriptors describing the image in terms of a strip-cell structure is stored in the video memory.

Block 20 synchronization is a multi-mode programmable counter, forming a temporary diagram of the frame sweep depending on the contents of the registers (frame mode) 10, (strip mode) 12. (cell mode) 11. Block 20 operates from a clock source

the frequency supplied to input 24 and provides the formation of frame sync pulses at output 36, synchronization pulses of sampling / recording video words at output 35, horizontal sync pulses

at the output 38, the blanking pulses of the reverse stroke at the output 34, the video frequency at the output 37, the signal sample / write buffer 32 at the output 39, the signal sample / write buffer 32 at the output 40.

The operation diagram of the counter 41 is determined by the values of the fields of the strip of attributes of the strip from the transducer 18, which sets the sequence of recording video words into the device registers and the purpose of each

the next video word read from memory. In accordance with the consecutive states of the counter 41, the switch 42 provides synchronization pulses to the register entries of the device registers.

According to the frame pulse generated by block 20 at the beginning of the scan of the next image frame, a fixed hardware address A of the first descriptor of the first band is entered into the counter 5 (current address).

This happens as follows. On the trailing edge of the frame clock, block 20 provides a sequence of synchronization pulses

sample / record video data. On the leading edge of the first pulse, the value A is displayed on the address bus 19, which is contained in counter 5. From block 3 of video memory, the first word of the descriptor block is read at this address, which is written to the register by the trailing edge of the first sample / write pulse (output 35) 4 (next lane addresses). The same front increases by 4 the contents of counter 5 and

a counter 42, which determines in which register the next word to be read from the video memory will be recorded. Similarly, the second synchronization pulse from the video memory (block 3) is read

a word at address A + 4, while the contents of the fields M and N are loaded into register 13 (attributes of the current strip), the contents of the fields MB, RA and P of the descriptor of the first strip are entered simultaneously into register 10 (mode

frame) and register 12 (lane mode). The values of the BP, MP, and MP fields are also recorded in registers 10 and 12. The counters 5 and 41 of the word are incremented, and the next pulse from the video memory is loaded into the counter 5 with the address of the block of cell descriptors of the current band. The beginning from this address is read from the video memory and sequentially loaded into the registers of block 6 of the start address of all cells of this strip (the maximum value of N is determined by the hardware implementation of the system). After that, the counter 41 sets the switch 42 to the state in which, by the next synchronization pulse, the information fields of the next word in the video memory containing the mode information, the sweep of the first cell of the strip is entered into the counter 16 (words) (field L 1) in register 7 (bias) (field S 1), into register 11 (cell mode) (field BP1, MP, NPllj, and field K1 and Н1 into format converter 18, with the next synchronization pulse, the contents of counter 5 are transferred to register 9 (cell descriptor}, and counter 5 is loaded from the first register of block 6, the address began and in the first cell of the strip, Subsequent synchronization pulses read from the video memory words the video data of the first line of the raster and write these words to the data buffer 2.

In this case, the leading edge of the pulse records the word from the video memory at the address contained in counter 5, s buffer 2, and the back edge - increment by 4 counter 5, by 1-counter 41, and also decrement by 1 counter 16. The purpose of the buffer video data 2 — conjugation of the rate of extracting words from the video memory with the rate of outputting pixels from the converter 18 formats and writing them to buffers 32 and 33, the Converter 18 formats transform 32-bit words read from the memory into a sequence of codes whose bit defined by the BP field and Fr, the repetition frequency - field MF or MG. Each of these codes is associated with a specific color or hue specified by the value of the MP field or Nni. Which of the fields (BP or BP1, MG or MP, MP or MP1) determine the cell display mode depends on the value of the field P in registers 10, 11 and 12. The cell mode has the highest priority (1 in the corresponding section of register 11), if in the field P of the register 11 - O, in the field P of the register 12 - 1, then the display mode is determined by the values of the fields of the registers 12 and 15. If there are no units in the fields P of the registers 11 and 12, the contents of the cell are displayed on the screen display in accordance with the contents of the register 10.

Buffer 32 fills up during a frame scan backward. Address counters 25 and 26 are reset to the line clock. On the leading edge of the video frequency pulse from the converter 18 of the formats to block 31, a code of a point is displayed on the screen and incremented by 1 counters 25 and 28. On the falling edge

5 video signal from output 27 to input. fetching / writing of buffer 32, a recording signal is received from output 39. The leading edge of this signal at the address formed by counter 25 records data from buffer 32. block 31 output. On sampling / recording buffer 33 a sample signal is received from output 40. The leading edge of the signal from output 40 is at the address generated by the counting clock 26, data from the output of the buffer 33

5 are read and fed through the multiplexer 27 to the input of the digital-to-analog converter 23. If the beam blanking pulse from the output 34 is supplied to the control input of the CDL, a 7iibKb: M УУВКвМ, Э ВИДБОДЕННИв

0 HC. screen display will not be displayed.

On the leading edge of the next pulse of the video frequency from the output of the converter 18 to the input of block 31, the code of the next point in the line is received, the counters 25 and 25 are incremented, then the procedure is repeated by soldering the video data into buffer 32 v, reading the video data from buffer 33.

During the forward frame sweep, the first horizontal sync pulse

0, the counters 25 are reset and the inputs of the multiplexer 27 are switched, the contents of the second line of the frame are recorded, and the buffer 33 and the sobbing of the pair line of the frame from the buffer. 32 through the multiplexer 27

5 DAC 23, From the outputs R, G, and DAC 23, the video signals enter the display.

Placing buffers 32 and 33 after block 32 after block 31 of the palettes makes it possible to store and output to the DAC 23 information in a form ready for display on the screen.

The use of horizontal scanning in the proposed device for recording video data in buffers allows significantly

5 to increase the amount of video information loaded into the buffer before the start of the next line, that is, increase the number of points displayed on one line or, in other words, the resolution of the video system.

0 Form of invention

A device for outputting graphic information containing the first and second memory units, a control unit, a synchronization unit, a first data buffer, a digital-to-tax converter, the outputs of which are the outputs of the device, the control input of the digital-to-analog converter is connected to the first output of the synchronization unit, the output of the first unit the memory is connected to the data bus, the address is

the input input of the first memory block is connected to the address bus, the first control input of the first memory block connected to the first control input of the first data buffer is connected to the output of the control unit, the clock input of which is connected to the second control input of the first memory block connected to the second output of the synchronization block, the third output of which is connected to the second control input of the first data buffer, the clock input of the synchronization block is the clock input of the device, from the first to seventh registers, from the first to fifth counters, register block, adder, format converter, decoder, first to third comparison blocks, the address input of the second memory block is connected to the output of the format converter, the first information input of which is connected to the output of the first data buffer, the second information input of the format converter is connected to the data bus , the clock input of the format converter is connected to the fourth output of the synchronization unit, the information input of which is connected to the information inputs of the decoder and the fifth counter and the first control input of the format converter is connected to the outputs from the fourth to sixth registers, the information inputs of which are connected to the data bus, the information inputs of the first, second and seventh registers and the fourth counter are connected to the data bus, the first control input of the first register connected to the first the control input of the first counter and the first control input of the control unit is connected to the output of the third comparison unit, the first input of which is connected to the output of the third counter, the reset input of which о, connected to the reset input of the second counter and the clock input of the fifth counter, is connected to the fifth output of the synchronization unit, the control input of which, connected to the second control input of the format converter, is connected to the first output of the decoder, the second output of which is connected to the first input the first comparison unit, the second input of which is connected to the output of the fifth counter, the third control input of the format converter is connected to the output of the control unit, the information input of which is connected to the second input a third comparing unit and to the first input of the second comparator unit, connected to the output of the seventh register, the control input of which is coupled to a control input of the sixth

register, connected to the output of the control unit, the second control input of which is connected to the clock input of the second counter and the second control input

the first counter connected to the output of the fourth counter, the control inputs of which are connected to the output of the control unit, the reset input of which is connected to the control input of the second

0 counter, clock input of the third counter, reset input of the fifth counter and the third control input of the first counter, connected to the third output of the synchronization unit, the output of the second counter is connected

5 to the second input of the second comparison unit, the output of which is connected to the fourth control input of the first counter, the first information input of which is the address input of the device, the output of the first comparison unit is connected to the first control input of the register block, the second control input of which is connected with the second control input of the first register, the clock input of the first

5 counters, controlling the input of the second register, controlling the input of the adder, controlling the inputs of the third, fourth and fifth registers and the fifth control input of the first counter, is connected to the output of the control unit, the output of the first register is connected to the second information input of the first counter, the third information input of which is connected to the data bus, and the fourth information input

5 - with the first output of the register block, the information inputs and outputs of the first counter are connected to the address bus, the adder output is connected to the first information input of the register block, the second output of which is connected to the first information input of the adder, the second information input of which is connected to the output of the second register, the information inputs and outputs of the register block are connected to the data bus, the information inputs and outputs of the third register are connected to the address bus, characterized in that, in order to increase the information capacity In order to improve the quality of the output information by increasing the number of image decomposition points in a row, it contains the second and third data buffers, the sixth and seventh counters, and the multiplexer, the output of which

5 is connected to the information input of the digital-analog converter, the control input of the multiplexer and the clock inputs of the sixth and seventh counters are connected to the fifth output of the synchronization unit, the fourth output of which is connected to the control inputs of the sixth and seventh counters, the outputs of which are connected to the address inputs of the second and third data buffers controlling

corresponding outputs of the second memory block, and the outputs to the information inputs of the multiplexer, the second information input of the register block is connected to the output

the inputs of which are connected, respectively, 5 of the second counter, the control input of the fifth to the sixth and seventh outputs of the sync counter block is connected to the output of the first block

ronization, information inputs - to co-editor

Compiled by I. Zaginaiko Tehred M. Morgenthal.

comparing.

FIG. 2

Proofreader M. Tkach