GB2148077A - Video display control system - Google Patents

Abstract

A computer with only one or two output ports can be used to write different data displays to an unlimited number of VDUs (22). Each VDU has an associated video buffer VB (18) capable of storing a screenful of information, and each video buffer VB has an associated addressable switch means S in a switch bank (14) which determines whether data on a video transmission line (13) from the CPU (10) reaches the video buffer and the associated VDU. The signal addressing and controlling the switch means or both may be transmitted over its own line 12 and the video data signal over line (13), may if desired be transmitted over the same video transmission line 13. The buffers VB and switches S may be located at the VDUs, or centrally at the CPU, or otherwise. <IMAGE>

Description

SPECIFICATION Video Display Control System This invention relates to the control of multiple video displays from a central processing unit.

In this Specification the generally accepted abbreviations VDU and CPU are used to mean 'video display unit' and 'central processing unit' respectively. Of these, the video display unit may be simply a dumb terminal or television monitor. It need not have any memory or logic, but must be able to display a video image on receipt of a video signal.

Known computer systems permit a number of VDUs to be addressed by a CPU. An output port is provided for each VDU to be addressed by the CPU, and if two or more VDUs are connected to the same output port, then they display the same data. In all known systems there is a stated upper limit to the number of different output ports that can be supported by the system.

British Patent Application No. 8313919, in the name of three of the present Applicants, discloses an interface assembly whereby a number of users can share the same input port of a computer, but there is at present no known system whereby a number of screens or VDUs can share the same output port in order to display different data. The need for such a system is immediately apparent. In isolation, it enables the number of VDUs on which idiosyncratic information can be displayed to be increased to more than the number of output ports on the computer. In conjunction with the invention of British Patent Application No. 8313919 above, it enables any computer to become muiti-user without requiring a separate i/o port for each user.

The present invention provides a video display control system for controlling data from an output port of a CPU to enable different data to be transmitted sequentially or in parallel to a number of VDUs. The system comprises: an addressable switch bank comprising an array of switching means any one or more of which can be closed by logic signals from the CPU; a video transmission line from the output port of the CPU to the addressable switch bank; a number of video buffers; data transmission means between individual switching means of the addressable switch bank and corresponding individual video buffers; and means for addressing and controlling the addressable switch bank from the CPU, whereby information sent from the CPU to the video transmission line is onwardly transmitted only to one or more of the video buffers whose associated switching means have been closed by signals sent from the CPU.

The means for addressing and controlling the addressable switch bank from the CPU may be a dedicated control line, for example from a second output port of the CPU. Alternatively coded control signals may be sent along the video transmission line itself, selectively to address and to actuate different switching means of the switch bank. Thus the system of the invention may be used with computers with either one or two available output ports.

Typically in use the sequence of events would be that the CPU would send the video transmission line to an unloaded state; it would then send address signals over either the video transmission line or a separate control line to identify and close selected ones of the addressable switch means while opening all others; finally it would write data to the video transmission line, whereby any data in any of the video buffers that are "hooked up to" or switched onto the video transmission line would be overwritten by the new data. All other video buffers would remain unchanged, so that the data displayed on selected VDUs would change whereas any data on the screens of other VDUs in the system would remain unaltered.It will be appreciated that not only does the system of the invention permit a large number of VDUs to be addressed by a single output port of the computer; it also permits the choice of which VDUs change their data displays at any given time to be completely software-dependent, and permits the simultaneous updating of a number of video buffers by the simultaneous closure of a number of switching means in the switch bank.

The system of the invention is essentially a queueing system, whereby for n different data displays the CPU must send out a succession of n different command sequences. It might therefore be thought that queueing problems would soon result in unacceptable delays and would effectively override the advantages of having a potentially large number of independently addressable VDUs.

Surprisingly this is not the case. The time taken to address and close a given switching means or set of switching means in the switch bank and to write a screenful of data into the associated video buffer or buffers is sufficiently small to maintain the queueing time below a level of operator-awareness for a very wide range of applications and a very substantial number of independent data displays.

The size of the buffer used for each video buffer would generally be 1K to 2K. A 1K buffer would support a 40x25 screen display, whereas a 2K buffer would support an 80x25 screen display.

Considering first the hardware configuration in which each VDU is in a console with its own internal video buffer; the data transmission means between the switch bank and the various video buffers must be capable of transmitting the data selectively to a number of remote locations. Hard-wired connections are clearly possible, with each VDU/ buffer console being connected to an output of one only of the switching means of the switch bank.

Alternatively each switching means output may lead to a modulation circuit and thence to a wire loop or transmitter which would transmit the modulated outputs of all the switching means in the switch bank to all of the VDU/buffer consoles in the system.

Each VDU/buffer console would then have to have an inbuiltdemodulatorenabling itto be tuned selectively to recognize the output of one only of the switching means. The transmitter in such a configuration could be an ultrasound, infrared or radio frequency transmitter, or any other appropriate transmission means.

Considering next the hardware configuration in which each VDU is a dumb terminal and the video buffers are collected together in a single buffer bank; the data transmission means between the switch bank and the buffer bank may be a hardwired connection such as a printed or integrated circuit connection. However a further data transmission means must be provided between the outputs of the individual video buffers of the buffer bank and the VDUs. This further data transmission means may be individual hard-wired connections to the various remote VDUs or a modulated transmission means such as that described above in connection with the first described hardware configuration.

A further level of software control over the data distribution can be obtained if the above further data transmission means incorporates a second switch bank enabling any VDU to be selectively connected, under the control of the CPU, to any one of the video buffers. Thus control signals from the CPU would enable the CPU selectively to address and close any one or more switches in the first switch bank to overwrite data in the selected buffer or buffers; and simultaneously to address and close any one or more switches in the second switch bank to transmit data from the same or other selected buffers simultaneously to different VDUs.

The flexibility of the system described immediately above is considerable. The CPU can sequentially load information into the video buffers in any sequence, and can if desired load the same information simultaneously into two or more buffers, all under software control utilizing the addressable switch means to identify the individual buffers or combinations of buffers to be addressed and loaded. Once a buffer is loaded with video information, that video information is available to any VDU or network of VDUs which address the output of the buffer.

By a network of VDUs in the above context there is meant a number of video screens all intended to display the same data and all connected to the same video buffer. This is in comparison with a single VDU which displays its own idiosyncratic data. The further addressable switch means, under software control, permits each of a potentially large number of VDUs or networks of VDUs to address individual buffers, to scan the video information in those buffers. That same information is therefore displayed on selected VDUs until such time that the CPU either overwrites the video buffer via the addressable switch means to vary the information in that buffer or switches the VDU or VDU network to another buffer via the further addressable switch means.The programming possibilities using such a system are boundless, and the long-recognized problems of queueing times associated with multiuser systems simply do not apply since each buffer in the video buffer bank can be both loaded and accessed independently and, if appropriate, simultaneously.

In each of the above configurations the addressable switch means may if desired be interactive with the video buffer for the purpose of defining the switch address. Such a switch address is a variable logic state, and its use would be as follows: on switching on a given VDU its video buffer (including a defined address area in that buffer) would have a null value and the screen would be blank. Signals written to the video transmission line by the CPU would regularly include a 'stand-by' or 'set-up' screen display addressed to all VDUs with such a null address value, so as to generate a screen display which, for example, may prompt a user into inputting to the CPU a response to a given question or series of questions.The response would be effective to reset the address area of the VDU buffer to a value reflecting the nature of the response, and thereafter the address could be interactive with responses given. This would be of prime benefit in a teaching situation where a number of students key in their own responses to screen questions and are independently advanced through a teaching program at rates which depend on the accuracy of their replies. This is something never before realized using only one (or at most two) outputs ports of the CPU.

The above teaching situation could equally be achieved by having each switching means uniquely addressable, without interaction between the switching means and the video buffer to vary the switch address. The data displayed at a VDU assigned to a given student could then be varied either by sending a new video signal to a unique switch address leading to a buffer which the assigned VDU is accessing, or by causing the above switching network to switch the VDU to another video buffer. The whole of the switching is solely under the control of the computer program.

The two teaching situations described above are both interactive in the sense that each VDU is associated with a particular user or group or users and its display is varied in response to key responses from those users. However the invention is not limited to such interactive systems, and is capable of use with any system of information dissemination in which a central computer is used to generate different video displays on different VDUs. Examples include travel information (on a railway station, for example, where general timetable information may need to be displayed on a central VDU and information unique to each particular platform may need to be displayed on VDUs at those platforms) or medical information (in a hospital, for example, where the medical record of each patient could be individually addressed to a VDU by the bedside of that patient).

Drawings: Figure 1 is a block diagram illustrating in its most general sense the video display control system according to this invention; Figure 2 is a general arrangement diagram of a system according to the invention, in which each VDU has its own video buffer and is hard-wired to an outlet port of the common switch bank; Figure 3 is a general arrangement diagram of a second system according to the invention, in which each VDU has its own video buffer and receives FM signals from modulation circuitry associated with the addressable switch bank; Figure 4 is a general arrangement diagram of a third system according to the invention, in which the video buffers are grouped together in a single video buffer bank addressed via the switch bank and each video buffer is hard-wired to an associated VDU;; Figure 5 is a general arrangement diagram of a fourth system according to the invention, in which the video buffers are grouped together as in Figure 4 and transmit their outputs to the VDUs via modulation/demodulation circuits; Figure 6 is a general arrangement diagram of a fifth system according to the invention, in which a further switch bank in the form of a multiplexer switching network is provided across the outputs of the video buffer bank; and Figure 7 is a general arrangement diagram of a sixth system according to the invention, being a modification of the fifth system in which the transmission to the VDUs is via modulation/ demodulation circuits.

Referring first to Figure 1, a CPU 10 is shown with an output port 12 which is used to send address, command and video output data to an addressable switch bank 14. The addressable switch bank 14 comprises an array of switching means each of which can be addressed and opened or closed by data from the CPU. If desired, the output from the CPU may be shared between two output ports 12, with a first output port transmitting address and command data and the second transmitting video output data on a video output line 13. Alternatively the data may be shared on a single output line 13.

There will be a number n of outputs from the switch bank 14, corresponding to the number of switching elements in the array. These n outputs are fed via transmission means 16 to n video buffers 18.

The n video buffers may be grouped together in a single video buffer bank or may be discrete buffers each located remotely from the CPU 10 and switch bank 14 as part of a VDU console.

The n video buffer outputs are transmitted via further transmission means 20 ton VDUs 22 so that each VDU displays the video output of a selected one of the video buffers.

Although all individual elements of the blocks 14, 18 and 22 are not shown in Figure 1, for convenience it will be assumed that the switch bank 14 comprises n different switching elements S,~Sn; that the video buffers 18 comprise n buffers VB1 to VBn; and that the VDUs 22 comprise n VDUs, VDU, to VDUn. It will be apparent from the following description that the three values of n need not necessarily be the same, although for the purpose of this general description of Figure lit is assumed that there are the same numbers of switching elements, video buffers and VDUs.Each video buffer VB1 to VBn is of a size capable of writing a complete screenful of information to its associated VDU, and each switching means S1 to S, in the addressable switch bank 14 is addressable by its own unique logic state or number which for convenience will be assumed to be the number of the subscript referred to above.

In use, the CPU 10 is able to write different data to each of the VDUs, VDU1 to VDU,. A command signal is first written to the switch bank 14 to identify, for example, switch S, and close that switch. All other switches S2 to S, are open. Data is then written by the CPU to the video transmission line 13, and is onwardly transmitted by only the switch S, via the transmission means 16 to the associated video buffer VB1. The data is thence transmitted by the further transmission means to the screen of VDU1.

Finally another control signal from the CPU 10 causes all the switches S1 to S, to open. The display on the screen of VDU1 is maintained until the data in the buffer VB, is overwritten by a similar sequence of commands, or until the transmission means 20 breaks the connection, and in the meantime the CPU 10 can address, in sequence, the other VDUs 22 and write separately to each.

It will be appreciated that the time taken to load information into each video buffer is very small, and certainly much less than that taken to paint the screen with the information contained in that buffer.

Thus to the user it will appear that the displays on the various screens change simultaneously, although the various buffers are loaded sequentially.

One possible variant of the simple example given above is that more than one switch S may be addressed at the same time. Thus for example the command signal may close switches S1 and S2 while maintaining the others open, or may close all switches S1 to Snl to enable the closed switches to cause their associated video buffers to be overwritten simultaneously with the same information.

The output port 12 of the CPU may carry parallel coded or serial coded information which may be in any recognized or recognizable form, for example ASC1 1,8-bit or 16unit bytes. If desired, the same output port 12 can be used to convey both the command signals and serial coded video transmission signals. The output of the CPU at port 12 would then typically comprise: * a trigger byte indicating 'address follows'; * an address byte or series of address bytes, sufficient to close the switches at those addresses; * a second trigger byte indicating 'video buffer information follows'; * a series of bytes for overwriting any buffers that have been accessed; and * a final byte closing all switches at all addresses.

Clearly the cycle is repetitive, so that the same byte could have both the first and last functions indicated above.

Figure 2 shows a first example of an installation which operates in the way described with reference to Figure 1. The same reference numerals are used, where possible, as those in Figure 1.

In Figure 2 the CPU 10 sends its data over a video transmission line 13 to a switch bank 14. The switch bank 14 comprises n switches S, each capable of delivering a signal from the video transmission line 13to its own onward transmission line 161 to 16,,.

The lines 161 to 16n comprise the transmission means 16 of Figure 1 and are laid around the room, building or user area and terminate in outlet sockets 30 into which can be plugged video consoles 32 each of which comprises a video buffer VB connected to its own video display unit VDU. Thus then buffers 18 of Figure 1 are located inn different consoles, as are then VDUs 22. The further transmission means 20 of Figure 1 comprises simply the internal wiring of the VDU consoles 32.

Since the video consoles 32 are identical, they can be interchanged and as they are moved to different outlet sockets 30, each will display the data directed by the switch bank 14 to that outlet socket 30.

Clearly in the arrangement of Figure 2 the switch bank 14 could if necessary be integrated into the CPU or CPU housing.

Figure 3 shows a modification of the system of Figure 2 in which the transmission means 16 comprises a series of n frequency modulation circuits 34 each of which modulates the output of an associated one of then switching elements S1 to Sn.

The transmission means 16 further comprises a wire connection or broadcast transmission 36 to all of the consoles 32, each of which will be provided with a demodulating circuit enabling itto betunedto a particular carrier frequency. Thus the output of switch S1 is received only at the buffer VB,.

Many conventional television sets can be tuned to 32 different channels, so that by providing 32 switching elements in the switch bank 14 a single CPU can be programmed according to this system to address 32 different television screens and to write identical or idiosynchratic data to each of the screens. Particularly when the transmission means 16 makes use of a television distribution line conventionally available in modern school buildings, this makes the invention particularly suited to a classroom teaching situation.

Figure 4 shows a further arrangement in which not only the switches S but also the video buffers VB are integrated into banks. The CPU 10 writes data to its video transmission line 13 as in the previous embodiments.

The video transmission line data is fed through the switch bank 14 to a video buffer bank 18 which comprises a 1K or 2K buffer for each VDU of the system. The transmission means 16 of Figure 1 between the switch bank 14 and the video buffer bank 18 is in this example simply the wiring, printed circuitry or integrated circuitry connecting the two together. The video data is transmitted from the respective buffers to video outlet sockets 30, and VDUs 22 which are plugged into the various sockets 30 show an immediate display of the information carried in the respective video buffers. As with the arrangement of Figure 2, the information displayed on each VDU 22 is unique to the socket 30 into which it is plugged, rather than being unique to the particularVDU used.

Figure 5 shows a modification of the system of Figure 4 in which the further transmission means 20 between the buffer bank 18 and the VDUs 22 comprises frequency modulation circuitry 38 and a wire or broadcast signal 39 to provide signal separation in the same way as in Figure 3.

Figure 6 shows a further arrangement in which both the buffer inputs and the buffer outputs are independently switched under the control of the CPU. As with Figure 4, the video buffers VB are integrated into a video buffer bank 18, but in addition a switching network 40 is provided as part of the further transmission means 20 between the video buffer outputs and a bank of video outlet sockets 42. Loading of video information from the video transmission line 13 into selected video buffers VB is exactly the same as in Figure 4, but the switching network 40 gives a further very important ,level of control over what is displayed on the VDUs.

The switching network 40, under the control of the CPU 10, is capable of connecting any one of the video outlet sockets 42 in the bank to any one of the video buffers VB1 to VB,. If desired a number of video outlet sockets 42 can be connected to the same video buffer VB.

Thus to change a screen display on a VDU, for example VDU,, it is necessary simply to switch its associated outlet socket 42 via the switching network 40 from, for example, video buffer VB2 to VB,.

Finally Figure 7 shows a modification of the system of Figure 6 in which the further transmission means 20 between the switching network 40 and the VDUs 22 comprises, in place of the video outlet sockets 42, frequency modulation circuitry 38 and a wire or broadcast signal 39 in a manner analogous to that of Figures 3 and 5.

Claims (13)

1. A video display control system for controlling data from an output port of a CPU to enable different data to be transmitted sequentially or in parallel to a number of VDUs, comprising: an addressable switch bank comprising an array of switching means any one of more of which can be closed by logic signals from the CPU; a video transmission line from the output port of the CPU to the addressable switch bank; a number of video buffers; data transmission means between individual switching means of the addressable switch bank and corresponding individual video buffers; and means for addressing and controlling the addressable switch means from the CPU, whereby information sent from the CPU to the video transmission line is onwardlytransmitted only to those of the video buffers whose associated addressable switch means have been closed by signals sent from the CPU.

2. A system according to claim 1, wherein each VDU has a housing or console which houses one of the video buffers which uniquely supplies that VDU.

3. A system according to claim 2, wherein each VDU further comprises demodulation circuitry and the data transmission means comprises signal modulation and transmission means, whereby the output of a specified switching means of the addressable switch bank can be uniquely addressed to a particular VDU by appropriate tuning of the modulation and demodulation circuits.

4. A system according to claim 1, wherein all the video buffers are grouped together in a single video buffer bank with each switching means in the switch bank leading through an associated video buffer in the video buffer bank to a further data transmission means between individual video buffers of the video buffer bank and corresponding VDUs.

5. A system according to claim 4, wherein the further data transmission means comprises, between the individual buffers of the video buffer bank and individual outlet ports for the associated VDUs, a switching network addressable by the CPU selectively to enable any one or more of the outlet ports to receive a video signal from any one of the video buffers.

6. A system according to claim 4 or claim 5, wherein each VDU comprises demodulation circuitry and the further data transmission means comprises signal modulation and transmission means, whereby the output of a specified video buffer can be uniquely addressed to a particular VDU by appropriate tuning of the modulation and demodulation circuits.

7. A system according to any preceding claim, wherein each addressable switching means contains its own unique address which is independent of any data in the associated video buffer.

8. A system according to any of claims 1 to 6, wherein each addressable switching means contains an address which is interactive with data in the associated video buffer and which is changeable to reflect changes in the data in that buffer.

9. A system according to any preceding claim, wherein each video buffer is of a size capable of holding a complete screenful of information for its VDU.

10. A video display control system substantially as described herein with reference to Figure 1 of the drawings.

11. A video display control system substantially as described herein with reference to Figure 2 or Figure 3 of the drawings.

12. A video display control system substantially as described herein with reference to Figure 4 or Figure 5 of the drawings.

13. A video display control system substantially as described herein with reference to Figure 6 or Figure 7 of the drawings.