GB2129249A

GB2129249A - Apparatus for generating a signal for driving the field deflection in a picture reproducing device

Info

Publication number: GB2129249A
Application number: GB08328335A
Authority: GB
Inventors: Alain Decraemer
Original assignee: Philips Gloeilampenfabrieken NV
Current assignee: Koninklijke Philips NV
Priority date: 1982-10-27
Filing date: 1983-10-24
Publication date: 1984-05-10
Also published as: JPS59112766A; FR2535562A1; FR2535562B1; IT1171777B; IT8323407A0; DE3337386A1; GB8328335D0

Abstract

In a picture display device with a digital time base and providing an indirect field synchronisation by means of counting the number of half line periods and ascertaining if for a certain number of times there has been coincidence between the appearance of a predetermined count and a received field pulse, the detection of coincidence between the appearance of a further count and the said received pulse enables operation with indirect synchronization for two different standards e.g. 625-line and 525-line standards. The synchronizing circuit comprises one single counter 15, two state detectors (22A, 22B) which detect said coincidence states, and a selection circuit (23) which checks whether the coincidence state has been obtained for one of the two counts and, if so, instructs the reset- to-zero circuit 20 to generate a counting pulse for this count and to utilise it to release the field signal. The circuit 23 also checks whether the coincidence state has been obtained for the two counts or whether it has not been obtained for any of the counts, and in both cases instructs circuit 20 to utilise the separated pulse to release the field signal for the vertical deflection. <IMAGE>

Description

SPECIFICATION Method and apparatus for generating a signal for driving the field deflection in a picture reproducing device The invention relates to a method and apparatus for generating a signal for driving the field deflection in a picture display device, in which field pulses are obtained by counting half line periods, a check being made as to whether there is coincidence between the appearance of a predetermined number of half-line periods and a separated field pulse recovered from a signal received by the picture reproducing device, a synchronized state being determined when there is such coincidence during a predetermined number of consecutive fields for generating, when this state has been determined, a counting pulse when the said predetermined number of half-line periods appears and to use this counting pulse to generate a field deflection driving signal the separated pulse being used to generate the driving signal when the synchronized state has not been detected, There is at present a tendency as regards electronic circuits, and more specifically in picture reproducing devices, for example television receivers, to find a method in which a maximum number of signals can be processed digitally as this technique makes it possible to avoid the use of components such as capacitors or precision resistors, as it then becomes possible to integrate increasingly complete functions on a single semiconductor wafer, which reduces the number of interconnections by means of printed circuits.

Because of the fact that the number of expensive components, the size of the printed circuit surface areas and the number of semiconductor envelopes can be reduced very important savings can be realised.

One of the additional objects is inter alia to improve the insensitivity of the field synchronization to interference which synchronization one tries to obtain by means of counting the lines.

A number of embodiments have been realised in this field which are based on the same basic principle of generating a field pulse by means of a line counter, for a predetermined number of lines.

For the case of the European Standard of 625 lines a pulse is generated every 312.5 lines, that is to say every 625 half-line periods and this pulse is utilised instead of the above-mentioned separated pulse (indirect synchronisation).

A problem is then encountered, especially in the following two cases: when the phase of a field scan changes, which may, for example, be the case when a change is made from one camera to another it must be possible to start the counter again in accordance with the new phase, when the frequency is not the frequency expected, for example when a standard is received different from the anticipated standard, synchronization must nevertheless be obtained.

The underlying idea of all the prior art embodiments is to determine whether the synchronization is correctly defined by the line count, by means of trying to obtain coincidence between the separated pulse and the counting pulse, and to revert to the direct use of the separated pulse (direct synchronization), if the counting pulse is not correct. Obviously, in order to eliminate the action of interference, the decision that there is a non-synchronized state is not taken before the absence of coincidence has occurred several successive times.

A circuit having these features is described in, for example, French Patent Specification No.

2,208,261. This known circuit has the disadvantage that, when a transmission is received in which the number of half-lines of each field differs from 625, the circuit can only function with direct synchronization, that is to say by means of the separated pulse with all the known drawbacks of this mode of operation, namely sensitivity to interference and a poor performance in the case of a weak signal causing a poor signalto-noise ratio. Consequently, this circuit can only be used for synchronization by counting for one single standard.

The invention has for its object to provide a method and apparatus for generating a field signal by means of synchronization by counting for at least two existing standards, more specifically without the intervention of the user.

The invention provides a method as described in the opening paragraph which is characterised in that a check is also made as to whether there is coincidence between a second predetermined number of half-line periods and the separated field pulse, the synchronized state for each one of the predetermined number of half-line periods being stored and if this state is obtained for only one of these two numbers of half-line periods the corresponding counting pulse is generated and utilized to generate the field deflection driving signal, whereas when the synchronized state is not obtained for either of these two numbers of half-line periods the separated pulse is used to generate the field deflection driving signal.

The invention also provides apparatus for generating a signal for driving the field deflection in a picture reproducing device in which field pulses are obtained by counting half line periods, said apparatus comprising means for checking whether there is coincidence between the appearance of a predetermined number of ha If- line periods and a separated field pulse recovered from a signal received by the picture reproducing device, means for determining when there is such coincidence during a predetermined number of consecutive fields for generating, when this state has been determined, a counting pulse at the moment the said predetermined number of ha If- lines appears, and for using the counting pulse to generate a field deflection driving signal or for using the separated pulse to generate the driving signal when such coincidence has not been detected, characterised in that said apparatus further comprises means for checking whether there is also coincidence between a second predetermined number of half-line periods and the separated field pulse, means for storing information related to the said coincidence for each one of the predetermined number of halfline periods, means for producing the corresponding counting pulse if coincidence is obtained for only one of these two numbers of half-line periods and for generating the field deflection driving signal therefrom, and means for causing the separated pulse to be used to generate the field deflection driving signal should such coincidence not be obtained for either of these two numbers of half line periods.

The invention further provides a circuit for the above method and comprising - a half-line period counter, - a first count detection circuit to produce a pulse which corresponds to the first predetermined number of half-line periods, - a first state detector for detecting the synchronized state corresponding to the first count detection circuit and for generating the counting pulse when this state is detected, is characterised in that it further comprises:: - a second count detection circuit, coupled to the counter, for producing a second pulse which corresponds to the second predetermined number of half-line periods - a second state detector for detecting the synchronized state corresponding to the second count detection circuit and for generating the counting pulse when this state is detected, - a selection circuit connected to the first and second state detectors and operative when the first or the second state detector indicates the synchronized state and which triggers when the synchronized state is detected the field driving signal by means of the corresponding counting pulse, - and a gate which receives the separated pulse and is connected to the output of the selection circuit to trigger the field driving signal by means of the separated pulse when the selection circuit is not operative.

An advantage of the invention is that it is possible for a television receiver to operate in the synchronization-by-counting mode for two different standards which can be accomplished by using only one signal counter with consequent advantageous savings. It can therefore be used for the two main standards now existing in the world.

The following description which is given by way of example with reference to the accompanying drawings will describe how the invention can be put into effect: Figure 1 is a block diagram of a televison receiver comprising a circuit for effecting the method according to the invention, Figures 2 and 3 show details of the circuit of Figure 1, the circuit shown in Figure 3 being known per se, and Figures 4 and 5 illustrate the nature of some signals produced in the circuit of Figure 1.

In Figure 1, an aerial 1 receives a television signal and applies it to a high-frequency detection portion 2. Thereafter, the detected signal reaches the sound section 3 of the receiver and also a video amplifier 4, whose output supplies a composite video signal. This signal is applied to a portion 5 which recovers therefrom the components necessary to control a cathode-ray tube 6. It is also applied to a sync-separator 7, which applies line synchronizing pulses to a phase detector 8, whose output voltage is used to control an oscillator 11 by means of a filter 9 and a reactance circuit 10.The oscillator 11 generates a signal whose frequency is equal to twice the line frequency, i.e. 2H, that is to say 31,250 Hz upon reception of a signal in accordance with the standard having 625 lines per complete picture with two interlaced fields per picture and 50 fields per second. A further possiblity is that the oscillator 11 generates a voltage at a frequency f this frequency being doubled thereafter. The voltage having the frequency 2fH controls a frequency-divider circuit 12 in which the said frequency is divided by two, the signal obtained being applied to a line output stage 1 4 via a pulse-shaping stage 13.The line output stage 14 applies the deflection current to a horizontal deflection coil which forms part of a coil assembly 61 and sends a retrace pulse to the phase detector 8.

All these circuits are well-known to a person skilled in the art. They are here advantageously realised in accordance with digital circuit techniques, at least as regards the components 8 to 13. More specifically, the oscillator 11 may generate the frequency 2fH from an osciliation of a much higher frequency, for example of 38 MHz of which certain dividing radios supply integral multiples of the line frequency and more specifically a clock signal having a period of 842 ns, the use of which will be described hereinafter.

A digital field synchronizing separating circuit 21 renders it possible to recover the field synchronizing pulse contained in this signal from the synchronizing signal received by the aerial and separated by the separator 7. The separating circuit 21 utilizes the clock signal produced by the above-mentioned oscillator 11. Every 842 ns this signal starts feeding a sample of the separated signal into the series input of a shift register, for example a 24-bit register. The bits present at the parallel outputs of this register form a word.

When a field pulse appears in the separate signal, this word has a very special configuration, which is characteristic of this pulse. It may, for example, have at a precise instant after the beginning of the pulse, 12 1-bits followed by 12 O-bits. The detection of this configuration by means of a gate assembly releases the separated field signal.

This occurs during one single cycle of writing the samples into the register and the separated field pulse obtained will thus have a theoretical duration of 842 ns. The separating circuit 21 is not shown in detail for the sake of simplicity of the Figures, as such a separator is well known and can be easily realised by a person skilled in the art. It may be realised in any other known manner.

The field synchronization can be obtained by counting the 2fH-pulses in a 10-bit binary counter 15, which is connected to a pulse shaping circuit 17 and to a field output stage 18 which applies the deflection current to a vertical deflection coil which forms part of the coil assembly 61.

The synchronizing circuit comprises a first state detector 22A which includes a coincidence detector which detects coincidence between a separated field pulse recovered by the separator circuit 21 from the signal received at the aerial 1 and preprocessed by the circuits 2, 4, 7, and a pulse supplied by a first count detector 1 9A at the appearance of a predetermined number of ha If- lines at the output of the counter 1 5. This circuit 22A detects whether coincidence takes place during a predetermined number of consecutive fields, in which case it stores a synchronized state and delivers a signal which indicates that the synchronizing circuit is in this state.This synchronized-state signal is conveyed to a resetto-zero circuit 20 to let it know that it must generate a so-called "counting" pulse at the appearance of the said predetermined count of half-lines, and to utilize it to release the field synchronizing signal. In the embodiment described here it has been opted to have this signal appear by resetting the counter 1 5 to zero.

Thus, the counting pulse triggers the reset-to-zero operation of the counter, which generates the field signal conveyed to the vertical scanning circuit 18.

A second counting detector 1 9B applies a pulse to a second state detector 22B at the appearance of a further predetermined count at the output of the same counter 1 5. This state detector 22B comprises a coincidence detector which detects coincidence between the separated pulse and the appearance of this other predetermined count, and it stores a synchronized state for this other count.

A selection circuit 23 checks whether the synchronized state has been obtained for one of the two counts and, if so, instructs the reset-tozero circuit 20 to generate a counting pulse for this count and to utilise it to release the field signal. The circuit 23 also checks whether the synchronized state has been obtained for the two counts or whether it has not been obtained for any of the counts, and in both cases instructs circuit 20 to utilize the separated pulse to release the field signal for the vertical deflection.

Fig. 2 illustrates in greater detail the mode of operation on the basis of an example of a circuit diagram for the circuits 19, 20, 22, 23. It will be obvious that any other equivalent logic combination, possibly adapted to a specific manufacturing technique does not depart from the framework of the invention.

The circuit 20 is provided by an AND-gate 26 and three NAND-gates 27, 28, 29. The output of the gate 26 is connected to the reset-to-zero input of the counter 15, three of its inputs are each connected to the output of one of the NAND-gates 27, 28, 29 and a fourth input is connected to circuit 1 9D which supplies a "O" level for the count 656 of the counter. An input of the gate 27 is connected to the output of the circuit 19B which supplies a "1" level for the count 525 and a further input is connected to a connection denoted ds 525. An input of the gate 28 is connected to the output of the circuit 1 9A which supplies a "1" level for the count 625 and a further input is connected to a connection denoted ds 625.An input of the gate 29 is connected to the output of significance 512 of the counter 15, a further input is connected to a connection denoted ds and a still further input is connected to a connection denoted te The first state detector 22A rS fornned by two AND-gates 45, 46, two NOR-gates 43, 44, a shift register 42, two gates 47, 48 to check whether all the respective parallel outputs of the register 42 are "0" or "1", and a bistable trigger circuit formed by two NAND-gates 40, 41, which are coupled cross-wise. An input of the gate 46 is connected to the output of the circuit 1 9C which supplies a "1" level for the zero count of the counter and a further input is connected to the connection ds 625.An input of the gate 45 is connected to the connection ds and a further input to the above-mentioned output of the circuit 19A. An input of the gate 44 is connected to the output of the gate 46 and a further input is connected to the output of the gate 45. An input of the gate 43 is connected to the output of the gate 44 and a further input is connected to a connection denoted td. The output of the gate 43 is connected to the series input of the shift register 42, whose clock input is connected to the connection te. The two gates 47, 48 have their inputs connected to parallel outputs of the register 42. Gate 47 is an NAND-gate while gate 48 is a OR-gate, each of these gates having eight inputs. Their outputs are connected to the inputs of the bistable trigger circuit 40, 41 of which only one output is used.

The circuit 22B is similar to the circuit 22A, and all the internal components are denoted by the reference numerals 30 to 38, the unit digits being the same as those of the corresponding components of circuit 22A. The only differences in the connections are that one input of the gate 36 is connected to the connection ds 525 (instead of ds 625 for the gate 46) and that an input of the gate 35 is connected to the output of the circuit 1 9B (instead of 1 9A as for gate 45).

The circuit 23 is formed by three NOR-gates 49, 51, 53 and two inverters 50, 52. An input of the gate 51 is connected to the output of the bistable trigger circuit 30, 31 and the other input is connected to the output of the bistable trigger circuit 40, 41 via an inverter 50. An input of the gate 53 is connected to the output of the bistable trigger circuit 40, 41, and the other input is connected to the output of the bistable trigger circuit 30, 31 via an inverter 52. The inputs of the gate 49 are each connected to the output of one of the gates 51, 53. The connection ds 652 is connected to the output of the gate 51, the connection ds 525 to the output of the gate 53 and the connection ds to the output of the gate 49.

The circuit is capable of operating by counting in the so-called synchronous state for the 625line and the 525-line standards and in the direct synchronisation mode by means of the separated pulse for the other standards, or in a transitory way at the moment a change is made from one standard to the other or when the phase of the line scan changes which may be the case, for example, when during the transmission a change is effected from one camera to another.

The components 17, 1 9A to 1 9D, 37, 38, 47, 48 of Fig. 2 all have for their object to supply a signal for a certain configuration of their inputs.

Fig. 3 shows in known manner a circuit diagram of this type of circuit. The inputs of this circuit are provided by the parallel outputs of a counter or a register. Five inputs of the NOR-gate 24 are connected to the bits of the significance 2, 4, 8, 128,256 and six inputs of the AND-gate 25 are connected to the bits of the significance 1, 1 6, 32, 64, 512. When the latter have the value 1 and the former the value zero, the output of the gate 24 is a "1", as are also the inputs of the gate 25 and a signal is present at the output of the gate 25. In the example given here, this is obtained by means of a total number of 625 (i.e.

512+64+32+16+1 which corresponds to the bits connected to the gate 25). It is easy four a person skilled in the art to conceive further similar circuits for the detection of any number of counted lines. For that reason the components 1 9A, 1 9B and 1 9C in Fig. 2 are formed in such a way that they are capable of detecting the numbers equal to 625, 252 and zero, respectively. The circuits 1 7, 1 9D, 37, 38, 47, 48 are of the same type but are more simple and will be described hereinafter.

Fig. 4 illustrates how the two registers 32, 42 and one NOR-gate 39 operate. The signal td and a signal c are applied to the gate 39. The signal td shows the above-mentioned separated pulse and the signal c is the above-mentioned signal having a period of 842 ns supplied by the oscillator 11.

The output of the gate 39 supplies the signal te whose ascending edge 70 is delayed with respect to the descending edge 69 of td. The threshold at "O" of the signal td applied to the gates 43,33 renders it possible for these gates to apply a coincidence signal to be stored to the data input of the registers 42, 32 and the ascending edge of the signal te starts the storage at the instant indicated by an arrow at td, leaving enough time for the state to be established without fail before storage.

Resetting the counter to zero is effected by a transition to zero. Generally, all the inputs of the gate 26 have the "1" value, and also its output, the counter being reset to zero when at least one of its inputs passes to "O". The input connected to the circuit 1 9D does not pass to zero until the count 656. The inputs connected to the gates 28 and 27 do not pass to zero until the counts 625 or 525 and when ds 625 ords 525 have a "1" value. The input connected to the gate 29 does not pass to zero until the pulse te appears when the count exceeds 512 and do="1".

For a more detailed description of the operation of the circuits shown in Fig. 2 two cases will be considered, namely the case in which the field synchronizing circuit is in the synchronized state or in the non-synchronized state.

- In the synchronized state, for example at 625 lines.

In a way which will be explained hereinafter, the state detector 22B supplies a "0" from its output, which is an indication that there is no synchronism at 525 lines. This output is connected to an input of the gate 51 of the circuit 23. In the same way, the detector 22A supplies a "1", which indicates that there is synchronism at 625 lines. This "1" is converted into "0" by the inverter 50. As a result thereof the NOR-gate 51, whose two inputs have the value "0" supplies a "1" at its output, which "1" is applied to the gates 49, 28 and 46 via the connection ds 625.

The circuit provided by the inverter 50 and the gate 51 thus forms a first selection circuit which is activated when the first state detector 22A, and this first detector only, indicates that there is synchronization. This circuit then provides a "1" on the connection ds 625, the result being that: - the NOR-gate 49 supplies a "O" at its output to the connection ds and cuts off and the AND gate 29 which consequently does not play any part.

when the count 625 is reached, a "1" appears at the output 625 of the count detector 1 9A, which produces a "O" at the output of the AN AND-gate 28. This "0" causes the output of the AND-gate 26 to pass to "O" (as described in the foregoing, its four inputs all had first the value "1"), and thus triggers the reset-to-zero operation of the counter 1 5. The gate 28 has therefore for its function to withdraw the pulse from the count detector 1 9A and to release a field signal when this pulse is produced.

-The zero count having been reached, the circuit 1 9C supplies a "1", which is conveyed via the gate 46, which is followed by the NOR gate 44 which then supplies a "O". If a separated pulse "0" is present at td at that moment, the gate 43 supplies a 1 which is stored in the shift register, in accordance with a sequence which will be explained with reference to the Figures 4 and 5. As the synchronizing circuit is in the synchronized state, which was already obtained during preceding fields and the register was filled with ones. Consequently, nothing has changed, and the cycle may be reproduced indefinitely.

If the circuit was in the synchronized state, but at 525 lines, the mode of operation would be the same provided the components 23A, 228, 50, 51,28, 46, ds 625,44,43 are replaced in the above description by the respective elements 22B, 22A, 52, 53,27,36 ds 525, 34, 33. More specifically, the inverter 52 and the gate 53 provide a second selection circuit which is activated, that is to say it presents a "1" at its output to which the connection ds 525 is connected when the second state detector 22B, and this detector only, indicates that there is synchronization. The gate 27 has for its function to withdraw the pulse from the second count detector 19B and to release the field signal (by resetting the counter to zero) when this pulse occurs.

- In the non-synchronized state; Let it be assumed that a phase shift is effected in response to a change in the number of lines per field or a phase change without a change in the number of lines: in both cases the process of changing to the non-synchronized state will be the same. The register 42 stores a zero since the coincidence pulse coming from the gate 43 is not present at the moment at which the separate pulse occurs.

To ensure that the bistable trigger circuit 40, 41 changes state, it is necessary for one input of the gate 41, whose output has the value "0", to change to zero. The presence of a single zero at the output of the register 42 causes the output of the gate 48, which is a OR-gate, to change to "1", but this does not change the state of the gate 40 which has a zero at its other input.

As regards the component 47, which is an NAND-gate, seven of its inputs have still a "1" value and its output consequently does not change. The output of the gate 40 remains at "1" and the shifting operations of register 42 continue to be controlled every 625 half-lines.

Consequently, zeroes continue to be entered into the register 42 until the moment at which it will be full of zeroes, that is to say at the end of eight non-synchronized fields. The output of the gate 47 then changes to zero, the bistable trigger circuit 40,41 changes state and the output of the gate 40 changes to "O".

If also no coincidence at 525 lines has been registered, the output of the gate 30 remains at "O". The inverters 50 and 52 then supply "ones" and the two gates 51 and 53 supply "zeroes" to the connections ds 625 and ds 525. The output of the gate 49 which is connected to the connection ds and to an input of the gate 29 changes to "1".

The circuit 49 then indicates by means of this "1" that none of the two selection circuits is activated. A further input of the gate 29 is connected to the output of significance 512 of the counter. This is done for the safety of the output circuits 1 8 so as to ensure that the scan can never be shorter than 512 half-lines. If the count reached is higher than 512, a "1" is present at the output of significances 512 of the counter and a signal "1" conveyed by the gate 39 causes the appearance of a "O" at the output of the gate 29 and consequently also at the output of the gate 26, which causes the counter 15 to be reset to zero and consequently the field signal to be generated. Thus, the gate 29 has for its function to provide the separated pulse, transmitted by the gate 39, and to release the field signal when this pulse is produced.The circuit then no longer operates in the counting mode, but in the direct synchronization mode from the separated pulse.

It is possible that an exceptional burst of interference pulses will be recognized as a train of separated pulses and will generate "ones" at the two registers at the same time. The gates 40 and 30 then apply "ones" to at least one input of each gate 51 and 53 whose outputs are then both zero, the output of the gate 49 then being "1". The indicated state is the non-synchronized state and the separated pulse is utilized as described above, which renders synchronization possible when the interference pulses disappear.

If now a separated pulse occurs again in accordance with one of the two standards of 625 lines per field or 525 lines per field, at the arrival of a new separated pulse, the counter which has been reset to zero at the moment the preceding pulse was received shows a count of 625 or 525.

These counts cause the appearance of a "1" at the inputs of the gate 45 or 35, respectively, whose other input which is connected to the connection ds is also "1". This causes the appearance of a "1" at the output of the gate 45 or 35 and a "O" at the output of the gate 44 or 43 and a "1 " at the output of the gate 34 or 33. As a result thereof, a "1" is stored in the shift register 42 or 32. After eight fields, this register will thus be again filled with "ones" and the circuit 48 or 38 will apply a zero to the gate 40 or 30, which causes the bistable trigger circuit to change state which produces a "1". The system is then again in the synchronized state either at 625 lines or at 525 lines.

Fig. 5 shows some signals occurring in the circuit of Fig. 2 to provide a better understanding of the object of the arrangement of the abovedescribed circuit and more specifically, the difference between the synchronized and nonsynchronized states. The signal 2fH is the signal coming from circuit 11 and provides a pulse for each scanning half-line. The signal td is the signal which provides the separated pulse. The three diagrams within the bracket A represent the signals which appear in the synchronized state.

The signal ct indicates the counting state of the counter 1 5. Thanks to the circuit 1 9A, 28, 26 whose operation has been described in the foregoing, the appearance of the count 625 immediately triggers the reset-to-zero operation of the counter and consequently the count 625 is only very short-lived. This is of course also the case for the count 525 when the circuit operates in accordance with this standard. The signal S44 is the signal present at the output of the gate 44.

As described in the foregoing, this output has the value "0" during the zero count of the counter. At the instant 69, the separated pulse td appears and the signal at the output of the gate 43 has the shape indicated by S43. The arrow at the pulse td indicates the instant 70 at which storage into the shift register 42 is effected. A "1" is now registered.

The three diagrams within the bracket B represent the signals appearing in the state denoted the non-synchronized state here, but only when the separated pulse occurs again in accordance with any of the two standards, here, for example: 625 lines. The signals ct, S44 and S43 are defined as above. At the appearance of the count 625 the signal S44 changes to zero as described above, but the counter 1 5 is not reset to zero since the input of the gate 28 connected to the connection ds 625 is "O". At the instant 69 at which the separated pulse td appears, the signal S43 changes to "1". The counter is reset to zero at the instant 70 at which the pulse appears, thanks to the gates 29 and 26, as described in the foregoing.The reset-to-zero operation of the counter causes the signal S44 to change to "1" again but this reset-to-zero action is not instantaneous and is effected with the time delay indicated by two opposite arrows between the moments 70 and 71. As a result thereof, the signal 544 and the signal S43 do not show a transition until after this slight time delay after the instant 70 and at the recording moment 70 the signal S43 is still "1", and coincidence is registered.

The counter 1 5 which has the signal 2fH as its clock signal is incremented at the following line retrace and the counts 625 and 0 consequently have together a duration which is equal to the period of time of a half-line, and the following counts are the same, irrespective of the fact whether the indicated state is the synchronized or the non-synchronized state.

As has been described in the foregoing, the reset-to-zero action of the counter, which is triggered by either a predetermined count, in the so-called synchronized state (ds=0, ds 625 or ds 525=1) or by the pulse te supplied by the separated pulse td in the so-called nonsynchronized state (do=1, ds 625=ds 525), generates the pulse conveyed to the field scanning circuits. This is realised by means of the element 1 7 which supplies a signal when one of the bits of significance 1 6 to 51 2 does not have the "1" value. This element is, for example, provided by a NOR-gate having six inputs.The signal will then be supplied at all the counts, comprised between 0 and 15 that is to say during 16 half-lines, or a duration of 512 ys. This constitutes a shaping of the signal so as to adapt it to the field retrace drive in the scanning circuits 18(Fig. 1).

The circuit 1 9D supplies a "0." which resets the counter to zero at a count 656, so as to prevent in the absence of the separated pulse (owing to, for example, the absence of reception) the scanning circuits from being damaged by an excessive amplitude.

For the case in which it may happen that, at the beginning of the period of a non-synchronized state the separated pulse will arrive at an instant at which the count has not reached 512, the gate 26 will prevent the counter from being reset to zero. Let it be assumed that the number of halflines per field of the separated signal is 624 and that at the relevant instant the count is 511, which is the worst case. The counter will be reset to zero anyway at 656. The count will then be much lower at the arrival of the following separated pulse, since the counter has been reset to zero at 656 instead of at 624. It is reduced by 32. At the end of 1 6 fields the separated pulse will arrive in the window comprised between the counts 512 and 655 and the system will be synchronized as indicated above.

The field output stage 1 8 supplies a sawtooth deflection current whose amplitude is generally a function of the charging time of a capacitor which forms part of a sawtooth voltage generating circuit. This amplitude remains the same irrespective of the number of lines per field, on the condition that the field frequency is maintained constant. In the case of a synchronizing circuit designed to be suitable for use with a mixed number of lines "525 lines at 60 Hz,'625 lines at 50 Hz", it is advantageous to produce data to determine the value of the charging current of the above-mentioned capacitor as a function of the value of the number of lines.In its most simple form, such a circuit comprises a change-over switch by means of which it is possible to adjust the current for two values, the higher of these values corresponding to the shortest period, that is to say 60 Hz, this change-over switch being controlled by the signal ds 625 or by the signal ds 525.

The embodiment described here with reference to Fig. 2 is one of the numerous variations which may be conceived without departing from the frame work of the invention.

The synchronizing circuit described here permits inter alia the automatic adaptation to the two standards which are most widely used in the world, namely the 525-line standard and the 625-line standard. Variations for, for example, any other standard can be devised.

Moreover, further methods known to a person skilled in the art for recovering the field pulse from the signal supplied by the sync. separator 7 may be used. It may happen that the field pulse obtained is much longer than described in the above example. By means of digital differentiation the leading edge of this pulse may generate a shorter pulse, which is then utilized as in the above-described example. In the case in which an accurate phase relationship between the beginning of the separated pulse and the signal of the period 842 ns is not ensured, or if this signal was not available or when it is preferred not to use this signal, it is possible to obtain the sequence of the desired order of operations for controlling the coincidence, recording into the shift register and the reset-to-zero action of the counter by gate 29, by means of a series of bistable trigger circuits arranged in cascade provided in situ of the gate 39 between the connections td and te. It is alternatively possible to program the counter 1 5 by means of a microprocessor which then replaces the corresponding portions of the field synchronizing circuit. In view of the low rate of operation used such a realisation will not present any particular difficulties.

Claims

1. A method of generating a signal for driving the field deflection in a picture reproducing device, in which field pulses are obtained by counting half-line periods, a check being made as to whether there is coincidence between the appearance of a predetermined number of halfline periods panda separated field pulse recovered from a signal received by the picture reproducing device, a synchronized state being determined when there is such coincidence during a predetermined number of consecutive fields for generating, when this state has been determined, a counting pulse when the said predetermined number of half line periods appears, and to use this counting pulse to generate a field deflection driving signal, the separated pulse being used to generate the driving signal when the synchronised state has not been detected, characterised in that a check is also made as to whether there is coincidence between a second predetermined number of half-line periods and the separated field pulse, the synchronized state for each one of the predetermined number of halfline periods being stored and if this state is obtained for only one of these-two numbers of half-line periods the corresponding counting pulse is generated and utilized to generate the field deflection driving signal, whereas when the synchronized state is not obtained for either of these two numbers of half-line periods the separated pulse is used to generate the field deflection driving signal.

2. A method as claimed in claim 1, characterised in that the separated pulse is used to generate the field deflection driving signal when the synchronised state is obtained simultaneously for the two predetermined numbers of half-line periods.

3. A method of generating a signal for driving the field deflection in a picture reproducing device substantally as herein described with reference to the accompanying drawings.

4. The invention also provides apparatus for generating a signal for driving the field deflection in a picture reproducing device in which field pulses are obtained by counting half line periods, said apparatus comprising means for checking whether there is coincidence between the appearance of a predetermined number of halfline periods and a separated field pulse recovered from a signal received by the picture reproducing device, means for determining when there is such coincidence during a predetermined number of consecutive fields for generating, when this state has been determined, a counting pulse at the moment the said predetermined number of halflines appears, and for using the counting pulse to generator a field deflection driving signal or for using the separated pulse to generate the driving signal when such coincidence has not been detected, characterised in that said apparatus further comprises means for checking whether there is also coincidence between a second predetermined number of half-line appears, and for using the counting pulse to generate a field deflection driving signal or for using the separated pulse to generate the driving signal when such coincidence has not been detected, characterised in that said apparatus further comprises means for checking whether there is also coincidence between a second predetermined number of halfline periods and the separated field pulse, means for storing information related to the said coincidence for each one of the predetermined number of half-line periods, means for producing the corresponding counting pulse if coincidence is obtained for only one of these two numbers of half-line periods and for generating the field deflection driving signal therefrom, and means for causing the separated pulse to be used to generate the field deflection driving signal should such coincidence not be obtained for either of these two numbers of half-line periods.

5. A circuit for putting the method as claimed in claim 1 into effect, comprising: - a half-line period counter, - a first count detection circuit to produce a pulse which corresponds to the first predetermined number of half-line periods, - a first state detector for detecting the synchronized state corresponding to the first count detection circuit and for generating the counting pulse when this state is detected, is characterised in that it further comprises:: - a second count detection circuit, coupled to the counter, for producing a second pulse which corresponds to the second predetermined number of half-line periods, - a second state detector for detecting the synchronized state corresponding to the second count detection circuit and for generating the counting pulse when this state is detected, - a selection circuit connected to the first and second state detectors and operative when the first or the second state detector indicates the synchronized state and which triggers when the synchronized state is detected the field driving signal by means of the corresponding counting pulse, - and a gate which receives the separated pulse and is connected to the output of the selection circuit to trigger the field driving signal by means of the separated pulse when the selection circuit is not operative.

6. A circuit as claimed in claim 5, characterised in that the selection circuit is not operative when the two state detectors are simultaneously in the synchronised state.

7. A circuit as claimed in claim 6, characterised in that the selection circuit comprises an OR-gate a first input of which is connected to the output of the first state detector while a second input is connected to the output of the second state detector, the output of this gate providing the output of the selection circuit.

8. A picture reproducing device comprising a circuit or apparatus for generating a signal for driving the field deflection as claimed in any of the claims 4 to 7.

9. A circuit or apparatus for generating a field deflection driving signal substantially as herein described with reference to the accompanying drawings.

10. A picture reproducing device substantially as herein described with reference to the accompanying drawings.