FR2535562A1 - METHOD AND CIRCUIT FOR GENERATING A FRAME SYNCHRONIZATION SIGNAL IN AN IMAGE RECEIVER - Google Patents

Abstract

IN A DIGITAL TIME-BASED TELEVISION PROVIDING INDIRECT FRAME SYNCHRONIZATION BY COUNTING THE NUMBER OF LINES, WHERE A COINCIDENCE BETWEEN THE APPEARANCE OF A DETERMINED LINE COUNT AND A DIRECT SYNCHRONIZATION PULSE, THE DETECTION OF A ANOTHER COINCIDENCE BETWEEN THE APPEARANCE OF ANOTHER ACCOUNT AND THE SAID DIRECT PULSE ALLOWS TO OPERATE IN INDIRECT SYNCHRONIZATION FOR TWO DIFFERENT STANDARDS. THE SYSTEM INCLUDES A SINGLE COUNTER 15, TWO STATUS DETECTORS 22, INDICATING THE SYNCHRONISM STATES, A LOGICAL ANALYSIS CIRCUIT 23 SELECTING THE SYNCHRONIZATION SOURCE TO BE USED AND WHICH CONTROLS CIRCUIT 20 FOR RESETTING THE COUNTER.

Description

"Process 6 dice and circuit to generate a synchronization signal

  frame position in an image receiver ".

  The invention relates to a method for generating a frame synchronization signal in a receiver.

  images equipped with digital circuits in which

  holds frame synchronization pulses per

  age of scan lines in which it is checked whether there is a coincidence between 19 appearance of a pred count 6 termin 6 of half lines and a so-called "discriminated" frame pulse

  which is extracted from a signal received by the receiver in pro-

  coming from an external organ, and in which one d 6 ends a state called "Isynchronous" when the aforesaid coincidence takes place during a predetermined number of successive frames

  to generate, when said state is noted S, an im-

  so-called counting pulse at the appearance of said account pr 8 determinate of half-lines and use it to trigger a frame synchronization signal o

  The invention also relates to a nu-

  meric to generate a synchronization signal

  me in a r 6 image receiver, comprising: a half-line counter

  a first account detector circuit, for

  set a pulse corresponding to the counting of a determined number of scanning lines a first state detector to indicate that a state of synchronism is obtained when a coincidence

  between the pulse supplied by the sensor circuit

  te and an impulse called Odiscriminée "extracted from a si-

  received from an external organ by the receiver, a

  has been detected a number of times in a row.

  a first door to pick up the momentum of the

  account detector circuit and trigger a syn-

  frame timing when this pulse occurs

  a second door to pick up the discrete impulse

  undermined and trigger the frame synchronization signal

when this impulse occurs.

  The current trend in electronic circuits, and in particular in televisions, is to seek to digitally process the maximum of signals, because this technique makes it possible to avoid the use of components such as capacitors or precision resistors and, therefore, it becomes possible to integrate functions

  more and more complete on a single semi-insert

  conductor, which reduces the amount of interconnections per printed circuit Due to the removal of components

  costly and reduced printing circuit areas

  and the number of semiconductor shoemakers, economical

  very important things can be done.

  It is, moreover, for the additional purpose

  improve the insensitivity to synchronous parasites

  We have sought to obtain this frame at the

yen of a line count.

  A number of achievements have seen the

  day in this area, achievements based on the same principle

  -base of base, consisting in generating a "top" of synchronization-

  sation by means of a line counter, for a predetermined line count In the case of the European standard with 625 lines, one generates all of the 312 5 lines, that is to say all the 625 half-lines, and we use this

  top instead of the above discriminated impulse.

  A problem then arises, mainly in two cases: during a change of phase of the frame scan, which

  - can occur for example during a change of camera -

  ra, you must be able to initialize the counter again in accordance with the new phase, if the frequency is not that expected, for example

  upon receipt of a standard different from that pre-

  seen, it is necessary that synchronization occurs anyway.

  The idea retained by all the embodiments of the prior art is to determine if the synchronization is correctly defined by line counting, by means of

  of a search for coincidence between the discriminatory impulse

  born and counting impulse, and go back to the use-

  direct action of the discriminated pulse, in case the

  counting pulse is not correct Of course, in order to eliminate the action of parasites, we wait until an absence of coincidence occurs several times

  more before deciding that we are in a state of non

  synchronism. A circuit offering these characteristics is described for example in French patent application No. 2 208 261 This circuit has the disadvantage that, when

  of the reception of a program whose number of half

  lines per frame is different from 625, it cannot work

  Note that in direct synchronization using the

  drive discriminated with the classic drawbacks of this operating mode, namely sensitivity to noise and poor operation in the event of a weak signal providing a poor signal-to-noise ratio.

  circuit therefore does not allow synchronized operation

  counting only for one standard -

  The object of the invention is to provide a

  proc 6 d & and a circuit to generate a syn-

  frame timing which is capable of operating in synchronization by counting, also called indirect, with

  at least two existing standards, and this' without intervention

tion of the user.

  The inventive concept of the invention is based on the idea of taking a second account from the same counter, also testing the coincidence between

  this second account and the discriminated impulse, and con-

  stun the two coincidental states simultaneously

  laying on both counts, during syn-

  direct chronization, in order to automatically determine if we can return to synchronization by counting for

one of the two accounts.

  A method according to the invention is thus notably

  remarkable in that, also checking for another predetermined account of half-lines if there is a corner

  coincidence with the discriminated frame pulse, we record

  records the synchronism state for each of the two comp-

  tes, and in that if the state indicates a synchronism for

  only one of the two accounts generates the accounting impulse

  related age and is used to trigger the frame synchronization signal, while if the state indicates, either

  synchronization for the two accounts, i.e. no synchronization

  nism, we use the discriminated impulse to trigger

  the frame synchronization signal.

  A circuit according to the invention is in particular re-

  markable: in that it further comprises: a second account detector circuit connected to the

  same counter to provide another corresponding impulse

  in counting another predetermined number of half

scan lines.

  a second state detector to indicate a state

  of synchronism corresponding to the coincidences between the im-

  discriminated pulse and the second circuit pulse

account holder.

  a first selection circuit activated if the first

  state detector, and only the first, indicates a syn-

chronism.

  a second selection circuit activated if the two

  xth status detector Sr, and only the second, indicates a synchronism a circuit to indicate if neither of the two selection circuits is activated a third door to take the pulse of the

  second account detector circuit and trigger the

  general frame synchronization when this pulse occurs,

and in that -

  an entrance to the first door is connected to the exit

  tie of the first selection circuit, an entry of the third

  sth gate is connected to the output of the second selection circuit, and an input of the second gate is connected to the output of the circuit which indicates whether neither of the two circuits

selection is activated.

  The advantage of the method according to the invention and of the circuit constituting a form of implementation of said

  method, is that it allows the operation of a

  tor of images in synchronization by counting for two different standards, and that this is obtained with a single counter, and therefore with an advantageous economy of o 5 means This circuit can be used without modification or addition of external elements for the two main standards existing in the world It can therefore be mass produced larger and cost less.

  The following description next to

  attached drawings, all given by way of example, will make it clear how the invention can be implemented: FIG. 1 is a block diagram of a television receiver fitted with the circuit according to the invention FIGS. 2 and 3 show details of

circuit according to the invention.

  Figures 4 and 5 illustrate the appearance of some signals produced in the circuit according to the invention.

  In FIG. 1, an antenna 1 receives a signal

  - TV signal and provides it to a part of detective

  high frequency 2 Then the signal detected by

  comes on the one hand to the sound part 3 of the receiver, and on the other hand to a video amplifier 4 whose output provides a composite video signal This signal is supplied to a part 5 which extracts the components necessary for controlling the tube cathodic 6 It is also supplied

  to a synchronization separator 7 which provides

  line synchronization pulses to a phase detector 8 whose output voltage is capable of influencing an oscillator il by means of a filter 9 and a reactance circuit 10, The oscillator It generates a signal the frequency of which is equal to twice the line frequency and is therefore equal to 2 f H ', that is to say 31,250 Hz when receiving a signal according to the standard at 625 lines per complete image with two frames

  interline per image and 50 images per second One

  tre possibility is that the oscillator It generates a voltage at frequency f 9 this frequency then being doubled The voltage at frequency 2 controls a frequency division circuit 12 in which said frequency

  is halved, the signal obtained being supplied to the

  line output stage 14 via a pulse shaping stage 13 The line output stage

  14 supplies deflection current to a deflection coil

  tion- (61) and returns the return pulse to the

phase 8.

  All of these circuits are well known to those skilled in the art. They are here advantageously produced according to digital circuit techniques, at least as far as

  relates to elements 8 to 13 In particular, the oscilla-

  tor It can generate the frequency 2 f H from a higher frequency oscillation, for example at 38 M Hz,

  some division reports of which provide multi-

  whole lines of the line frequency, and in particular a

  842 n S period signal, a use of which will be seen below

reading.

  The digital discriminator 21 allows ex-

  process the signal received by the antenna and separated by the separation

  rator 7, the "discriminated" frame synchronization pulse.

  This discriminator uses the 842 n S period signal supplied

  by oscillator 11, as mentioned above

  sus. This signal triggers every 842 n S the input of a sample of the separate signal into the serial input of a

  shift register, for example at 24 bits The pre-

  sents on the parallel outputs of this register constitute a word When a frame pulse appears in the separate signal, this word has a very specific configuration, characteristic of this pulse It can present for example, at a precise instant after the start of the impulse,

  12 bits at 1 followed by 12 bits at zero Detection of this-

  configuration using a set of doors triggers

the "discriminated" signal.

  This occurs during a single intro cycle

  duction of the samples in the register, and the "discriminated" top frame will therefore have a theoretical duration of 842 n S Le

  detail of the circuits of the discriminator 21 has not been re-

  presented so as not to weigh down the figures because it is

  naked and can be easily carried out by a person skilled in the art -

  Frame synchronization can be obtained

  by counting pulses at 2 f in a binai counter

H

  10-bit re (15) connected to an image shaping circuit

  pulses 17 and to a frame output stage 18 which supplies the vertical deflection current to a deflection coil

(61).

  The circuit comprises a first state detector 22 A provided with a coincidence detector which detects a coincidence between a so-called "discriminated" frame pulse

  extracted by the discriminator 21 from the signal received on the year

  tenne 1 coming from an external organ and pretreated by circuits 2 4, 7? and a pulse supplied by a first count detector circuit 19 A during the appearance of a predetermined count of semilines at the output of the counter 15 This circuit 22 A detects if the coincidence takes place during a determined number of successive frames,

  in which case it records a state of synchronism and deli-

  sees a signal that the image receiver is in

  a "synchronous" state This synchronous state signal is trans-

  set to reset circuit 20 to indicate to it that it must generate a so-called "counting impulse" I when the aforementioned predetermined half-line count appears

  and use it to trigger the synchronization signal

  We have chosen in the embodiment described here to make this signal appear by resetting the counter 15 o The counting pulse triggers

  done resetting the counter 9 'which generates the if-

  g of synchronization transmitted to the scanning circuit

vertical 18.

  A second account detector circuit 19 B úEurns to a second state detector circuit 22 B an impulse for apprmimentation of another predetermined account at the output of the same counter 15 o This state detector circuit 22 X comprises a detector coincidence which detects a coincidence between the discriminated pulse and the appearance of this other predetermined account, and it records a synchronous state for this other account. A circuit 23 determines whether the synchronous state is

  obtained for only one of the two accounts and in this case indi-

  that at reset circuit 20 that it should generate a coupling pulse for this account, and use it to

  trigger the frame synchronization signal The circuit

  cooked 23 also determines if the synchronous status is obtained for both accounts, or if it is not obtained for any of the

  two, and in these cases tells circuit 20 that it should use

  read the discriminated pulse to trigger the signal

frame synchronization.

  Figure 2 allows you to enter more into the

  details of operation by providing an example of a diagram for circuits 19, 20, 22, 23 It goes without saying that all other equivalent logical combinations possibly

  better suited to a technology chosen for a manufacturing

  tion, would not depart from the scope of the invention.

  Circuit 20 consists of an AND gate (26) and three NAND gates (27,28, 29) The output of gate 26 is connected to the reset input of counter 15, three of its inputs are each connected to the output of one of the NAND gates 27, 28, 29 and a fourth input is connected to the circuit 19 D which provides a level "O" for the account 656 of the counter Uhe input of the gate 27 is connected to the output of circuit 19 B which provides a level "1" 'for account 525 and the other input is connected to a connection referenced ds 525 An input of gate 28 is connected to the output of circuit 19 A which provides a level "1" for account 625, and the other input is connected to a connection referenced ds 625 An input of gate 29 is connected to the weight output 512 of counter 15, another

  input is connected to a connection referenced ds and an

  the input is connected to a connection referenced te The first account detector circuit 22 A consists of two AND gates (45, 46), two NOR gates (43, 44), a shift register (42) two circuits 47, 48 to recognize respectively that all the parallel outputs of the register 42 are at "O", or are at "1", and a flip-flop formed from two NAND gates (40,41) in cross coupling An input of door 46 is connected to the output of circuit 19 C which provides a level "1" for the zero count of the counter, and the other input is connected to the connection ds 6250 An input of door 45 is connected to connection ds and the other to the aforementioned output of circuit 19 A An input from door 44 is connected to the output from door 46, and the other input is connected to the output from door 45 An input of door 43 is connected to the output of door 44 and the other input is connected to a connection referenced td The output of door 43 is

  connected to the serial input of the shift register 42 whose input

  clock connection is connected to the connection te o The two circuits

  cooked 47, 48 have their inputs connected to the parallel outputs

  or register 42 The outputs are connected to the inputs of

  flip-flop 40, 41 of which only one output is used.

  Circuit 22 B is similar to circuit 22 A, and all internal components are referenced by numbers

  from 30 to 38, the number of units being the same as that -

  corresponding elements of circuit 22 A The only diff-

  Connection references are that an entry from door 36 is connected to the connection ds 525 (instead of ds 625 for door 46) and that an entry from door 35 is connected to

  the output of circuit 19 B (instead of 19 A for gate 45).

  The circuit 23 consists of three NOR gates 49, 51, 53 and two inverters 50, 52 One input of the gate 51 is joined to the output of the rocker 30, 31 and the other is joined to the output of the flip-flop 40, 41 via an inverter 50 An input of the gate 53 is joined to the output of the flip-flop 40, 41, and the other is connected via an inverter 52 to the output of the flip-flop 30, 31 The inputs of the door 49 are each assembled at the exit of one of the doors 51, 53 The connection ds 625 is connected to the exit of door 51, the connection ds 525 to the exit of door 53, and the connection of to the exit of the door

* 49 o.

  The circuit is capable of operating by accounting

  ge in the so-called "synchronous" state for standards at 625

  lines and at 525 lines, and in synchronization by the impul-

  sion discriminated in other standards, or transiently at the time of a change of standard, or a change of phase of line scanning, which may occur

  for example when changing the camera on the broadcast.

  Elements 17, 19 A to 19 D, 37, 38, 47, 48 of FIG. 2 are all intended to provide a signal for a certain configuration of their inputs. A typical diagram of this kind of circuit is represented in the figure. 3 The inputs of this circuit come from the parallel outputs of a counter or a register Five inputs of the NOR gate 24 are connected to the bits of weight 2, 4, 8, 128, 256 and six inputs of the AND gate 25 are linked to the bits of weight 1, 16, 32, 64, 512 When the latter are at 1 and the previous ones at zero, the output of gate 24 is at 1, all the inputs of gate 25 also and a signal 1 is provided at the exit of gate 25 In the example given here this is obtained for a count of 625 (i.e. 512

  + 64 + 32 + 16 + 1 corresponding to the bits linked to the gate

  25) It is easy for those skilled in the art to imagine other

  very similar circuits to detect N 9 any comp-

  te Thus in FIG. 2, the elements 19 A, 19 B 19 C are constituted in this way in order to detect

  accounts equal to 625, 525 and zero respectively.

  cooked 17, 19 D, 37, 38, 47, 48 are of the same kind but sim-

  folded and will be described later.

  The operation of the two registers 32, 42 and of the NOR gate-39 is illustrated by FIG. 4.

  two signals td and c are applied to gate 39 The si-

  gnal td presents the above discriminated pulse, and the signal c is the aforesaid signal of period 842 n S supplied by the oscillator 11 The output of the gate 39 provides the signal te whose rising edge (70) is behind the falling edge (69) of td The bearing at "O" l of the signal td applied to doors 43, 33 allows application by

  these of a coincidence signal to be recorded, at the

  data entry of registers 42, 32, and the rising edge

  signal triggers recording at the specified time

  qué by an arrow on td, having therefore left the time necessary for the state to establish in a secure manner before recording. il Reset the counter seeffectue on transition to zero Gate 26 generally has all its inputs at "1" and its output also 9 and it is when at least one of its inputs changes to "O" that the counter is reset The input connected to circuit 19 D only goes to zero for account 656 The one connected to doors 28 and 27 only goes to zero for accounts 625 or 525 and only if ds 625 or d 5525 are at " , i "c The one connected to gate 29 does not go to zero until the appearance of the pulse te if

  the count is greater than 512 and that ds = "1".

  To explain in more detail the operation of the circuits of figure 2, two cases are to be considered according to whether the circuit is in the synchronous state or in the state

not synchronous.

  In the synchronous state, for example in 625 li-

  In a way that will be explained later,

  the state detector 22 B provides an "O" 1 on its output,

  saying that there is no synchronism in 525 lines This output is connected to an input of door 51 of circuit 23 In the same way, detector 22 A provides a "t 1", indicating that there is synchronism in 625 lines This "1" is transformed into the O "by the inverter 50 As a result, the NOT-OR po 51 having its two inputs at" O "provides a" '1 "at the output, which is applied & at doors 49, 28 and 46 by the connection ds 625 The circuit consisting of the inverter 50 and the door 51 thus constitutes a first circuit of

  selection activated if the first status detector 22 A, and only

  Lement him, indicates a synchronism, This circuit then has a "1 'l on the connection ds 625, it follows that the NOR gate 49 provides an" O "output on the connection ds and blocks the AND gate 29, who does not play so

none r 81 e.

  when the account 625 is reached, a "1" t appears

  on output 625 of circuit 19 A pro count detector

  duisant an "O" -at the exit of the NAND gate 28, This "O" causes the output of the AND gate 26 to change to "O" (as described above, its four inputs were all "* in previously) and thus triggers the reset of the counter 15 The r 8 le of the gate 28 is therefore to take the impulse from the count detector circuit 19 A and trigger a frame synchronization signal when

this impulse occurs.

  the zero count being thus reached, the circuit 19 C provides a "1" which is transmitted by the gate 46, followed

  of NOR gate 44 which therefore provides an "O" If an im-

  discriminated drive "10" 1 is present on td at this time

  gate 43 provides a t which is recorded in the re-

  shift register, according to a sequence which will be explained with reference to FIGS. 4 and 5 Since the circuit is in the synchronous state, this had already occurred in all the previous frames and the register was filled with 1 Nothing

  is therefore not changed, and the cycle can repeat itself indefinitely

is lying.

  If the circuit was in the synchronous state but in 525 lines, the operation would be the same provided

  to replace in the description above the elements

  22 A, 22 B, 50, 51, 28, 46, ds 625, 44, 43 by the elements

  respectively 22 B, 22 A, 52, 53, 27, 36, ds 525, 34, 33.

  In particular, the inverter 52 and the door 53 constitute

  a second activated selection circuit, i.e. pre-

  feeling a "1" on its output to which is connected the connection ds 525, if the second state detector 22 B, and only it, indicates a synchronism The door 27 has for

  r 8 le to take the pulse from the second counter detector

  te 19 B and trigger the frame synchronization signal (by resetting the counter) when this pulse occurs. In the non-synchronous state:

  Suppose that a phase shift occurs by following

  te of a change in the number of lines per frame or of a phase change without changing the number of lines the process of transition to non-synchronous state will be the same in both cases Register 42 registers a zero because the pulse of coincidence from gate 43 is not present at the time of the shift, i.e. when

  the discriminated impulse arises.

  For the flip-flop 40, 41 to change state, it is necessary that an input of the gate 41 whose output is at "O" itself passes to zero Or, the element 48 is constituted by a gate NON- AND with eight entries and the element

  47 consists of an OR gate with eight inputs The pre-

  sence of a single zero at the output of register 42 therefore makes the output of element 48 go to "1", but this does not change

  not the state of gate 40 which has a zero on its other end

* very. As for element 47, it still has seven entries

  to "1" and its output therefore does not change o The output of the gate

  te 40 remains at "1" and the d 6 calibrations of register 42 conti-

  nude to be ordered every 625 half-lines As a result, z 6 ro will continue to enter register 29 until it becomes full of "O", that is to say after eight non-synchronous frames Then, the output of element 47 goes to zero, flip-flop 40, 41 changes state,

  and the exit from gate 40 goes to "O" o.

  If no 525 line coincidence has been 6

  registered either, the output of gate 30 remained at "O". So the inverters 50 and 52 provide "1" and

  the two doors 51 and 53 provide "O" s on the conne-

  xions ds 625 and ds 525, The output of gate 49 connected to the connection ds t to a loss input 29 goes to "1" Circuit 49 therefore indicates with this "1" that neither of the two selection circuits n 'is activated Another entry

  of door 29 is connected to the weight output 512 of the comp-

  This is done for the safety of the output circuits.

  tie 18 so that the sweep can never be more

  short than 512 half-lines o If the count reached is greater than 512, umn'l "is present at the weight output 512 of the counter, and a

  signal "1" 'from door 39 results in the appearance of an "O O" at the exit from door 29 and therefore also at exit from door 26, which results in delivery

  at zero of counter 15, and therefore generates the syn-

  frame timing Thus gate 29 has the role of taking the discriminated pulse transmitted by gate 39, and of triggering the frame synchronization signal when this pulse occurs O Then the circuit does not

  no longer works by counting, but by di-

  rect from the discriminated pulse.

  It may be that an exceptional burst of pa-

  rasites, taken for discriminated impulses, generates 11111 on both registers at the same time So the doors

  40 and 30 apply "1" to at least one entry of each

  one of doors 51 and 53, the outputs of which are therefore all

  two to zero, the output of gate 49 therefore being at "1".

  The indicated state is not synchronous, and the pulse discriminates

  née is used as above, allowing syn-

  immediate chronization as soon as the parasites disappear.

  If now the discriminated pulse appears again according to one of the two 625 line standards

  per frame or at 525 lines per frame, upon arrival of a new

  old pulse discriminated, the counter, which was reset to zero during the previous pulse, has a count of 625 or 525 respectively The counts respectively 625 or 525 cause the appearance of a "1" respectively on the inputs of the doors 45 or 35, of which the other entry

  connected to the ds connection is also at "1" This

  does the appearance of a "'1" at the exit of the respective doors-

  45 or 35, and an "O" at the exit of the respective doors

  44 or 34 and a "1" at the exit of the respective doors

  vement 43 or 33 Therefore a '1 I "is recorded in the shift register respectively 42 or 32 After eight -25 frames this register will therefore be filled with 1 again and circuit 48 respectively 38 will provide a zero at the gate

  respectively 30 causing the rocker which provides

will then denote a "1".

  The system thus finds itself in the syn-

  chrone, either 625 lines or 525 lines.

  Figure 5 illustrates some of the signals encountered

  very in the circuit of figure 2 to better understand

  take the object of the circuit arrangement described above

  known and in particular the difference between the syn-

  chromatic and not synchronous The signal 2 f H is that coming from circuit II and presents a top for each scanning half-line The signal td is always the signal which has the discriminated pulse The three diagrams placed in the brace A represent signals appearing in the synchronous state The ct signal indicates the counting state

  of the meter Thanks to circuits 19 A, 289 26 whose function

  operation has been described above, the appearance of account 625 immediately triggers the reset of the counter

  and therefore account 625 has only a very brà-

  ve Of course it is the same for account 525 in the case of operation according to this standard The signal S 44 is that at the output of gate 44 As has been explained

  higher, it is at "O" during the zero count of the counter.

  At the instant 69 appears the discriminated impulse td and the

  signal at the output of gate 43 at the speed indicated by S 43.

  The arrow on the discriminated pulse indicates the instant 70 where the recording is made in the shift register

  42 It is therefore a "1" which is registered.

  The three diagrams placed in the brace B represent nt signals appearing in the state indicated as not synchronous but whereas the discriminated pulse appears again according to any one of the standards, for example here: 625 lines The signals and , S 44 and S 43 are defined as above When account 625 appears

  signal S 44 goes to zero as described above

  above, but the counter is not reset since the input of gate 28 connected to the connection ds 625 is at "O" At the instant 69 o appears the discriminated pulse td the signal S 43 goes to t " l ", The counter is reset to zero

  at instant 70 o there appears the impulse te, thanks to the

  tes 29, and 26 as described above Resetting the counter to zero causes the signal 544 to go back to "1" but this reset is not instantaneous and takes place within the time indicated by two arrows facing a face between times 70 and 71 o As a result, the signal S 44 and the signal S 43 only present a transition after this slight delay following time 70, and at time 70 of the recording the signal S 43 is still at "1", and a coincidence is recorded o The counter having as clock the signal 2 f Hl is incremented at the next line feed, and the accounts 625 and O therefore last together for half a line, and the following accounts are the same whether you are or

16 2535562

  not in the state indicated as synchronous.

  As described above, this is the re-

  counter reset, triggered either by a countdown

  finished, in the so-called synchronous state (Ws = 0, ds 625 or ds

  525 = 1) either by the impulse te coming from the impulse dis-

  td in the so-called non-synchronous state (ds = 1, ds 625 = ds 525), which generates the synchronization pulse transmitted to the frame scanning circuits This is obtained by means of element 17 which provides a signal when none of the bits of weight 16 to 512 is at "1" This element consists for example of a NON-O Utà gate with six inputs Le

  signal will therefore be provided for all accounts included in

  be O and 15, that is to say for 16 half-lines, i.e.

  duration of 512 1 us This constitutes a formatting of

  gnal-to adapt it to the return-frame command in the

scanning circuits 18 (Figure i).

  The circuit 19 D provides a signal "O" which resets the counter for a count 656 to zero, in order to prevent that

  the absence of discriminated impulse (due for example to the

  reception) the scanning circuits are not

  deteriorated by excessive amplitude.

  In the event that by chance, at the start of the non-synchronous state period, the discriminated pulse arrives at an instant or the count has not reached 512, gate 29 would prohibit resetting the counter Suppose that the number of half lines per frame-of the discriminated signal is 624, and that at the instant in question the count is 511, which is the worst case The counter will be reset to zero

  anyway at 656 The account will therefore be weaker upon

  of the next discriminated impulse, since the comp-

  tor will have been reset to 656 instead of 624 It will have

  decreased by 32 After 16 frames, the discrete pulse

  born will arrive in the window between accounts 512 and 655 and the system will synchronize as indicated above, The output stage frame 18 provides a current

  sawtooth sweep whose amplitude is generally

  ral function of the charging time of a capacitor This amplitude therefore remains the same regardless of the number of lines per frame, provided that the frame frequency is maintained In the case of a circuit designed especially for the purpose of mixed use "'525 lines at 60 Hz / 625 lines

  at 50 Hz ", it is advantageous to provide said output stage

  tie 18 a data to adjust the amplitude of the charge current of the capacitor in fctiond the value of the number of lines In

  its simplest form such a circuit includes a commu-

  tator allowing the adjustment of the current for two values this switch being controlled by the signal ds 625 or by the

signal from 525.

  The embodiment described here with reference to FIG. 2 constitutes one of the numerous variants which

  can be imagined without departing from the scope of the invention.

  For example, if the circuit described here allows among other things automatic adaptation to the two standards

  most widespread in the world, namely those at 525 li-

  genes and at 625 lines we can imagine variants for

any other standard.

  In addition - other known methods of the hom -

  me of the trade to extract the discriminated frame pulse from the signal from the separator 7 can be used It can be done while the discriminated frame pulse

  is much longer than in the example described above

  above By means of a digital differentiation, the leading edge of this pulse can generate a shorter pulse, which is then used as in the example described above In case a precise phase relationship between the start of the discriminated pulse and the signal of period 842 n S would not be ensured, or else if this signal was not available or it is preferred not to use it it is possible to obtain the succession in the desired order of the operations of contr 8 coincidence, recording in the shift register and resetting the counter

  through door 29, by means of a series of cascules

  of introduced in place of door 39 between the connectors

xions td and te.

Claims (2)

CLAIMS:   1 Method for generating a sync signal   frame framing in an image receiver equipped with   digital cooked, in which we get pulses of   frame synchronization by counting scan lines   ge, in which we check if there is a coincidence between the ap-   appearance of a predetermined account of half lines and an im-   so-called "discriminated" frame pulse which is extracted from a   signal received by the receiver from an ex-organ   and in which a state known as "synchro-   ne "when the above coincidence takes place during a predetermined number of successive frames, to generate, when said state is observed, a so-called counting pulse at the appearance of said predetermined half-line count and use it to trigger a signal frame synchronization, characterized in that, also checking for   another predetermined half-line count if there is a corner   coincidence with the discriminated frame pulse, we record   be the synchronism state for each of the two accounts, and in that if the synchronous state is obtained for only one   from the two accounts, the counting pulse is generated   rent and it is used to trigger the signal of Eynchro-   frame nisation, whereas if the synchronous state is obtained   naked for both accounts, or if it is not obtained for either, we use the discriminated pulse to trigger   the frame synchronization signal.   2 Digital circuit for generating a frame synchronization signal in an image receiver, comprising: a half-line counter (15) a first account detector circuit (19 A) for   provide a pulse corresponding to the counting of a name-   determined bre of scan lines.   a first state detector (21 A) to indicate   that a state of synchronism is obtained when a coincidence   dence between the pulse supplied by the count detector circuit and a so-called "discriminated" pulse extracted   of a signal received from an external organ by the reception   has been detected a number of times consecutively   ves. a first gate (28) for picking up the pulse from the counting circuit and triggering a frame synchronization signal when this pulse occurs a second gate (29) for picking up the discriminated pulse and triggering the frame synchronization signal when this pulse occurs, characterized in that it further comprises: a second circuit (19 B) linked account detector   to the same counter (15) to provide another pulse   responding to the counting of another predetermined number of scanning half-lines, a second state detector (22 B) for indicating a state of synchronism corresponding to the coincidences between the discriminated pulse and the second circuit pulse account detector.   a first selection circuit (509 51) activated if the first state detector (22 A) and only the first indicates synchronism, a second selection circuit (52, 53) Wctivated if   the second state detector (22 B) and only the second   tells me a syncironism a circuit (49) to indicate if no selection circuit is activated a third door (27) to take the impulse from the second circuit (19 B) account detector and trigger   the frame synchronization signal when this pulse sion occurs, and in that-   an input of the first door (28) is connected to the output of the first selection circuit (51), an input of the third door (27) esg connected to the output of the second   selection circuit (53), and an input of the second gate   te (29) is connected to the output of the circuit (49) which indicates whether neither of the two selection circuits is activated