GB2105538A

GB2105538A - Television tuning system

Info

Publication number: GB2105538A
Application number: GB08133055A
Authority: GB
Inventors: Pietro Belisomi
Original assignee: Indesit Industria Elettrodomestici Italiana SpA
Current assignee: Indesit Industria Elettrodomestici Italiana SpA
Priority date: 1978-05-22
Filing date: 1981-11-03
Publication date: 1983-03-23
Also published as: GB2105538B

Abstract

A circuit arrangement is provided for tuning into a television signal from among a number of radio-electric signals receivable on a television set which is supplied by a television power supply subject to interruption. The arrangement includes a random access memory 12 comprising a number of cells for storing data relative to the television signals to be presented in the event of the television power supply being cut off. Conditioning means 14, 15 are provided for preventing modification of the contents of the memory by incoming signals during transient states caused by loss and/or return of the television power supply. A battery 13 maintains a d.c. supply to the memory 12 in the event of a power cut. Means 14, 15 are disclosed in detail as 105 and 80, Fig. 6 where an signal from the integrator circuit 85, 86 and 87 of means 15 is fed to means 14 to provide signals to disactivating input CD, read disabling input NR and write disabling input NW to prevent corruption of the contents of the memory during the transient states. <IMAGE>

Description

SPECIFICATION Television tuning system The present invention relates to a circuit arrangement for tuning into a television signal from among a number of radioelectric signals receivable on a television set.

A system commonly used in television receivers for tuning to required channels is the so-called FREQUENCY SYNTHESIZER system. This system, made possible by the advent of integrated circuits, offers a number of advantages over other known systems, such at the conventional potentiometer type MECHANICAL MEMORY systems and the more recent so-called VOLTAGE SYNTHESIZER systems. The frequency synthesizer system is fully electronic enabling any channel to be called up directly by the user who formulates the channel number on a keyboard or other device. The system usually consists of a quartz-controlled reference oscillator, a phase lock loop, a programmable divider and a computer which supplies the number sent to the programmable divider in response to the number of the channel set by the user.

Thanks to the phase lock loop, for each channel number set by the user, the frequency of the local oscillator on the set is kept so stable and accurate that the set is tuned with great precision to the corresponding channel signal. For further details about frequency synthesizer tuning systems, refer to the article entitled "A Frequency Synthesizer for Television Receivers" by E. G. Breeze, published in the November, 1974 issue of the "Transactions BRT" magazine, or "Digital Television Tuner Uses MOS LSI and Non Volatile Memory" by L. Penner, published in the April 1, 1976 issue of "Electronics".

The frequency synthesizer system lends itself well to a number of different modes of television channel tuning:~ ~direct selection by formulating the required channel number as described above (television channels are numbered: for example, in the European C.C.I.R. standard, VHF band channels are numbered from 2 to 12 and UHF band channels from 21 to 69; in the American standard, VHF channels are numbered from 2 to 13 and UHF from 14 to 83).

~memory selection: each of a certain set of keys corresponds to a preselected and memorised channel; ~automatic scanning of all the channels of a given standard, or of all the channels contained in the memory or continuous scanning of all the frequency bands involved.

The first application enables immediate, direct selection of any one of the channels in the relative standard (60 in Europe, 82 in America).

The second enables faster detection of one of a limited number of preferred channels.

The third is a fast, simple way of finding out which standard channels can be received, which channels have been memorised and whether other broadcasting stations exist on non-standard frequencies such as the private broadcasting stations in Italy (there are currently over a hundred operating).

Examples of frequency synthesizer systems with this wide range of selection modes are described in West German Patent Application No.

26 45 833 and 26 52 185 and, in particular, Italian Patent Application No. 69.950-A/77 filed on December 30, 1 977 by the present applicant.

All these modes, which are particularly useful in areas where a number of broadcasting stations can be received, require highly complex control equipment which many users may find difficulty in operating. This is even more so if, besides emitter selection and standard receiver adjustment controls (volume, brightness, colour, etc.), provision is also made for additional accessory functions such as a digital clock which requires additional setting controls. What is more, it must be possible to preserve memorised channel data in the case of power cuts. This can be done in the known way using a permanent outside memory (battery-supplied lowconsumption CMOS memory or non-volatile MNOS memory). Nevertheless, it has been shown that part of the data in the memory may be lost during the transient state between loss and return of power supply.

A further aim of the present invention is to provide a circuit arrangement designed to prevent loss of part of the data in the memory during the transient state between loss and return of power supply.

According to the present invention, there is provided a circuit arrangement for tuning into a television signal from among a number of radioelectric signals receivable on a television set which is supplied by a television power supply subject to interruption, the said arrangement including a read and write memory comprising a number of cells for memorising data relative to the said television signals which is to be preserved in the event of the television power supply being cut off, and conditioning means for preventing corruption of the contents of the memory during transient states caused by loss and/or return of the television power supply.

The invention will now be described, by way of example only, with reference to the accompanying drawings, in which:~ Figure 1 shows the block diagram of part of a television receiver according to the present invention; Figures 2, 3 and 4 show block diagrams of elementary logic functions performed by the circuits on the device according to the present invention; Figures 5 and 6 show a number of Figure 1 circuits in greater detail; Figure 7 shows the block diagram of a perfected version of the Figure 1 circuit - only the differing features are shown. Number 1 in Figure 1 indicates a receiving aerial connected to varicap-diode tuner 2 at the output of which a signal converted to intermediate frequency IF is available. The tuner is the known type and consists essentially of a selective amplifier state, a mixer circuit and local oscillator circuit.

One output on the local oscillator circuit is connected to a first frequency-divider circuit 3 which divides by a fixed number N 1 and whose output is connected to the signal input of a second divider 4 which divides by a variable number N with 12-bit programming, which means it can divide by any number from 1 to 212.

The output of divider 4 is connected to a first input of phase-frequency comparator circuit 5 to whose second input a reference signal generated by quartz generator 6 is sent via a third frequency-divider circuit 7. The output of comparator circuit 5 is connected to the tuner circuit varicap diode voltage control input via amplifier and filtering circuit 8.

Number 10 indicates a control unit consisting of a keyboard which, besides the control keys not shown, such as the on/off switch and volume, brightness, contrast and colour adjustment controls, also contains 10 number keys marked 0 to 9 (or letter marked A, B, C, D, E, F, G, H, I, L) and 7 auxiliary keys marked +, -, T, C, OR, M, CT (or+,-, R1,R2,R3,R4,CT).

This control unit is connected to a first group of eight input-output terminals of processing unit 11 and to the address inputs of memory circuit 12.

The said processing unit also has a second set of eight input-output terminals connected to the data input-output terminals of memory circuit 12 and the inputs of character generator circuit 16.

This, in turn, is connected to display device 9 (including the kinescope on the set) while a third group of 16 terminals is connected to: - 12 programming inputs of 12-bit divider 4; - 2 band-switch input (U and BIll) of tuner 2; - 1 control input of character generator circuit 16; - a first input of combined circuit 14.

Memory circuit 12 has further control terminals connected to the output of combiner circuit 14 which receives a signal from circuit 11 at a second input and a signal from on-detector circuit 15 at a third. Circuit 15 receives a signal from the power mains the television set is connected to and also has its output connected to a RESET input of circuit 11.

Memory 12 and the low-current-absorption CMOS combiner circuit 14 are connected to a local battery supply source 13. The circuit operates as follows:~ Circuits 3, 4, 5, and 8, together with the varicap-diode-controlled local oscillator (VCO) in tuner 2, form a phase lock loop controlled by the reference signal generated by quartz generator 6 and divided by divider 7 according to the known technique.

The function of divider circuit 3 is to reduce the frequencies involved to more easily processable levels while programmable divider 4 enables locking to be affected for a number of local oscillator frequencies, that is, it acts as a frequency synthesizer circuit.

In fact, after selecting division number N for divider circuit 4, phase-frequency comparator 5 supplies circuit 2, via amplifier 8, with voltage for obtaining the following condition:~ f6 f2 1) = or N2 N1.N 2) f2=P.N in which f2 is the oscillation frequency of the local oscillator circuit in tuner 2, f6 is the oscillation frequency of reference oscillator circuit 6, N2, N1 and N are the division ratios of dividers 3, 6 and 4 respectively, while N1 P=f6 N2 indicates the system pitch, that is, the amount by which local oscillator frequency varies alongside variations in number N.

The receiver must be capable of tuning into broadcasting stations of a given transmission standard, e.g. C.C.I.R./B-G, which channeling as agreed at the 1961 European Radio Broadcasting Conference in Stockholm, that is, broadcasting stations with one-step spacing between adjacent 7 MHz channels on the I and III (VHF) bands and 8 MHz channels on the IV and V (UHF) bands with a 5 MHz video signal band width. These broadcasting stations fall within television channels 2 and 69 (video carrier frequencies 48.25 and 855.25 MHz respectively) with 38.9 MHz intermediate frequency IF. This means the local oscillator on the tuner must be capable of generating frequencies ranging from 87.15 to 894.15 MHz. A 0.25 MHz pitch was selected which, according to equation 2 gives the following values for the two abovementioned channels: 87.15 87 Nm,n= =348 0.25 0.25 894.15 894.25 NmaX= =3577 0.25 0.25 By varying number N between this maximum and minimum, any television channel on the VHF and UHF bands can be tuned into with a maximum error of 125 KHz.

Not all of this frequency range can be utilized so the tuner is provided with two band switch inputs U (UHF/VHF) and B (BllI/B/) to ensure only effective bands are covered. Divider 3 is a highspeed ECL type which divides by 64 (Sp 8750).

Divider 4 is a programmable TTL which can operate up to frequencies of about 15 MFz (3xSN74LS191). Circuits 5, 6 and 7 consist of an SP8760 integrated circuit with 250 KHz frequency quartz and N2=64 division ratio so that comparator circuit 5 operates at 3906.25 Hz frequency which corresponds to a quarter of line frequency. The function of amplifier and filter 8 is to adapt the output level of comparator 5 (max.

5V) to the requirements of tuner 2 (max. 30V) and provide the bets possible filtering and lock speed conditions.

Circuit 11 , which consists of a microprocessor unit, is designed to generate, among other things, N numbers and band-switch signals for tuning into specific television broadcasting stations on the basis of data relative to the signals being tuned into supplied by the user from control keyboard 10. The said circuit 11 is also capable of supplying or receiving signals from memory 12 and sending signals to character generating circuit 16.

Number N is calculated using the following equation:~ 3) N-(K.F+C).4+S The operations shown are performed by means of a series of elementary operations by an arithmetical-logic unit (ALU) on the basis of instructions contained in a (ROM) programme memory contained in the said processing circuit 11 and performed, in this case, using an F8 microprocessor. Constant correction C and factor F depend on the band selected; K is the channel number according to the said standard and the S variable can be changed for performing fine tuning corrections.

If channel number K is changed, we only get the frequencies corresponding to standard channels with a pitch equal to F (8 MFz for UHF and 7 for VHF), whereas one-unit variation of S causes frequency shifts of 0.25 MHz.

With appropriate control from the keyboard, various modes are possible for tuning into a given broadcasting station partly using known methods.

Whenever any one of the keys is pressed, processing unit 11 sends an ISO-coded 48character sequence to character generator 16 which is displayed on the television screen in a three 18character line arrangement.

This sequence always includes a time indication (hours, minutes, seconds). The remainder consists partly of fixed data from the ROM programme memory (e.g. "CHANNEL" and "KEY" shown in Figure 1) and partly of variable data depending on the controls activated by the user and the situation resulting from them which is memorised in a memory buffer inside unit 11 (e.g. the letter T indicating operation mode in the top right-hand corner of Figure 1; Figures 31-01, also in Figure 1 following the "CHANNEL" indication which shows the channel number and tuning correction).

The time indication is corrected automatically each second even if no key is pressed in the meantime.

When one of the "T", "C", "OR" or "M" keys is pressed, the corresponding operation mode is set and memorised in the memory buffer of processing unit 11. At the same time, one or more question marks are entered into the buffer at appropriate points to guide the user on to the next control operation. The content of the buffer is then transmitted, of course, to the character generator and displayed on the television screen.

A few examples will now be given to give a clearer idea of this point.

When key "T" is pressed, the display shows: 00:MM:SS T KEY? In this way, the user is informed that he has selected mode "T" (memory selection) and that the device expects a number key to be pressed (that is, an emitter memory key number). N.B.: OO:MM:SS in the above example stands for the time indication (hours, minutes, seconds).

When key "C" is pressed, the display shows:~ 00:MM:SS C CHANNEL?? In this way, the user is informed that he has selected mode "C" (direct selection) and that the device expects two number keys to be pressed (required channel number).

If the number formulated by these two keys corresponds to a channel in the standard, the said number will be displayed in place of the two question marks beside the "channel" indication. If the channel number does not correspond to one in the standard, the display shows:~ 00:MM:SS C CHANNEL?? 88 In this way, the user is informed that the control set (channel 88 not covered by the C.C.l.R.

standard) has not been performed and that the device is awaiting further instructions. When key "OR" is pressed, the display shows:~ ??:??:?? T CHANNEL 21+01 KEY 0 OR This tells the user that the television set is still set to mode "T", that it is tuned to channel 21 with a tuning correction equivalent to one frequency shift over 250 KHz, memorised on key 0, and that the device expects six number keys to be pressed one after the other corresponding to the hours, minutes and seconds the clock is to be reset to. As the said six keys are pressed, the corresponding number is displayed in place of the "OR" indication and pairs of numbers replace the "??"corresponding to the hours, minutes and seconds, provided the numbers are acceptable.

In fact, the device checks the set numbers and, if the hour number is over 23 or the number corresponding to the tens of the minutes or seconds over 5, the two numbers (hours, minutes or seconds) are rejected and the two question marks are left displayed to inform the user that the device is waiting for another pair of acceptable numbers to be set. After the operation has been performed, the clock starts counting from the time set by the user.

The device is so designed that, following a power cut, series of zeros is displayed for the hours, minutes and seconds and the clock remains in this condition to inform the user that the power supply has temporarily been cut off.

When the "M" key is pressed, the display shows :- 00:MM:SS T CHANNEL 21+01 KEY #7 M This tells the user that the television is still set to "T" mode, that it is tuned to channel 21 with +01 tuning and that the set is waiting for a number key to be pressed to memorise the channel tuned into. If key "0" is pressed, for example, the display shown in Figure 1 appears and the said channel is associated with key "0" for memory selection. If key "+" is pressed, the display shows:~ 00:MM:SS T CHANNEL 21+02 KEY O This tells the user that the television is still set to "T" mode and that excess tuning corrections are being made, that is, towards the audio carrier of the received video signal.Circuit 11 supplies the programmable divider circuit, with a suitable modified number N and this tuning condition is automatically associated in the memory with key "0". Operation is similar when key "-" is pressed except for the direction of the tuning adjustment (towards the video). Once nominal tuning is obtained, the "+" sign and the following number are cancelled while, for more defective tuning conditions, the "-" sign appears followed by the number of displacements made. The system is so designed to limit maximum variations to the -16 to + 1 5 range. Of course, the tuning correction can be made in the same way even with the set in the direct selection mode (mode "C").

In this case though, the operation does not involve automatic memorisation for the channel and obtained tuning condition to be memorised, the "M" key must be pressed, followed by a number key.

When the "CT" (keyboard switch) key is pressed, the display shows:~ OO:MM:SS *T* CHANNEL 21+01 KEY O This tells the user ("*" beside the mode indication) that the device is set to perform a further series of functions corresponding to the second indication on each key. Following this operation, the processing circuit 11 supplies character generator 16 with a switch signal to switch signal to switch the colour of the writing on the screen or the background colour so as to make it even more clear to the user that the controls available from that time on correspond to second key indications (this applies, of course, to colour television sets).

If one of the keys marked "A" to "L" is pressed, the display shows:~ 00:MM:SS *C* CHANNEL A This tells the user that the television is set to mode "C" but, in this case, channels can be selected directly according to the Italian standard by pressing a single key with indication of the received channel.

When one of keys R 1, R2, R3 or R4 is pressed, the display shows, for example:~ 00:MM:SS *1 * CHANNEL 21+01 KEY O RA This tells the user that the set is performing an automatic scanning operation, for example type 1, or is scanning operation, for example type 1, or is scanning all the channels in the memory.

Scanning progresses automatically every two seconds with indications in each case of the key number and associated channel. At the same time, processing circuit 11 generates the relative N numbers for receiving the channel. Scanning stops when any other key is pressed. If the "+" or key keyis pressed, the device remains set for manual advance or reversing (every time the "+" key is pressed, the key number is increased and decreased every time the "-" key is pressed). If the "CT" key is pressed, the device switches back to the first keyboard and awaits further instructions, in particular, tuning correction or memorisation controls. Similarly, if key R2 is pressed after selecting the second keyboard using the "CT" key, this starts a type 2 scanning operation of all the standard channels (one switch per second).This can be stopped in the same way as type 1 scanning.

If key R3 is pressed, this starts a continuous scanning operation of the frequency band in 1 MHz steps, that is, 4 fine tuning switches per second, to detect any emitters operating over non-standard frequencies. The same type of scanning operation, though at reduced speed (one switch every two seconds), is started pressing key R4.

The "KEY" indication is not displayed during type 2, 3 and 4 scanning operations.

Display or omission of the fixed "CHANNEL" and "KEY" indications depends on whether the indication or blank sectors of the ROM memory are utilized. Circuit 11 also comprises a timer which, 1 5 seconds after the last key has been activated, supplies a switch signal (bit 6 port 1) to character generator 16 which reduces the display to one line and also halves the height of the characters (7 instead of 14 television lines) to reduce disturbance to the picture. This switch signal, or course, is not supplied during automatic scanning or clock adjustment.

To prevent memorised data being lost during a power cut, provision is made for a batterysupplied outside RAM memory 12. Whenever a memorisation operation is performed, processing unit 11 updates the information in the RAM memory. When power supply returns to normal, the same unit 11 calls up the data memorised in the RAM memory.

"ON RESET" circuit 15 and combiner circuit 14 protect the data contained in RAM memory 12 during transient states between power supply failure and restoration.

Operation of processing unit 11 is shown more clearly in the elementary logic function block diagrams in Figures 2, 3 and 4.

Figure 2 shows operation mode and relative indication selection; Figure 3 shows updating of the data in outside RAM memory 12; Figure 4 shows data being called up from the outside RAM memory following restoration of the power supply.

Number 20 in Figure 2 indicates a timer which sets a switch circuit, 22, with its output usually towards block 23 and supplies an RTI signal to block 21 which reads the controls set on the keyboard. Block 21, via switch 22, supplies a signal to block 23 which ascertains the presence of a new order. The "NO" output supplies the RTI signal which reactivates reading block 21 while the "YES" output activates block 24 which ascertains whether the key pressed was a mode key. The "NO" output of block 24 activates block 25 which examines the operation mode selected and, in turn, activates block 26 which, depending on the mode chosen, combines and supplies the indication sequence to the character generator for display. Block 26 then activates block 27 which examines the number keys pressed and activates block 28 which ascertains whether the corresponding order is feasible.

The "NO" output of the said block 28 (control not feasible, e.g. the number does not correspond to a standard number channel) activates a following block 34 which inserts question marks at appropriate points in the buffer to inform the user that the control is not feasible and transmits them to character generator 16 (Figure 1). Block 34 then supplies an RTI signal to block 21 which reads# the keyboard once more awaiting further instructions.

The "YES" output of block 28 activates block 29 which sends the channel of key numbers to the buffer, usually the numbers of the order received, transmits the numbers to the character generator and, finally, activates block 30 which calculates number N according to equation (3) and sends this number to programmable divider 4 (Figure 1) to obtain the required tuning. Finally, block 30 supplies the RTI signal to block 21.

The "YES" output of block 24 activates block 36 which inserts the indications and question marks in the buffer and transmits them to the character generator (as described already). Block 36 then supplies block 21 with the RTI signal.

After a set length of time (about 4 milli-seconds), depending on circuit 20, switch 22 positions itself with its output towards count circuit 31 which, after a set number of pulses (about 250) per second, supplies a signal to block 32 which updates the clock numbers in the buffer and activates block 22 which sends the data contained in the buffer to the character generator and then supplies an RTI signal to block 21.

Number 40 in Figure 3 indicates a block for ascertaining whether the operation selected involves memorisation. The "NO" output supplies a signal which activates block 25 (Figure 2) while the "YES" output activates in turn:~ ~block 41 , which examines the number of the key pressed; ~block 42, which memorises the channel number and tuning in the registers corresponding to the said key; ~block 43, which supplies an enabling signal (C.E.) and a first address for the outside memory circuit 12; ~block 44, which supplies the channel number data and a memorising pulse (WRITE) to the same circuit 12; ~block 45, which supplies the new address; block 46, which supplies the tuning data and memorising pulse to memory 12.

Number 50 in Figure 4 indicates a block which, following an "ON RESET" signal from circuit 15 in Figure 1, supplies an output enabling (O.E.) signal to memory 12 as well as a signal for activating in turn: ~block 51, which supplies the address to memory 12; ~block 52, which reads the data from memory 12 and loads it into the registers in unit 11 of Figure 1 ; ~block 53, which calculates the new address; ~block 54, which ascertains whether all the cells in memory 12 have been read.

The "NO" output of block 54 supplies a signal for activating 51 once more. The "YES" output activates block 55 which sets to mode "T" (memory selection) and key "0" and supplies an activation signal to block 25 of Figure 2.

For further information concerning operation of the device, refer to Italian Patent Application No.

69950-A/77, already mentioned, which described a device partly similar to the present one. On the actual device, a Fairchild F8 microprocessor unit was chosen for processing unit 11 which consists of a 3850 C.P.U., 3861 P.l.O., 3853 S.M.I. and two PROM F93448 memories. Each of the said two PROM memories consists essentially of a connection matrix with a 512 x8 format, input and address decoding circuits and output buffer circuits.

Each connection may be open or closed and represents permanent elementary data (bit) 1 or 0 respectively. Each group of 8 connections, addressed by one of the 512 address input combinations, represents an elementary 8-bit instruction or word (byte). By applying all the possible address combinations at the input, all the# data contained in the ROM can be obtained at the output in word form.

These connections are described in the following tables for the circuit. The left-hand columns show the addresses, using hexadecimal notation, and the right-hand ones the connections of the corresponding memory cell. Number 1 refers to an open connection with logic 1 at the output while 0 refers to a closed connection.

As each memory cell consists of 8 connections, this means it can be represented with a combination of 8 binary figures. For the sake of simplicity, the hexadecimal system was used on the following tables, so that, for example, EA for base 16, which corresponds to 11101100 of base 2, indicates that the corresponding memory cell has connections 1,2,3,5 and 6 open and the rest closed.

The above tables contain, in coded form, one possible sequence of elementary operations for performing, via the microprocessor system indicated, the functions shown in the block diagrams and foregoing description.

Fig. 5 shows a more detailed representation of the block diagram of character generator 16 in Fig. 1.

Number 60 in Fig. 5 indicates a character count circuit for supplying the addresses to character memory 61. This has a 48 x 6 format for containing the 48 characters transmitted periodically by processing unit 11.

The six INPUT/OUTPUT terminals of the said memory are connected to six output terminals of PORT 71 of processing unit 11. These are also connected to six inputs of character ROM 62.

This may be a Fairchild 3258 type, for memorising 64 characters for each of which it supplies an image consisting of a 5x7 point matrix. Each character is separated vertically from the next by two lines of blanks.

A built-in counter, which receives a clock signal with horizontal scanning frequency FH from the television circuits and a reset signal R1 from circuit 60, scans the following point lines of the said matrix.

The five outputs of the said ROM 62 are connected to a parallel-series converter circuit 63 which transforms the 5 signals received from the said 5 outputs into a series signal. It also adds a suitable number of blanks (e.g. 3) on to the end of the said 5 signals to separate the characters horizontally.

Circuit 63 receives a clock signal from oscillator circuit 66 the frequency of which determines the width of each of the characters displayed on the screen. It also receives a LOAD signal "L" for each character (every 5+3=8 clock cycles in the example shown) from divider circuit 67 which, in turn, receives the clock signal from oscillator circuit 66. The signal thus received at the output of converter 63 is sent to combiner circuit 64 consisting of known logic elements (e.g.

three 2-input AND gates each with a first input connected to the output of circuit 63 and a second connected to one of the outputs of circuit 65) which sends the said signal to one or more of its three outputs, marked R, G and B in the Figure, in response to the same number of control signals supplied by control circuit 65. The said outputs R, G and B are connected, in the known way, to the amplifier circuits of the colour signals on the set so that the signals supplied by circuit 64 are added to the video ones of the received television signal.

Depending on the instructions received from circuit 65, it is possible to obtain the indications in any one of the three primary colour combinations.

In Figure 5, the control circuit 65 receives a control signal from an output of circuit 71~port 4 of unit 11~(Figure 1) so that the indications are displayed in green when the system is set to the first keyboard and yellow when it is set to the second.

Numbers 68, 69 and 70 indicate three switch circuits, similar to one another, controlled in parallel by a control signal DT supplied by a bit of port 1 of processing unit 11 in Figure 1.

Depending on the DT signal, these three switch circuits enable the Figure 5 circuits to be set so as to load the data in memory 61 when the DT signal is present (high) and, vice versa, to set the same circuits for transmitting the data from the said memory to outputs R, G and B when the DT signal is absent (low) or when unit 11 is not transmitting characters to memory 61 (for display updating).

To do this, when the DT signal is present, switches 68, 69 and 70 are positioned as shown by letter A in Figure 5. This causes a reset pulse to be applied to terminals R2 and R3 of count circuit 60 and memory 61 is set to INPUT by the same DT signal applied to the input-output I/O control terminal.

Via switch circuit 68, count circuit 60 receives clock pulses DC from an output terminal of processing unit 11 of Figure 1 (port 4). The same DC signal is also sent to the write control input "W"ofmemory6l.

In this way, for each clock pulse it receives, counter 60 supplies RAM memory 61 with addresses from 0 to 47. At the same time, unit 11 supplies the 48 signals (at port 4) received at the data input of the same memory so that they are memorised in the corresponding cells as a result of the "W" pulses.

When the DT signal is absent, on the other hand, (switches in position B), character counter 60 receives clock signals from circuit 66 via divider 67, reset signals with vertical scanning frequency FV at terminal R2, reset signals with horizontal scanning frequency FH at terminal R3 and a format-change signal "F" from processing unit 11. In this way, it supplies memory 61 with suitable addresses for arranging the 48 display characters in three 16-character lines, should signal "F" be present, or else it supplies the said memory with only the first sixteen addresses for displaying a single 16-character line when signal "F" is absent. Counter 60 also supplies combiner circuit 64 with a disabling circuit for disactivating it during the remaining television picture time. In this way, only a certain part of the screen is displayed, e.g. the top left-hand corner.

If needed, the same disabling signal can be used for supplying a blank signal at an appropriate point in the television video amplification chain so as to blacken the background of the display to make the characters more visible.

A further output of circuit 71 (port 4 of unit 11) controls a switch 72, between a BIP signal (which can be picked up at an appropriate point on the circuit, e.g. at the output of divider 7 of Figure 1) and a first input of an adding circuit 73, whose second input receives the audio B.F. signal of the received television signal picked up downstream from the manual volume adjuster. The output of the said adding circuit is connected to the input of the B.F. amplifier 74, on the set which pilots the loudspeaker 75. In this way, under given circumstances, the processing unit 11 can control the sounding of an alarm for warning the user.

The said circumstances may be: ~when the "M" memory key is pressed the alarm reminds the user that the key has been pressed so as to prevent him from altering the content of the memory by mistake; ~when an unperformable instruction is given (e.g. the number of a non-existent channel or time) etc.; ~when the maximum allowable limits have been reached for certain adjustments such as fine tuning corrections.

Figure 6 gives a more detailed view of parts of circuits 12, 13, 14 and 15 in Figure 1 showing memorisation of the channels in the outside memory and maintenance of data during temporary power cuts. The said circuits 12, 1 3, 14 and 15 roughly correspond to the blocks marked 113, 100, 105 and 80 in Figure 6.

Block 80 comprises a Zener diode 83, connected between a + 12 output of a supply circuit "AC" voltage input, transformer 81 and rectifier 82) and a grounded resistor 84. The signal present at the resistor terminals is sent to an integrator circuit consisting of resistor 86, diode 87 and condenser 85.

The signal made available here, and inverted by inverter 88, is sent to inverter circuit 95 via integrator assembly consisting of resistor 93 and condenser 94, and also to the base of commonemitter transistor 90 via coupling resistor 89. The collector of transistor 90 is connected to a +5 supply voltage through resistor 92 and grounded through push-button switch 91 and supplies a reset signal to processing unit 11 (Figure 1).

The + 12 voltage is also supplied to the input of a stabilizer circuit 96 at the output of which, filtered by condenser 97, is made available the +5 supply voltage for supplying other circuits not shown in the Figure. The output of inverter 95 is connected to a first input of NAND gates 107 and 109 and to both inputs of NAND gate 106 which acts as an inverter. The output of the said gate 106 is connected to a reset input R4 of separator circuit 112 which receives the output signal of gate 107 at its disabling input C.D. via inverter circuit 110. Gate 107 receives a conditioning signal C.S.

from processing unit of Figure 1 at its second input. The output of gate 107 is also connected to a disactivating input C.D. of memory 11 3.

A READ signal from processing unit 11 of Figure 1 is sent via NAND gate 108, which acts as an inverter, to the read disabling "NR" input of memory 113. This input is also connected to a second input of gate 109 the output of which is connected to a write disabling "NW" input of the same memory 113.

The +5 voltage is also supplied to the anode of diode 101 at the cathode of which is connected a condenser, 104, the second terminal of which is grounded. Resistor 102 and 3 Volt battery 103, connected in series, are also connected parallel to condenser 104. The voltage available at the terminals of condenser 104 supplies memory 113, separator 112 and the 4 gates 106, 107, 108 and 109 contained in a single semiconductor body (CHIP).

Separator 112 has 5 inputs connected to 5 outputs of control circuit 111 (keyboard or remote-control receiver) and 5 outputs connected to 5 terminals of circuit 114 (port 5 of processing unit 11 in Figure 1).

The same 5 outputs are also connected to 5 address inputs of memory 11 3.

The circuit described above operates as follows: The function of block 00 is to generate a permanent supply voltage to keep memory 113 activated. In the event of a power cut, battery 103 supplies sufficient current to maintain the data in the memory through resistor 102. Vice versa, when power is being supplied from the mains, the +5 voltage is supplied to the memory via diode 101 and, at the same time, the battery is recharged slightly through resistor 102.

By means of Zener diode 83 and the integrator circuit comprising elements 85, 86 and 87, block 80 supplies a signal, at the output of inverter 95, after the +5 voltage, when the power supply is restored, and in advance of the said voltage when the power supply is cut off. In this way, the signals supplied by processing unit 11 to memory 11 3 cannot reach the memory during a power cut or during transient states.

Under the above conditions, gates 107, 108, and 109 are conditioned so as to protect memory 113 whereas gates 106 and 110 force separator 11 2 to supply a series of zeros at the output to prevent the memory from receiving chaotic address signals.

Block 80 also supplies, at the output of transistor 90, a signal similar to the one supplied by inverter 95 to keep processing unit 11 inactive during transient states and thus prevent uncontrolled operation. Push-button 91, however, enables a reset signal to be supplied manually to the said unit to commence the operation sequence from a preset point.

Figure 7 shows a possible variation of one part of the circuit shown in Figure 1. Figure 7 only illustrates the parts which differ from Figure 1 or which are connected differently.

Number 120 in Figure 7 indicates a control keyboard which, besides the keys shown in Figure 1 and not repeated here, comprises 6 keys marked "V+", "V-", "L+", "L-", "C+" and "C-".

The outputs of the said keyboard are connected to a group of input-output terminals 5 of processing unit 121 which is essentially the same as unit 11 in Figure 1 from which it differs, among other things, by the provision of a further group of output terminals (ports) 6.

Six terminals of the said group are connected to six inputs of a digital/analogue converter 123 of the known type (e.g. consisting of a known network of R/2R resistors). The analogue output of the said converter is supplied to a switch circuit 124 with three outputs marked V, L and C in the Figure which are connected to three storage condenser 125, 126 and 127 respectively.

Switch 124 also has two control input terminals connected to the remaining two output terminals of port 6 of unit 121 which receive the respective control signals for forwarding the analogue signal to one or other of condensers 125, 126 or 127.

The group of terminals or port 4 is connected to 8 input/output terminals of a RAM memory circuit 122. This replaces memory 12 of Figure 1 from which it differs by the number of 8-bit cells (10x5 instead of 10x2). This memory also receives six address bits (instead of 5) from six output terminals (port 5) of unit 121.

The Figure 7 circuit operates as follows:~ When one of the six keys mentioned above is pressed (e.g. key "V+"), unit 121 supplies the character generating circuit with a combination of symbols which may be: VVVVVVVV...

LLLLLL . . .

CCCCCCCCCCC...

The line of symbols corresponding to the pressed key (V, L, C) is displayed with a different colour from the rest. The number of characters per line is proportional to the corresponding analogue signal level (V, L, C) at that time.

Whenever one of the + keys is pressed, the corresponding analogue level is increased 1/64 of maximum value. When an operation involving memorisation is performed (e.g. whenever "KEY" operation mode is adjusted or the "M" key pressed, processing unit 121 transmits the relative data in digital form to memory 122 and has it memorised with much the same procedure already described and shown in Figure 3. This means the data memory 122 is called upon to memorise for each of the 10 "KEYS" is of 5 types: channel, tuning, volume, brightness and colour.

For the sake of uniformity; the memory accepts 8bit data whereas, for analogue adjustments, 6 bits (64 levels) are more than enough so two bits are ignored.

Other ways exist of displaying analogue levels on the television screen using the character generator and circuit arrangement described in the present invention. Besides the one described above, the display could show any one of the following:- v******* L***** C********** or: VOLUME 40? BRIGHTNESS 30 COLOUR 50 or: V+++++ L C In the first, the number of asterisks is proportional to the relative analogue signal level and the adjustment being made indicated by the symbol " > ". In the second, the level is indicated by the number to the side of the adjustment item while the adjustment being made is indicated by the question mark. In the third, the number of "+" (or "-") signs is proportional to the increase (or decrease) made to the preset nominal level.Of course, the preselected, memorised levels are preserved in memory 122, even in the event of a power cut, thanks to the precautions already described which also apply to the Figure 7 case.

It may prove useful to apply the sound alarm described in Figure 5 for analogue adjustments too, for example, when the maximum level is reached.

The advantages of the present invention will be clear from the foregoing description. However, a number of variations can be made. For example, in the description, it was supposed a particular type of 8-bit microprocessor system was used with a separate cpu and ROM. It is possible, and even convenient, to use other types of microprocessors with a higher number of internal RAM registers (e.g. 128) or a so-called monochip containing an internal RAM and timer citcuit, besides the ROM, or a 16-bit microprocessor.

It may even prove useful to fit the receiver with a remote-control. In this case, a keyboard similar to the one described is combined on the portable transmitter part of the remote-control system. A further variation, to avoid duplicating the control keyboard, could be to provide accommodation in the receiver housing with electric contacts in which to connect the transmitter part for operating the local control.

Many other variations can be made without, however, departing from the scope of the present invention.

For example, besides the key arrangement in Figure 1 for controlling channel selection or Figure 7 for controlling analogue levels (V, L, C), a number of different combinations can be used even using other control components different from keys or push-buttons.

Claims

1. A circuit arrangement for tuning into a television signal from among a number of radioelectric signals receivable on a television set which is supplied by a television power supply subject to interruption, the said arrangement including a read and write memory comprising a number of cells for memorising data relative to the said television signals which is to be preserved in the event of the television power supply being cut off, and conditioning means for preventing corruption of the contents of the memory during transient states caused by loss and/or return of the television power supply.

2. A circuit arrangement as claimed in claim 1, comprising a processing unit for supplying a number N to frequency dividing means, wherein the conditioning means include first means for generating a first signal which is delayed with respect to the supply voltage of the processing unit during the transient state when the television power supply is restored and wherein the generation of the first signal ceases before the said voltage is interrupted during the transient state when the television power supply is cut off; the first means being connected between the television power supply and means for preventing the control signals from the processing unit from reaching the memory in the absence of the first signal.

3. A circuit arrangement as claimed in claim 1, comprising a processing unit for supplying a number N to frequency dividing means, wherein the conditioning means includes first means for generating a first signal which is delayed with respect to the supply voltage of the processing unit during the transient state when the television power supply is restored and wherein the generation of the first signal ceases before the said voltage is interrupted during the transient state when the television power supply is cut off; the first means being connected betwe#en the television power supply and means for maintaining constant the address signals of the memory in the absence of the first signal.

4. A circuit arrangement as claimed in claim 1, further comprising supply means for supplying power to the memory in the event of a power cut in the television power supply, wherein the supply means includes a battery, for supplying the memory through a resistor, and a diode for connecting the television power supply to the memory and resistor.

5. A television set including a circuit arrangement as claimed in any one of the preceding claims.

New Claims or Amendments to Claims filed on 5/10/82 Superseded Claims 1 and 2 New or Amended Claims:~

1. A circuit arrangement for tuning into a television signal from among a number of radioelectric signals receivable on a television set which is supplied by a television power supply subject to interruption, the said arrangement including a read and write memory comprising a number of cells for memorising data relative to the said television signals which is to be preserved in the event of the television power supply being cut off, and conditioning means for preventing modification of the contents of the memory by incoming signals during transient states caused by loss and/or return of the television power supply.