GB2095944A

GB2095944A - Switching circuit

Info

Publication number: GB2095944A
Application number: GB8208563A
Authority: GB
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1981-04-01
Filing date: 1982-03-24
Publication date: 1982-10-06
Also published as: FI821057A0; FI821057L; PT74627A; DE3212221A1; JPS57176839A; PT74627B; SE8201902L; ES510791A0; IT8220523A0; BE892605A; ZA822224B; ES8304386A1; AU8192082A; FR2503486A1

Abstract

A switching circuit includes a speed-up diode or transistor (Q3A; Q13A) connected in diode-like fashion between a collector load resistor (12; 24) of a switching transistor means (Q5/Q9: Q15/Q20) and a supply voltage terminal (41) for increasing the switching speed. The diode provides a turn-on delay, permitting the switching transistor to more rapidly discharge a parasitic collector capacitor (CA). The diode also provides a turn-off delay to more rapidly charge the parasitic capacitor (CA) when the switching transistor means switches to a nonconductive state. Another load resistor (10) may be connected in series between the collector of the speed-up transistor (Q3A) and the supply voltage terminal (41) to develop the output voltage of the circuit. In this case, the diode-connected transistor (Q3A) serves to buffer the switching transistor means (Q5/Q9) from parasitic capacitances of the output circuits and thereby further increase the switching speed. The switching circuit can be incorporated with a flip-flop circuit to increase its switching speed, which is of importance when the flip-flop is used for instance as a frequency divider in a phase locked loop tuning circuit e.g., for a radio or television receiver. <IMAGE>

Description

SPECIFICATION Switching circuit This invention relates to switching circuits and more particularly to switching circuits which may comprise flip-flop circuits, involving emitter-coupled logic (ECL).

ECL circuits are typically used where high switching speeds are desirable. For example, in a superheterodyne tuner for radio or television receivers, the receiver signal frequency of a local oscillator is adjusted to equal the sum of the frequency or desired ratio frequency (RF) carrier and the frequency of the nominal intermediate frequency (IF) response, the latter which is fixed.

For example, in a single conversion television tuner employed in the United States, since the highest UHF (ultra high frequency) broadcast carrier has a freqency of approximately 885 MHZ and the nominal IF response is at 45.75 MHZ the highest local oscillator frequency is about 930 MHZ.

Double superheterodyne tuners initially convert the frequency of the desired RF carrier to a first IF signal having a much higher frequency, e.g., 415 MHZ, than the nominal IF frequency and then convert the first IF signal to a second IF signal at the nominal IF frequency of 45.75MHZ. A double conversion tuner is described in U.S. patent 4,162,462 issued July 1979 in the name of Ash.

Therefore, the frequency of the local oscillator signal needed to convert the highest UHF broadcast carrier to the first IF frequency is approximately at 1300 MHZ.

Frequency sythesizer tuning systems include a phase locked loop (PLL) for comparing the frequency of the local oscillator signal to a reference frequency to derive control voltage for a voltage controlled oscillator. A prescaler circuit is typically used to divide the local oscillator signal frequency down to a lower frequency compatible with other portions of the PLL. Such a tuning system is disclosed in U.S.

patent 4,031,549 issued on June 21, 1977 in the names of Rast et al., which patent is incorporated by reference.

The prescaler must operate at the highest expected frequency of the local oscillator signal. In the case of a double conversion tuner, this means the prescaler may have to operate at 1300 MHZ. For such reason, ECL toggle flip-flops are often used in prescaler circuits. Therefore, it is deisrable to provide an ECLflip-flop having a switching frequency, known also as the toggle frequency, of 1300 MHZ or more.

The flip-flop toggle frequency is determined by the ability of the switching transistors which comprise the flip-flop to drive capacitive loads. In conventional switching circuits which may be employed in a flip-flop, the load typically takes the form of a resistor which is passive.

In accordance with an aspect of the present invention, switching transistors, such as may be employed in a speed flip-flop, drive a load including a passive load resistor and an active load component including a diode arrangement. The latter enhances the ability of the transistor to drive capacitive loads and thereby increases its switching speed.

The present invention will be described with reference to the accompanying Drawing in which: Figure 1 is a schematic diagram of a master-slave flip-flop embodying the present invention; and Figure 2 is a block diagram of a television receiver including a phase locked loop tuning system which may use the flip-flop of Figure 1 in its prescaler circuit.

The master slave flip-flop in Figure 1 contains two individual so-called ECL (emitter coupled logic) flip-flops. In the first, transistors Q6 and Q7 are cross coupled. The collector electrode of transistor Q6 at node A is coupled to the base electrode of transistor 07 through emitter-follower transistor Q3. The collector electrode of tranisistor Q7 at node B is coupled to the base electrode of 06 through emitter-follower transistor Q4. Node A is further connected to a supply voltage (V1) terminal 41 through passive load resistor 12 and an active speed-up circuit constructed according to one aspect of the prsent invention, comprising transistor Q3A connected in diode-like fashion and second load resistor 10.

Similarly, node B is further connected to power supply terminal 41 through load resistor 16 and another active speed-u p circuit comprising transistor 04A and resistor 14.

The emitter electrodes of transistors 06 and 07 are coupled to current (Il) source 30 through the collector-emitter path of transistor 010. Transistor 06 and Q7 form the storage element of the first flip-flop. Current source 30 is connected to reference voltage (V2) terminal 42. The emitter electrodes of transistors Q5 and Q8 are coupled to current source 30 through the collector-emitter path of transistor Q9. The bases of OS and Q8 are coupled to reference terminal 42 through respective bias resistors 18 and 20. Transistors Q5 and 08 are gating transistors for entering data into the flip-flop storage element Q6, Complementary clock signals are coupled to the bases of transistors 09 and 010 through clock terminals 44 and 46. Transistors Q9 and 010 control the mode of the flip-flop.When transistor a9 is conducting, the flip-flop is placed in a gating mode in which new data is entered. When transistor Q10 is conducting, the flip-flop is placed in a data storage mode in which the previously entered data is stored.

The second flip-flop is similar to the first and includes transistors 016 and 017, cross-coupled through transistors 013 and Q14 as the storage element. The gating portion of the second flip-flop comprises transistors Q15 and Q18 and respective bias resistors 22 and 28. Transistors 019 and Q20 control the mode of the second flip-flop. When transistor 020 couples current (12) source 32 to the emitter electrode of transistors 015 and 018, the second flip-flop is placed in its gating mode. When transistor 019 couples current source 32 to the emitter electrodes of 016 and 017, the flip-flop is placed in its data storage mode.

In the second flip-flop, in accordance with another aspect of the present invention, the collector electrode of transistor 016 is coupled to power supply terminal 41 through an active speed-up circuit comprising diode-connected transistor Q13Ain series with passive load resistor 24. Similarly, the collector electrode of transistor 017 is coupled to power supply terminal 41 through an active speedup circuit comprising diode connected to transistor 014A in series with passive load resistor 26.

The master-slave flip-flop is operated in a toggle mode in which the output of the first flip-flop is connected to transfer its stored data to the input of the second flip-flop for a given polarity of input clock signal and the output of the second flip-flop is connected to transfer the complement of its stored data to the input of the first flip-flop for the opposite polarity of clock signal.For this purpose, the output voltages of the first flip-flop developed at the emitters of emitter-follower transistors Q3 and 04 are coupled to the respective bases of Q1 5 and Q18 and the output voltage of the second flip-flop developed at the emitters of emitter-follower transistors 013 and Q14 are coupled to the respective bases of Q8 and 05. For each successive clock pulse, the first and second flip-flops change states. Thus, the toggle flip-flop acts as a frequency divider. The switching frequency of the flip-flop is one-half that of the complementary clock signals applied at terminal als 44 and 46.

The output and complementary output signals of the master slave flip-flop are developed across resistors 10 and 14, respectively, at the collector electrodes of 03A and Q4A. Emitter-followertransistors 023 and 024 provide buffering of the respective output signals. Diode pairs D1 and D2 and D3 and D4 are connected between the emitters of 023 and Q24 and respective output terminals 48 and 50, and together with respective resistors 34 and 36, shift the level of the output signals appropriate for driving subsequent divider stages.

In operation, when terminal 46 is at a greater potential than terminal 44, transistor Q10 conducts, placing the first flip-flop in the data storage mode. At the same time, transistor 020 conducts, placing the second flip-flop in the gating mode. As a result, the data stored in the first flip-flop is transferred to the second flip-flop and the second flip-flop changes state. When the clock signal changes polarity, i.e., applying a more positive potential to terminal 44 than to terminal 46, the first flip-flop is placed in gating mode and the second flip-flop is placed in data storage mode. As a result, the complement of the data previously stored in the second flip-flop is transferred to he first flip-flop and the first flip-flop changes state.

To facilitate an understanding of the switching operation, assume that the first flip-flop is in its storage mode wherein transistor 09 is nonconductive, transistor 010 is conductive, transistors Q5 and 08 are non-conductive and transistor Q6 is conductive and transistor 07 is non-conductive. In this condition, transistor Q3A is conductive and transistor 04A is non-conductive. As a result, node B is near Vi. However, node A is at a potential somewhat less than V1 due to the voltage drop across resistor 12 and the base emitter voltage drop of transistor 03A.

When the polarity of the input clock signal switches, transistor Q9 is rendered conductive, thereby conditioning transistors Q5 and 08 to be rendered conductive. Due to the state of the second fip-flop only Q8 is conductive. As a result, the voltage at node A will tend to increase the voltage at node B will tend to decrease.

The active load arrangements including transistors 03A and Q4A enhance the switching speed of the first flip-flop. It is believed that the speed enhancement is due to the effective turn-on and turn-off dalay provided by transistors 03A and Q4A.

When transistor O3A is conducting current, node A is at lower potential than V1. As transistor 06 switches to a non-conductive state, transistor 03A momentarily stays on, ie., exhibits a turn-off delay.

This creates an over-shoot in the voltage at node A, charging the parasitic capacitance CA at node A more rapidly than otherwise, thereby producing a faster rise time. At the same time, parasitic capcitance CB at node B is being discharged from a high voltage to a lower voltage. Before the transition, transistor 04A is not conducting. When transistor Q8 turns on, transistor Q4A momentarily stays off, i.e., exhibits a turn-on delay. Thus, transistor Q4A momentarily presents a high impedance at the collector of transistor 08. Accordingly, transistor 08 need only sinkthe discharge current of CB and not the current from supply voltage V1. This allows Q8 to more rapidly discharge the capacitance of node B.

Therefore, it is believed that the active pull-up transistors 03A and Q4A provide a speed up effect because they inhibit the instantaneous change in current flowing through them. In this respect, at high frequencies, the active pull-up transistors Q3A and Q4A behave like inductances.

The active speed-up networks comprising transistors 03A and 04A have been found to operate to speed up the switching times in another manner.

Specifically, the output voltages are developed at the collector electrodes of speed up transistors 03A and Q4A. Accordingly, transistors 03A and Q4A provide isolation between the first flip-flop and the output emitter follower transistors 023 and Q24. Node A, rather than being directly connected to transistor Q24, and its associated parasitic capacitance is buffered by transistor 03A. Similarly, node B rather than being directly connected to transistor 023, is buffered by transistor 04A. The capacitive loading on nodes A and B is reduced so that the switching speed at such nodes is increased.

The operation of the second flip-flop 016, Q17 is analogous to that of the first flip-flop 06, Q7. The collctor electrodes of transistor Q1 3A and Owl 4A are shown directly connected to terminal 41 inasmuch as no output signals from the second flip-flop are desired.

A transistor structure suitable for use wth the present invention may be fabricated using conventional planar transistor construction. A typical vertical transistor includes a buried collector semiconductor region of N+ type conductivity. A base region of P type conductivity and an emitter region of N type conductivity are disposed above the buried collector.

The contact to the buried collector may be made by a deep N+ diffusion from the planar surface down to the buried layer. The collector resistance shown in Figure 1 as resistors 10 and 14 may be the resistivity of the buried collector. An output connection, if desired, may be made to the buried collector through a separate deep N+ diffucsion from the planar surface contacting the buried collector region.

A use of the present invention in a phase locked loop PLL tuning control system of a television receiver is shown in Figure 2. Tuner 62 receives a plurality of RF carriers from antenna 60 and converts a selected one in accordance with the selected channel to an IF signal. Components of the IF are coupled to signal processing circuit 64 which generates appropriate video signals for kinescope 66 and audio signals for loudspeaker 68. Channel selection is accomplished by a PLLtuning control system 78 which controls a voltage controlled local oscillator 70. A prescaler circuit 72, which divides the frequency of the signal from the local oscillator 70, is shown comprising a first counter stage 74 and subsequent counter stages 76. The first stage 74 of the prescaler 72 switches at the highest frequency, i.e., the frequency of the local oscillator 70. Therefore, the first stage 74 is preferably a master slave flip-flop in accordance with Figure 1, while subsequent counter stages 76 may be of conventional flip-flop design.

While the present invention is particularly useful in flipflops where particularly high frequency ECL master-slave transitions are generated, it may be employed in other switching circuits. These and other modifications are contemplated to be within the scope of the present invention as defined by the following claims.

Claims

1. Aswitching circuit comprising; first and second terminals for receiving an operating potential therebetween; a third terminal for receiving an input signal; transistor switch means responsive to said input signal at said third terminal for selectively providing current between said second terminal and a circuit node; a transistor having emitter, base, and collector electrodes, the base electrode thereof being connected to said terminal; a first resistor connected between the emitter electrode of said transistor and said circuit node; a fourth terminal for providing output signal to which the collector electrode of said transistor is connected; and a second resistor connected between said first terminal and the collector electrode of said transisto r.

2. A switching circuit in accordance with Claim 1 wherein said transistor switch means comprises; second and third transistors having respective emitter, base and collector electrodes, the respective current conduction path between collector and emitter electrodes of said second and third transistors being arranged in series between said circuit node and said second terminal, and the base electrode of one of said second and third transistors being connected to a source of reference potential, and the base electrode of the other of said second and third transistors being connected to said third terminal for receiving said input signal.

3. A switching circuit according to claim 2, further comprising a fourth transistor having emitter, base and collector electrodes, the emitter electrode of said fourth transistor being coupled to the emitter electrode of said third transistor; and a fifth terminal connected to the base electrode of the fourth transistor, said third and fifth terminals being arranged for receiving a differential signal therebetween.

4. A switching circuit comprising: first and second terminals for receiving an operating potential therebetween; first and second transistors having respective emitter, base and collector electrodes, the collector emitter conduction paths of said first and second transistors being arranged in series between said second terminal and a circuit node; a third terminal for receiving an input signal, said third terminal being connected to base electrode of one of said first and second transistors, the base electrode of the other of said first and second transistors being connected to a source of reference potential; a resistor having first and second ends, said first end thereof being connected to said circuit node; and a third transistor having emitter, base and collector electrodes, the base electrode thereof being connected to said first terminal, the emitter electrode thereof being connected to said second end of said first resistor, and means for connecting the collector electrode thereof to said first terminal.

5. A switching circuit in accordance with Claim 4 wherein said means for connecting said collector electrode of said third transistor to said first terminal comprises a direct connection without substantial intervening impedance.

6. A switching circuit in accordance with Claim 4 wherein said means for connecting said collector electrode of said third transistor to said first terminal comprises a resistor.

7. A switching circuit in accordance with Claim 4 furthur comprising: a fourth transistor having emitter, base and collector electrodes, the emitter electrode of said fourth transistor being coupled to the emitter electrode of said second transistor; and a fourth terminal to which the base electrode of said fourth transistor is connected, said third and fourth terminals being arranged for receiving a differential input signal therebetween.

8. In a bistable flip-flop circuit having first and second terminals for receiving an operating potential therebetween, a current source connected to said second terminal, and first and second transistors having collector emitter conduction paths connected in series for selectively conducting between said current source and a circuit node, the potential at said circuit node being provided at predetermined levels for selectively switching the state of said bistable flip-flop, an improved load means for connecting said circuit node to said first terminal comprising: a resistor; and diode means connected in series with said resistor for connecting said first terminal to said circuit node.

9. A bistable flip-flop circuit in accordance with Claim 8 wherein said diode means comprises: a third transistor having emitter, base and collector electrodes, the base electrode thereof being connected to said first terminal, the emitter electrode thereof being connected to said resistor; and means for connecting the collector electrode of said third transistor to said first terminal.

10. A bistable flip-flop in accordance with Claim 9 wherein said means for connecting the collector electrode of said third transistor to said first terminal comprises a direct connecting without substantial intervening impedance.

11. A bistable flip-flop in accordance with Claim 9 wherein said means for connecting the collector electrode of said third transistor to said first terminal comprises a second resistor.

12. A bistable flip-flop circuit in accordance with Claim 11 further including a second terminal for providing output signal to which the collector electrode of said third transistor is connected.

13. A switching circuit comprising transistor switching means with an active load substantially as herein before described with reference to compo nents Q3A, 10 and 12 or Q13A and 24 in Figure 1 of the accompanying drawings.

14. A bistable flip-flop circuit substantially as hereinbefore described with reference to either the first or the second flip-flop in Figure 1 of the accompanying drawings.

15. A phase locked loop circuit incorporating as a frequency divider a bistable flip-flop as claimed in any of claims 8 - 12 and 14.