GB2083667A - Improvements in or relating to control units for input-output modules in electronic processors - Google Patents

Abstract

In a microprogrammed circuit arrangement designed to operate a functional unit, termed module below, and comprising a plurality of input- output interface circuits and auxiliary circuits, a recorded-programme control unit is arranged to receive control and timing signals from a central logic unit (CPU) and sends suitable microcontrols to the remaining units in the module. The control unit comprises: a circuit CSL for rapidly synchronizing the beginning of the microinstructions carried out by the control unit together with those carried out by the CPU; a circuit FL arranged to stop a microinstruction being effected by the control unit while waiting for the arrival or the discontinuance of a signal sent by the CPU; and a circuit MPC arranged to control whether the microcontrol sequence in a microinstruction is correct and whether the microinstruction itself is completed. Logic gates supply either an operative microinstruction or a cyclic scanning microinstruction to be effected via signals WP, IP respectively. Cyclic scanning microinstructions for interface circuits to trace requests to be sent to CPU are output when the control unit is not carrying out one of the microprograms stored in the control store Cs. <IMAGE>

Description

SPECIFICATION Improvements in or relating to control units for input-output modules in electronic processors The present invention relates to a microprogrammed circuit arrangement designed to operate a functional unit in an electronic processor, termed module below, and comprising a plurality of inputoutput interface and auxiliary circuits.

Data transfer operations between the central memory or the central logic unit (CPU) in an electronic processor and the peripheral units, by way of respective interface circuits to which each peripheral unit is connected, make it necessary to perform a series of microinstructions. To avoid uselessly operating the CPU, these operations are conveniently carried out by decentralized units which directly interact with the interface circuits.

Such decentralized units, termed control units below, preferably have a simple structure, which limits the number of interfaces each control unit can operate.

Thus, the input-output part of the processor has a modular structure where each module comprises a plurality of interface circuits and control units arranged to operate them, whereas the messages sent by the CPU include the module address, the module interface address and the instructions for the control unit to perform an operation by activating a suitable microprogramme.

According to the invention there is provided a control unit for an input-output module in an electonic processor from whose central logic unit are received control and timing signals, comprising: a coding unit arranged to generate, in response to a request for carrying out a microinstruction, a code which is written in a first register; a counter arranged to scan the microcontrols forming one microinstruction; a first memory arranged to be addressed by the code written in the first register and by the counter and containing operative microinstructions; a second memory arranged to be addresses by the counter and including cyclic scanning microinstructions for interface units belonging to the modules; a first circuit arranged to synchronize the beginning of the microinstructions performed by the control unit with those of the control logic unit; a second circuit arranged to stop a microinstruction being carried out in the control unit while awaiting for the appearance or disappearance of at least one signal generated by the central logic unit; a third circuit arranged to control correct succession of microcontrols in one microinstruction and the completion of the microinstruction itself; and means arranged to enable an operative microinstruction and a cyclic scanning microinstruction to be carried out.

It is thus possible to provide a control unit comprising circuits arranged to rapidly synchronize it with the CPU both at the beginning of a microinstruction and while the same is being carried out, as well as circuits arranged to control whether the microcontrol sequence in a microinstruction is correct and whether the microinstruction itself is completed.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure lisa block diagram of a control unit constituting a preferred embodiment of the present invention; Figure 2 shows an embodiment of the synchronization circuits CSL and FL of Figure 1; and Figure 3 shows an embodiment of the circuit MPC of Figure 1.

Signals indicating a microinstruction to be carried out, coded by a coder CE and written in a register CC, constitute the most significant bits of addresses in a memory CS (Control Store) whose cells store the microcontrol forming each microinstruction. The least significant bits of each address are generated by a counter PC which also addresses an second memory PS which stores cyclic scannning microinstructions for the interface circuits to trace requests to be sent to the CPU. Cyclic scanning takes place when the control unit is not used to carry out one of the microprogrammes stored in the memory CS. The memories CS and PS and the memory forming the counter PC are followed by respective registers R timed by a signal CKP and reset by a signal RS.

These signals will be further described below.

Some of the signals arranged to activate a microinstruction correspond to instructions of the programme being carried out by the CPU, whereas other signals are due to input-output operation requests sent to the CPU by the peripheral units. With reference to the drawing, signals RW (transfer of a datum to the CPU), CW (transfer of a datum from the CPU), and IOG (control instructions for the interfaces) originate from the programme of the CPU, whereas signals DCY (first cycle of a double DMA), Dl (input DMA), DO (output DMA) and IBT (interrupt request) are originated from requests sent to the CPU.

DMA (Direct Memory Access) indicate a procedure which makes it possible to rapidly transfer data from the central memory to a peripheral unit and vice versa. Double DMA indicates a particular DMA in which a plurality of peripheral units can write in the same memory area and each word is preceded by the address of the peripheral unit which has generated it.

An embodiment of a circuit belonging to the module and arranged to effect the DMA, including the double DMA, is disclosed in Italian Patent Application No. 23659 A/80 filed on 24/7/1980.

To carry out the programmes correctly, it is necessary to synchronize the beginning of a microinstruction with the programme of the CPU and to stop, if necessary, the microinstruction until a control signal is received from the CPU.

Synchronization is obtained by means of a circuit CSL (cycle synchronization logic) which is arranged to reset the registers R by way of the signal RS. A microinstruction is stopped by a circuit FL (freezing logic) designed to eliminate, by means of a signal F, a signal CXP designed to time the registers R.

An embodiment of the circuits CSL and FL is shown in Figure 2.

A microprogramme controlling circuit MPC illus trated in Figure 3 is designed to make sure that the microcontrols generated by the memory CS correctly follow one another and the microinstruction is completed. Any possible error (ME) is signalled to the CPU.

As already mentioned above, a scanning microinstruction IP generated by the memory PS is performed by all the input-output processor modules which are not carrying out one of the operative microinstructions generated by the memory CS and generally indicated atWP in the drawings.

The counter PC causes both the memory PS and CS to step forward. More particularly, at the beginning of each cycle, the memory PS generates a microcontrol CK which writes any input signals in the registers CC and RK. The register CC receives coded signals from the coder CE, whereas the register RK enables the operative microinstructions WP when the module recognizes the address (ID) associated with a control IOG, RW or CW generated by the CPU when the CPU accepts a request (ASW) sent by the module, or, in the second cycle of a double DMA, in response to a signal DF generated by the DMA circuit in the module.

The outputs IP and WP are, of course, mutually exclusive as the module cannot simultaneously carry out an operative microinstruction and cycle scanning of the peripheral units.

Figure 2 shows an embodiment of the synchronization logic CSL and the freezing logic FL.

The circuit CSL is arranged to synchronize the input-output module with the CPU. Such a synchronization is particularly important when the peripheral units are operated bytwo synchronized processors. The times of execution of the same programme are not perfectly equal to one another for the two processors, and thus it is necessary to make sure thatthe beginning of an input-output operation takes place simultaneously in the two processors as soon as both CPUs are in a position to perform it.

The CPU always generates a timing signal MCK and while terminating the preceding instruction it generates a signal PR having a predetermined duration which is an integer multiple of the period of the clock MCK. At the end of the signal PR, the CPU is certain to be available for carrying out a new instruction.

A J-K type bistable 1 forming the circuit CSL generates a signal RS which has a duration equal to one period of the clock MCK and resets the registers R (Figure 1). The bistable 1 istimed bytheclock MCK. Thus, the edges of the signal RS coincide with two successive identical transitions (e.g. leading edges) of the clock MCK. The registers R are timed by a clock MCK and begin to store the microcontrol available at the output of the memories half a period of MCK after termination of the signal PR. The function of the signal PR is as follows. The leading edge indicates that the CPU needs a predetermined time for terminating a cycle and the input output module is getting ready for a successive cycle by resetting the registers E.The trailing edge indicates that the CPU has terminated its cycle and the input-output module is ready for a successive cycle.

Two processors operating in synchronization exchange information with one another and among these the state of the signal PR. In each processor the state of operation of the CPU performing the cycle being carried out determines the leading edge of the signal PR, whereas each CPU terminates its signal PR only when it receives confirmation that the other CPU has terminated its own cycle, so that the trailing edges of both signals PR coincide.

If the duration of the signal PR is an even multiple, greater than two, of the period of the clock MCK, a series of pulses RS is generated, i.e. the registers R are reset several times.

The circuit CSL and the structure of the memories PC, CS and PS make it possible to start input-output microprogrammes synchronously with the CPU and in a very limited time.

When the signal RS resets the registers R, the start address is simultaneously provided for the memory PS, whereas the memory CS receives the least significant data of the microinstruction to be performed.

At the end of the signal PR, the CPU sends the signal indicating a new microinstruction to the coder CE and the memory PS simultaneously generates a timing signal CK, whereas the memory CS reaches the complete starting instruction address by means of a conditioned leap in the successive period of the clock MCK. Thus, the control unit of the input-output module is in a position to start a new microinstruction with a predetermined and strictly observed delay of two periods of the clock MCK with respect to the moment at which the CPU has sent to it information about the new microinstruction to be performed once the preceding cycle has been terminated and the signal PR eliminated.

Figure 2 also shows an embodiment of the circuit FL. During the execution of some cycles it may be useful or necessary to synchronize the input-output operations while the programme is being performed in the CPU, by stopping the input-output microprogramme until a predetermined event has occurred, such as the appearance or disappearance of a signal sent by the CPU.

In the drawing it is assumed that a microinstruction may include only waiting for a signal enabling a datum (signal LIO) to be sent to the CPU, or the end of such a signal. These two circumstances are governed by microcontrols FUL and FEL inserted in the microinstruction perforated by the control unit in the input-output module.

The circuit FL comprises a plurality of gates 21,22 equal in number to the stop microcontrols, each gate receiving a microcontrol and the signal whose appearance or disappearance must be awaited. The outputs of the gates are connected, by way of an OR gate 11, to the data input of a second bistable 2 timed by the clock MCK.

The output F of the bistable 2 prevents the clock MCKfrom passing through the NOR gate 12. In this way, there is no signal CKP causing the registers R to advance and performing the microinstructions.

More particularly, the counter PC is blocked (the memory CS is addressed to the cell storing the stop microcontrol) and also blocked is the register R associated with the memory CS. The stop microcon trol is effective until the signal F ceases.

It may happen that the signal waited for cannot arrive (e.g. if the memory is engaged, the CPU does not ask for a datum to the interface module). To prevent the module controlling unit from being jammed in a stall state, a signal SD is provided which is sent from the CPU when the latter realizes that it cannot send the signal waited for.

As already mentioned with reference to Figure 1, the interface module controlling units effect cycle scanning of the interfaces by being controlled by the microprogramme stored in the memory PS and caused to advance by the memory PC which also controls the memory CS. To prevent a possible stop microcontrol from blocking the memory PC, and thus the cyclic scanning, the gates 21, 22 are enabled by the signal RK available only in the module addressed by the CPU.

Without departing from the scope of the present invention, it is possible to provide further interrupting microcontrols besides, or in place of, those (FUL,FEL) indicated in the drawings by correspondingly adjusting the number of gates connected to the inputs of the gate 11.

Figure 3 shows an embodiment of the micriinstruction controlling circuit MPC.

The circuit MPC comprises a parity control circuit PA4 whose input receive address bits from the counter PC and the register CC, and the parity bits PA of a successive address included in the microcontrol generated by the memory CS.

The registers associated with the memories PC and CS are stepped forward by the same clock CKP which, while storing a microinstruction in the register R associated with the memory CS, increases by one the address available at the output of the memory PC. The address given by PC is that of a successive microinstruction. By knowing the correct sequence of the microcontrols it is possible, while carrying out each microinstruction, to give the bit PA of each microcontrol a requested value.

For the last microcontrol EOP of each microinstruction it is impossible to know which will be the successive microinstruction, and thus to know to which address to refer for computing the bit PA.

To eliminate such an ambiguity many solutions may be adopted, among which are the following: inhibiting the circuit PA4 by means of the last microcontrol EOP, or preventing a possible error signal S4 from being sent to the CPU; by using constant length microinstructions, arranging the counter PC in such a way that, when it has exhausted its counting capacity, i.e. the microinstruction is terminated, it remains in the reached state; the bit PA of the last microcontrol EOP is computed in accordance with the address of the microcontrol itself.

If a cycle is regularly terminated, upon arrival of the signal PR (which, as mentioned above, indicates that the CPU is terminating its own cycle) the last microcontrol EOP must be active in the module. The absence of the microcontrol EOP, which is detected, for instance by a bistable 3, is signalled to the CPU, e.g. by the OR gate 14 which also receives the error signal S4 to form a signal ME to be sent to the CPU.

A signal C4 makes it possible to alter, by means of a software control, the parity bit PA so as to cause the error signal S4to be generated. This makes it possible for the CPU to check correct operation of the circuit PA4.

Claims (12)

1. A control unit for an input-output module is an electronic processor from whose central logic unit are received control and timing signals, comprising: a coding unit arranged to generate, in response to a request for carrying out a microinstruction, a code which is written in a first register; a counter arranged to scan the microcontrols forming one microinstruction; a first memory arranged to be addressed by the code written in the first register and by the counter and containing operative microinstructions; a second memory arranged to be addressed by the counter and including cyclic scanning microinstructions for interface units belonging to the modules; a first circuit arranged to synchronize the beginning of the microinstructions performed by the control units with those of the central logic unit; a second circuit arranged to stop a microinstruction being carried out in the control unit while awaiting for the appearance or disappearance of at least one signal generated by the central logic unit; a third circuit arranged to control correct succession of microcontrols in one microinstruction and the completion of the microinstruction itself; and means arranged to enable an operative microinstruction and a cyclic scanning microinstruction to be carried out.

2. A control unit as claimed in claim 1, in which the second memory is arranged to generate at the beginning of each cycle, a first signal for enabling the said means and to control writing of the code generated by the coder in the first register.

3. A control unit as claimed in claim 1 or 2, in which respective registers are provided at the outputs of the counter and of the first and the second memories, the registers being arranged to be reset by a second signal generated by the first circuit and to be advanced by a third timing signal obtained by means of a fourth signal generated by the second circuit and by a fifth timing signal generated by the central logic unit, the counter comprising a memory arranged to be addressed together with the first and second memories by the output of the register associated with the counter.

4. A control unit as claimed in claim 3, in which the firstr circuit comprises a first J-K type bistable arranged to be timed by the fifth signal and having control inputs arranged to receive a sixth signal generated by the central logic unit when a predetermined time interval is needed to reach the end of the preceding cycle, the sixth signal terminating at the end of the cycle, the output of the first bistable forming the second signal.

5. A control unit as claimed in claim 3 or 4, in which the second circuit comprises: a plurality of gates equal in number to the number of stop microcontrols available in the microinstructions stored in the first memory, each gate being arranged to receive at one input thereof, a microcontrol of awaiting the arrival or the termination of a signal and the signal at another input thereof; an OR gate connected to the outputs of the plurality of gates and having an output connected to the data input of a second bistable; and the second bistable arranged to be timed by the fifth signal and to provide an output which forms the fourth signal.

6. A control unit as claimed in claim 5, in which each of the plurality of gates associated with a microcontrol of awaiting the arrival of a signal is arranged to receive, on a further input thereof, a seventh signal from the control logic unit in place of the signal awaited when such a signal cannot be generated owing to an interruption in the processing cycle.

7. A control unit as claimed in any one of claims 3 to 6, in which a predetermined bit of each microcontrol forms a parity bitforthe address of the next following microcontrol, the third circuit comprising a parity control circuit whose inputs are arranged to receive the address bits available at the output of the first register and the register associated with the counter as well as the parity bit, there being provided a third bistable arranged to be timed by the sixth signal and to receive on its inverted data input the last microcontrol of the microinstruction, the outputs of the parity control circuit and the third bistable connected to inputs of an OR gate arranged to generate an alarm signal for the central logic units.

8. A control unit as claimed in claim 7, in which the counter is arranged, when its counting capacity has been exhausted, to remain in the state it has reached, so that the value of the parity bit of the last microcontrol coincides with that of the preceding microcontrol.

9. A control unit as claimed in any one of the preceding claims, in which the enabling means comprises a second register arranged to be timed by the first signal and to activate its output when the module identifies its own address associated with a message sent by the central logic unit or in response to a signal generated by a circuit belonging to the module and designed to operate a double DMA, the logic level of the output of the second register causing an operative microinstruction or the cyclic scanning signal to be sent to the interface circuit.

10. A control unit as claimed in claim 9 when dependent on claim Sin which all the gates of the second circuit are arranged to be enabled by the output signal of the second register.

11. A control unit substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

12. An electronic processor including an inputoutput module having a control unit as claimed in any one of the preceding claims.