GB2075669A - Monitoring sheet material width - Google Patents

Abstract

A device for monitoring the width of sheet material has a plurality of light emitting elements 1l-16l and 1r-16r and a plurality of light sensitive elements 1L-16L and 1R-16R. Each light sensitive element is paired with a light emitting element geometrically and electrically, each light sensitive element opposing a light emitting element in face-to-face relationship with the former electrically combined with the latter such that only the output from the opposing light sensitive element is sensed when a light emitting element is energized. An electric circuit operatively associated with the light emitting and receiving elements to combine them in the aforementioned manner includes a clock signal generator, a counter for counting the clock signals generated from said clock signal generator to give out output signals for energizing the light emitting elements serially one by one and an analog multiplexor for serially selecting the outputs from the light sensitive elements one by one. <IMAGE>

Description

SPECIFICATION Device for monitoring the width of sheet material The present invention relates in general to devices for monitoring the width of sheet material.

Such width inspection devices are generally used for example in bank note sorting or counting machines to monitor the width of each bank note under inspection.The data relating to the widths of the bank notes are used for discriminating forged or false bank notes from the genuine bank notes to be handled in the machine.

A device for monitoring the width of a bank note and having a plurality of light emitting elements and photosensitive elements is known in the art. Half of a typical example of a known device is shown in Fig. 1 arranged along one side of a bank note passage 20 to detect the left edge of a bank note 21 moving perpendicularly to the drawing sheet, as viewed in Fig. 1. Although not shown, a similar assembly is arranged along the other side, the right-hand side, of the bank note passage 20 to detect the right edge of the bank note 21. Eight equispaced light emitting diodes (hereinafter referred to as LED) 11 to 81 are arranged to cover the left side of the bank note passage 20, and sixteen equispaced photosensitive diodes (hereinafter referred to as PD) 1 L to 1 6L are arranged in an opposed relationship with the light emitting elements.

The bank note 21 is conveyed perpendicularly to the drawing sheet, for instance from the front to the back of the sheet, by conveyer, not shown. The LEDs 11 to 81 are continuously energized by a power source of a width detection circuit, not shown, to emit light. Some of the light is shielded by the bank note 21, and the remaining light which is not shielded by the bank note 21 is received by the PDs 1 L to 1 6L. Upon receipt of light, the PDs 1 L to 1 6L generate output signals which are put in the width detection circuit, where they are combined with the output signals from the assembly arranged at the right side of the bank note passage 20. The width of the bank note 21 is determined by the combined information derived from these signals.

However, the prior art device shown in Fig.

1 gives erroneous information if the bank note 21 is conveyed While being bent or curved upward. If the end of the bank note 21 is curved upward as shown in Fig. 1, the light emitted from the diode 61 positioned outwardly of the edge of the bank note is received by the diode 8L positioned inwardly of the edge of the bank note. As a result, the left edge of the bank note 21 is detected as if it were positioned inwardly of the diode PD 8L.

The datum relating to the width of the bank note based on such erroneous information leads to a wrong result in that the width of the bank note is monitored as being less than the real width. This a serious problem because the bank notes are frequently conveyed in such a curved condition rather than being maintained completely flat.

The invention provides a device for monitoring the width of sheet material comprising a plurality of light emitting elements, a plurality of light sensitive elements opposing corresponding light emitting elements, the light emitting elements and light sensitive elements being arranged for the passage of sheet material therebetween, and an electric circuit for monitoring the width of the sheet material by the light signals received by the light sensitive elements, the electric circuit including means for selectively energizing the light emitting elements one by one and scanning means for selectively scanning outputs generated by the opposing light sensitive elements in response to the light signals they receive.

An embodiment of the present invention will now be be described, by way of example, with reference to Figs. 2 to 7 of the accompanying drawings, in which: Figures 2 and 3 are respectively front and plan views of a device embodying the invention for monitoring the width of bank notes, wherein the arrangement of the light emitting and receiving elements is shown schematically to demonstrate the principle of the invention; Figures 4 and 5 show an electric circuit operatively associated with the device of Figs.

2 and 3; and Figures 6 and 7 are time charts showing the operation of the electric circuit shown in Figs. 4 and 5.

Firstly referring to Figs. 2 and 3, a bank note 21 is passed through a bank note passage 20. Pulley blocks 23 and 24 are mounted on a drive shaft 22 rotated by a suitable drive mechanism (not shown). These pulley blocks 23 and 24 are operatively associated with paired pulley blocks (not shown) to move pulley belts 25 and 26 stretched over them. Upper pulley belts 35 and 36 are stretched over pulley blocks 33 and 34 mounted on another shaft 32, and over combined pulley blocks (not shown), the belts 35 and 36 being positioned in opposed relationship with the pulley belts 23 and 24. Thebank note 21 is inserted between and held by the pulley belts 25, 26 and the upper pulley belts 35, 36 to be conveyed through the passage 20.A left side sensing assembly comprises a group of light emitting elements or diodes 11 to 1 61 arranged at the upper left side of the passage 20 to cover the left marginal portion of the travelling bank note 21, and a group of photosensitive diodes 1L to 16L, arranged at the lower left side so that each photosensitive diode is opposed to one of the light emitting diodes. A similar sensing assembly including light emitting diodes (her einafter referred to as LED) 1 r to 1 6 rand photosensitive diodes (hereinafter referred to as PD) 1 R to 1 6R is arranged at the right side of the passage 20. The LEDs 11 to 1 61 are equispaced with the LED 11 arranged at the innermost position while the LED 1 61 is arranged at the outermost position.PDs 1 L to 1 6L are also arranged at equal intervals so that the innermost PD 1 L faces the innermost LED 11 and the outermost PD 1 6L faces the outermost LED 1 61. The correlation between the LEDs lrto 16randthe PDs 1rto 16rof the sensing assembly positioned at the right side of the passage 20 is similar to that in the aforementioned left side assembly.

As the drive shaft 22 is rotated in the clock wise direction, as viewed from the right edge of the drawing sheet, the shaft 32 is driven in the reverse direction, whereupon the pulley blocks 23, 24, 33 and 34 are rotated to move the pulley belts 25, 26, 35 and 36 which, in turn, convey the bank note 21 in the direction shown by the arrow 30 in Fig. 3.

The left and right portions of the travelling bank note 21 are sensed, respectively, by the combination of LEDs 11 to 161 and PDs 1 L to 1 6L and by the combination of LEDs 1 rto 16rand PDs 1R to 16R, and the signals generated from the sensing assemblies are fed to an electric circuit which will be described in detail hereinbelow.

Now referring to Figs. 4 and 5 showing an electric circuit 1 8 operatively associated with the device shown in Figs. 2 and 3, the procedure of determining the width of a bank note will be described in detail. In Figs. 4 and 5, the parts or constituent elements corresponding to those shown in Figs. 2 and 3 are denoted by the same reference numerals. In the following description relating to the logical design, binary logic levels "1" and "O" will be used. Referring to Fig. 4, the electric circuit 1 8 includes a clock signal generating circuit 40 having output terminals t, to t4 from which four-phase clock signals S1 to S4, as shown by (b) to (e) of Fig. 6, are given out.

Reference numeral 41 designates a binary counter for counting the clock signals S2 to give out four-bit code signals S30t S31, S32 and S33 corresponding to (20), (21), (22) and (23).

These signals are fed to a circuit 1 9 through terminals 42 to 45. Referring next to Fig. 5 showing the detailed design of the circuit 19, the binary code signals S30 to S33 fed through the terminals 42 to 45 are converted to signals of hexadecimal notation by decoders 46 and 47. Each one of the sixteen outputs of each decoder 46 and 47 is brought to the level ''1'' by each of the hexadecimal code signals, and these outputs are passed to drivers 48 and 49. Each of the drivers 48 and 49 has sixteen driver circuits and puts out a corresponding output of "0" level in response to the input of "1" level. The output terminals of these drivers 48 and 49 are connected, respectively, to the cathodes of the LEDs 11 to 1 61 and the cathodes of the LEDs 1 rto 16r.The anodes of the LEDs 11 to 161 are commonly connected through a resistance 50 to a power source + V. Similarly, the anodes of the LEDs 1 rto 1 6r are commonly connected through a resistance 51 to the power source + V. As the clock generating circuit is actuated to initiate oscillation, the binary counter 41 counts the clock signals S2.

The resultant code signals S30 to S33 are decoded respectively by the decoders 46 and 47 and fed to the drivers 48 and 49 by which the cathodes of the LEDs 111 to 1 61 and the cathodes of the LEDs 1rto 1 6 r are brought to the level "0" one by one. When all of the binary code signals S30 to S33 are at the "0" level, the cathodes of the innermost LEDs 11 and 1 rare brought to "O". at that time, both the LEDs 11 and 1 rare energized to emit light concurrently. At the next timing, the LEDs 21 and 2rare energized to emit light concurrently, followed by energization of the LEDs 31 and 3r, and so on.Thus the LEDs Il to 161 are energized or scanned serially from the innermost LED 1 to the outermost LED 161, and at the same timing the LEDs 1 rto 1 6r are scanned serially. One cycle scanning is completed by concurrant energization of the LEDs 161 and 16r, and the next cycle scanning is started by again energizing the diodes serially from the innermost LEDs 11 and 1 r. Scanning operations are repeated periodically.

Now referring back to Fig. 4, the outputs from the photosensitive diodes 1 L to 1 6L of the left side sensing assembly are fed to and amplified by a set of amplifiers, generally denoted by 52. Similarly, the outputs from the photosensitive diodes 1 R to 1 6R of the right side sensing assembly are fed to and amplified by another set of amplifiers, generally denoted by 53. The output terminals of the amplifier sets 52 and 53 are connected, respectively, to analog multiplexors 54 and 55. These multiplexers are provided to select one input generated from an appointed photosensitive diode facing the energized LED to connect the thus selected input to the output terminals. The outputs from the multiplexors 54 and 55 are fed to comparators 56 and 57.

These comparators serve to exclude noise signals by allowing to pass and be amplified only the signals having potentials above a pre-set standard voltage level. The outputs from the comparators 56 and 57 are put into inverters 58 and 59 where they are inverted to be fed out therefrom as detection signals Se and S7, respectively. The detection signals Se and S, take the level ''1" only when the corresponding PDs are in the unexposed condition (or in the dark state).

A four-input AND circuit, designated by 60, puts out a signal S5 of "1" level when all of the binary code signals S30 to S33 are at the level "1", representing number "1 5" by the decimal system, namely when the outermost LED and PD pair is selected. Reference numeral 61 designates a D-type flip-flop (hereinafter referred to as DFF) which is set and reset when the clock signal S, is fed to its clock signal terminal C on the basis of the signal S5 fed to its D terminal and puts out a signal S20 from its output terminal at the set side (See (f) and (g) in Fig. 6.). This signal S20 takes the level "1'' nearly at the timing when all of the binary code signals S30 to S33 are at the level "0", representing number "0" by the decimal system, namely when the innermost LED and PD pair is selected.Reference numeral 62 designates an AND gate from which a signal S2, is fed to the clock signal terminals C of DFFs 63 and 64 at the same timing as the clock signal S4 when the signal S20 is at the level "1'' (See (g) and (h) in Fig.

6.) The flip-flop DFF 63 is set and reset when the signal S21 is put in through its clock signal terminal C on the basis of the detection signal S6 fed to its terminal D, and puts out a signal S8 from its output terminal at the set side.

Similarly, the flip-flop DFF 64 is set and reset when the signal S2, is fed to its clock signal terminal C on the basis of the detection signal S7 fed to its terminal D, and puts out a signal S9 from its output terminal at the set side. As will be understood from the foregoing, DFF 63 and 64 are flip-flops for storing, respectively, the detection signals S6 and S7 generated in response to the outputs from the innermost PD 1 L of the left side assembly and from the innermost PD 1 R of the right side assembly (See (h), (i) and (j) in Fig. 6.) The signals S8 and S9 are put into a reset signal generator circuit 65 from wich reset signals So and S22 are given out.The reset signal S22 takes the level ''1" when both of signal S8 and S9 are at the level"O", whereas the reset signal So takes the level ''1'' during the one clock period starting from the time when either of the signals S8 or S9 is at the level "1" (See (j) and (k) in Fig. 6.) In other words, the reset signal S22 is given out when the innermost PD of both of the left and right side assemblies receive lights, i.e. when no bank note is present at the detection position.On the other hand, the reset signal S,O is put out for a one clock period starting from the time when either one of the innermost PDs of left right side assembly is brought to the dark state, i.e. when a bank note is detected.

A counter circuit 66 for counting the scanning frequency is provided and has two decimal counters 67 and 68. After being reset by the reset signal S22, the counter circuits 66 begins to count the number of the signals S8 when both of the signals S8 and S9 take the level ''1'' (this condition being shown by the signal S" of (e) in Fig. 7), and puts out signals S,2 depending on the counted number. The counter circuit 66 gives out a signal S23 when the counted number reaches a predetermined number, and stops counting by itself after that time. The operations of the counter circuit are shown by (e), (f), (g) and (h) in Fig. 7.As seen from this Figure, in the present embodiment, the signal S,2 rises from "O" to "1" at the counts "8", "18" and "28", and the counter circuit stops counting at the count "30". Reference numeral 67 designates a circuit for generating an actuating signal S,3 for actuating a circuit, not shown, for determining the genuineness of the bank note and for discriminating the sort of bank note. The actuating signal S,3 takes the level ''1'' for one clock period from the time when the first clock signal S, rises after the counted number in the counter circuit 66 has reached "30" and the signal S23 has risen, and this actuating signal is fed out through the terminal 88.In a sample enable circuit 68, a sample enable signal S,4 takes the level ''1'' from the time when the first signal S, generated after the signal S,2 has risen falls to the time when the second signal S5 falls, and a signal S,4 takes the level "0" for the same period. Namely, the sample enable signal S,4 takes the level ''1'' for the period of the first scanning cycle after each rise of signal S,2, whereas the signal Sr4 takes the other level (See (g) and (j) in Fig. 7.) Reference numeral 69 designates a threeinput AND gate to which the sample enable signal S,4, the signal S5 and the clock signal S, are fed and subjected to AND operation.

The result of the AND operation by the AND gate 69 is given out as a data latch signal S,5.

Namely, the data latch signal S,5 is put out by the last clock signal S, just before the sample enable signal S,4 falls (See (j) and (k) in Fig.

7.) Reference numeral 70 designates a detection signal counting circuit having binary counters 71 and 72. The detection signal counting circuit 70 is reset when the signal 8a4 takes the level ''1''. When the signal S14 takes the level "0", i.e. when the sample enable signal S,4 takes the level , the circuit 70 is allowed to be ready for counting and cbunts the clock signals S4 by its binary counter 71 when the detection signal S8 takes the level ''1" and concurrently counts the clock signals S4 by its binary counter 72 when the detection signal S7 takes the level ''1''. In this manner, the number of LED-PD pairs shielded by the left and right portions of the travelling bank note 21 are counted by the detection signal counting circuit 70. The outputs from the binary counters 71 and 72 of the detection signal counting circuit 70 are added together by an adder 73, and the result of the addition operation by the adder 73 is fed to an integrating accumulating circuit 74.

The accumulating circuit 74 has two adders 75 and 76 and two data latches 77 and 78.

The circuit 74 is reset by the reset signal S,O.

The output from the adder 73 and the outputs from the data latches 77 and 78 are added by the adders 75 and 76, and the result of this addition operation is re-stored by the data latches 77 and 78 at the timing when the data latch signal Sis rises, whereby the results are accumulated. The output from the accumulating circuit 74 is put out through terminals 80 to 87 as forming width information signals TDo to TD7 and fed to the aforementioned circuit, not shown, for determining the genuineness of the bank note and for discriminating the sort of bank note.

In operation, when the clock signal generating circuit 40 begins to oscillate, the binary counter 41 begins to count to generate outputs for energizing the LEDs 11 to 1 61 and LEDs 1 rto 16 r serially one by one. Simultaneously, according to the outputs from the binary counter 41, the outputs from the PDs 1 L to 1 6L and PDs 1 R to 1 6R amplified by the amplifiers 52 and 53 are selected serially one by one by the analog multiplexers 54 and 55.

The scanning operations are cyclicly repeated.

When a bank note to be examined or inspected takes a position where it shields some of the light passages from the LEDs 11 to 1 61 and 1rto art the PDs 1Lto 16L and 1Rto 16R, either or both of the detection signals S6 and 87 takes the level ''1''. Assuming now that either one of the detection signals S6 or S7 takes the level "1" in the first place, either of the DFFs 63 or 64 is set and then a reset signal S,O is fed out from the reset signal generator circuit 65 followed by resetting of the accumulating circuit 74.When both of the detection signals S8 and S7 take the level "1" as the bank note travels, both of the DFFs 63 and 64 are set and the scan frequency counting circuit 66 begins to count the scanning frequency. At the eighth, eighteenth and twenty-eighth scanning operations, the detection signal counting circuit 70 is allowed to be ready for counting under the action of the signal from the sample enable circuit 68 and counts the number of LED-PD pairs shielded by the left and right portions of the bank note. At the ends of these three cycle scanning operations, the counted numbers of LED-PD pairs of the left and right side assemblies are added by the adder 73.The information-relating to width of bank note obtained as the result of the addition operation by the adder 73 is accumulated by the integrating circuit 74 at the timing of the rise of the data latch signal S15. Results of the intergrating operatiom, i.e. the width information signals TDo to TD7, are given out from the terminals 80 to 87 as the informmation on which basis the genuineness or sort of bank note is to be judged. The scan frequency counting circuit 66 stops counting when the count number reaches "30", whereupon the circuit 67 brings the actuating signal S13 to the level "1" '' which is fed out through the terminal 88.At the timing of the actuating signal S13, the width information signals TDo to TD7 are supplied to the circuit, not shown, for determining the genuineness of the bank note and for discriminating the sort of bank note.

In the above embodiment, the signal S12 rises at the counts "8", "1 8" and "28".

However, the timing of generating the signal S,2 may be varied depending on the length of bank note to be inspected. In the case where the width of bank note is determined by a single scanning cycle, the adders 75 and 76 of the accumulating circuit 74 may be dispensed with.

It should be appreciated from the foregoing that the device comprises a plurality of light emitting elements arranged transversely of the travelling sheet material and a plurality of light receiving elements each opposing a respective light emitting element and that the light emitting elements are energized serially one by one with the outputs from the light receiving elements selectively scanned serially one by one. More specifically, a certain light receiving element is paired with an opposing light emitting element so that only the output signal from the paired light receiving element is sensed at each time a certain light emitting element is energized. Thus the embodiment has the advantage that the width of the sheet material can be determined precisely even if the sheet material passes through the device in an upwardly-curved condition.

It will be apparent to those skilled in the art that various modifications may be made in the device without departing from the spirit and scope of the invention. Accordingly the foregoing description is to be contrued as illustrative only and not limiting.

Claims (5)

1. A device for monitoring the width of sheet material comprising a plurality of light emitting elements, a plurality of light sensitive elements opposing corresponding light emitting elements, the light emitting elements and light sensitive elements being arranged for the passage of sheet material therebetween, and an electric circuit for monitoring the width of the sheet material by the light signals received, by the light sensitive elements, the electric circuit including means for selectively energizing the light emitting elements one by one and scanning means for selectively scanning outputs generated by the opposing light sensitive elements in response to the light signals they receive.

2. A device according to claim 1, wherein said light emitting elements are light emitting diodes and said light sensitive elements are photosensitive diodes.

3. A device according to either claim 1 or claim 2, wherein the selective energizing means includes a clock signal generating circuit and a counter for counting clock signals generated from the clock signal generating circuit to give out output signals for energizing the light emitting elements serially one by one.

4. A device as claimed in any preceding claim wherein the scanning means comprises an analog multiplexor for serially selecting the outputs from the light receiving elements one by one.

5. A device for monitoring the width of sheet material substantially as hereinbefore described with reference to and as shown in Figs. 2 to 7 of the accompanying drawings.