GB2047474A - A strip carrying devices for processing electrical signals, and a method of producing the strip - Google Patents

A strip carrying devices for processing electrical signals, and a method of producing the strip Download PDF

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Publication number
GB2047474A
GB2047474A GB7929905A GB7929905A GB2047474A GB 2047474 A GB2047474 A GB 2047474A GB 7929905 A GB7929905 A GB 7929905A GB 7929905 A GB7929905 A GB 7929905A GB 2047474 A GB2047474 A GB 2047474A
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United Kingdom
Prior art keywords
strip
substrate
conductors
conductive
zone
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GB7929905A
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Bull SA
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Bull SA
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Publication of GB2047474A publication Critical patent/GB2047474A/en
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Dispersion Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)
  • Multi-Conductor Connections (AREA)
  • Packages (AREA)

Abstract

The invention relates to a strip 10 formed by an electrically insulating substrate 19 carrying conductive zones 20 regularly distributed along its length and each provided with at least one device 11 for processing electrical signals, and also with contact regions. The device has an array of conductors 16 of which the outer ends are connected to respective connecting points 21 belonging to the corresponding conductive zone. To make such a strip 10 the conductive zones 20 are formed on a flexible continuous film 10 of the cinematograph type, and electrical devices 11 contained in openings 14 in a second strip 12 are positioned aligned with these conductive zones, cut away and connected to the zones. <IMAGE>

Description

SPECIFICATION A strip carrying devices for processing electrical signals, a method of producing the strip, and the application of the strip to a member for processing signals The present invention relates to a method of producing a strip carrying devices for processing electrical signals, to the corresponding strip, and to the application of the strip to a member for processing electrical signals.
A known strip of this kind is described in particular in US patent specification no.
3,689,991. This strip carries conductive zones which are regularly distributed along the length of one of its faces and which are each provided with a device for processing electrical signals, such as an electronic integrated circuit device for example. Each conductive zone consists of an array of conductors, parts of which are secured to the strip and whose free inner ends converge into the central region of an opening formed in the strip. The said devices have their output terminals connected to the inner ends of respective ones of the conductors and are thus supported at the centre of the opening by the conductors alone. The free outer ends of the conductors rest on the strip and form contact regions which are intended in particular to allow the satisfactory operation of the associated device to be checked.Such a strip is particularly useful for equipping a connecting substrate with integrated circuit devices, since it is readily possible to detach the devices from the strip by severing the conductors near the periphery of the corresponding openings, as is described in particular in our copending applications Nos. 10514/77 (Serial No 1570406) and 38210/77.
It is also on the basis of a strip of this kind that the construction of a portable card of the credit card type is described in our copending patent application No. 53214/76 (Serial No 1567784).
In this specification, an integrated circuit device, which is equipped with output conductors attached to a thin substrate and terminating in contact regions, is accomodated in a cavity in the card. This cavity may be an embossed area or a hollowed-out area of the card or even a hole. The substrate carrying the device is secured to the card either directly or by adding a cover. The contact regions are accessible through holes pierced in the card or the cover. Also, this patent specification discloses a method of producing such a card from at least two strips, one being cut to the size of the card and the other, carrying an integrated circuit device, being cut out to act as a substrate. Possibly a third strip may be used to produce the said covers.
It has been found that the device-carrying strip described above is particularly poorly suited for producing a credit card of the above mentioned kind. The addition of a cover is expensive and its thickness causes a corresponding reduction in the already small thickness allowed to the substrate and the device in the cavity formed in the standard thickness of a credit card.In this regard, it should be remembered that standard ISO/DIS 2894 promulgated by the International Standards Organisation on the subject of credit cards, lay down for them a rectangular shape measuring 85.59i0,12 mmX53.97*0.06 mm and a thickness of 0.76 + 0.08 mm to which a maximum of 0.50 mm can be added to show for example the name and address of the holder of the card by means of applied items (such as sticky labels) or by embossing the card itself. Another drawback of using the device-carrying strip mentioned above resided in the need to provide contact holes in the card, which have to be filled with a conductive substance to prevent dust or other undesirable insulating substance from affecting the standard of contact.Furthermore, although the substrate illustrated in Fig. 4 of the abovementioned patent application No. 53214/76 (Serial No 1567784) appears more suitable for insertion at a very small thickness in a standard credit card, it still suffers from the fact that it cannot be used on its own without a cover due to the fact that otherwise the electronic device associated with it would have its working face protected from external effects only by a thin encapsulation which would, admittedly, prevent any illicit operations being performed on the circuits of the device, but whose mechanical and thermal protective properties would leave something to be desired.
The invention provides a strip suitable for the construction of a standard cavity-containing card of the above-mentioned kind, a method of producing the strip, and the application of the strip to the production of a signal processing device, such for example as a credit card or an integrated circuit package.
In accordance with the invention, a strip carrying conductive zones regularly distributed along its length and each provided with at least one device for processing electrical signals and with contact regions, is characterised in that the said device is provided with an array of conductors connected to the strip by respective ones of the said contact regions.
The method according to the invention for producing a first strip formed by an electrically insulating substrate carrying conductive zones regularly distributed along its length and each provided with at least one device for processing electrical signals and with contact regions, is characterised in that it consists in taking at least one second strip having, along its length, a plurality of adjacent openings in which the said devices are supported by an array of conductors which are respectively connected at one end to the output terminals of the devices and which at the other ends rest on the said first strip; in taking a ribbon of electrically insulating material forming the said substrate of the said first strip; in forming on the said substrate, along its length, the said conductive zones including connecting points; in severing one of the said arrays of conductors from the said second strip; in arranging the severed array of conductors against one of the said zones on the first strip in such as way as to align respective free ends of the severed conductors with at least parts of the said connecting points belonging to the corresponding conductive zone; and in soldering the said free ends of the conductors to the said connecting points.
The invention also has as an object a member for processing electrical signals which is characterised in that it incorporates a part of the said strip including at least one conductive zone.
The features and advantages of the invention will be more clearly apparent from the following description, which is given with reference to the accompanying drawings. In the drawings: Figure 1 is a perspective view of an embodiment of strip according to the invention in conjunction with a prior art which is used to show how the strip of the invention may be produced; Figure 2 is a view from below of part of a strip according to the invention as shown in Fig. 1; Figure 3 is a view from below of an embodiment of credit card incorporating an integrated circuit chip which has been detached from a strip as shown in Figs. 1 and 2; Figure 4 is a sectional view on line IV-IV of Fig. 3; Figure 5 shows a modified embodiment of chip which can be detached from a strip according to the invention; Figure 6 is a sectional view on line VI-VI of Fig. 5;; Figure 7 is a view from above of a package for two integrated circuit devices which employs a chip taken from a strip according to the invention; Figure 8 is a sectional view of the line VIII-VIII shown in Fig. 7; Figure 9 is a sectional view similar to that in Fig. 7 of another embodiment of package which makes use of the principles of the invention; and Figure 10 is a sectional view of the strip according to the invention on the line X-X shown in Fig. 1, which illustrates a particular method of attaching an external conductor of an integrated circuit device to a conductor of the strip by means of a hole.
Fig. 1 is an illustration of a strip 10, according to the invention, which carries devices 11 for processing electrical signals, of the method of producing the strip using as a basis a prior art strip 12 of the kind described in the above-mentioned U.S. patent specification no. 3,689,991 from which the devices 11 are taken, and of the method of making use of the strip 10 which is the subject of the invention.
The prior art strip 12 is in the form of a cinematographic film of flexible and electrically insulating material in which are formed two rows of perforations 13 regularly spaced along the two edges of the film, and a series of axially eqispaced openings 14 which are square in shape in the example illustrated.
Also in this example, the two opposing sides of each openings 14 next to the edges of the strip carrying the outer ends which form contact regions 15, of any array of eight conductors 1 6 which converge into the central region of the opening. Each device 11, which in the present case is an electronic integrated circuit device, has its output contacts connected to the inner ends of respective conductors 16.
The utilisation principle of the strip 12 is as described for example in the above-mentioned patent application no. 10514/77 (Serial No 1570406). The strip 12 advances step by step in the direction of arrow 17 in such a way that the central axis 18 normal to each opening 14 successively coincides with that of a tool (not shown). It is along the axis 18 that the tool successively severs the conductors 16 belonging to the appropriate opening 14, close to the edges of the opening, and along this axis that it applies the detached device 11 to a substrate, from which will be formed the strip 10 according to the invention, as will now be described.
In the embodiment illustrated, the substrate 1 9 of the strip 10 is also a cinematographic film of electrically insulating material having two rows of lateral perforations 13. At the beginning, that is to say before the devices 11 detached from the strip 12 are added to it, the strip 10 according to the invention has conductive zones 20 regularly disposed in its longitudinal central region. In what follows the five successive zones which the strip 10 carries in the direction of arrow 17 (which arrow also indicates the direction of movement of the strip 10 in the embodiment illustrated) will be referred to as 20a, 20b, 20c, 20dand 20e, it being understood that as a general rule the production of a strip according to the invention in no way requires the directions of movement to be identical since all that in fact is required is the coincidence between an opening 14 and a conductive zone 20 which is indicated in Fig. 1 by axis 18.Returning to the description of the strip 10, it will be seen that each of the conductive zones 20a to 20e includes connecting points 21 which are arranged in such a way as to allow the end of respective conductors 16 associated with each device 11 detached from the strip 12 to be attached by soldering and thus the devices to be mounted in the way shown for zones 20d and 20e in Fig. 1. An example of a soldered joint particularly suitable for the strip 10 will be described below with reference to Fig. 10. It is these conductive zones which will be detached from the strip 10, together with a part of the substrate 19 and the corresponding device 11, to form a wafer 22 intended to fit into a member for processing electrical signals, as will be seen at a latter stage with reference to Figs. 3 to 9.
To complete the description of the strip 10, it will be mentioned that in the embodiment selected the conductive zones 20 are formed on one face (the bottom face of the strip 10 in Fig. 1) from a continuous conductive layer 23 which is etched in the manner shown in Figs.
1 1 and 2. The connecting points 21 can be seen on the other face of the strip and, in embodiment shown in Fig. 10, correspond to holes 24 passing through the substrate 19. At the time of manufacture, depending upon the material forming the substrate 19 and the soldering technique used, the piercing of the holes 24 may take place either before the conductive layer 23 is deposited or after.
When using the kind of attachment illustrated in Fig. 10, the conductive layer 23 is formed after the substrate 19 has been pierced so that it plugs the holes 24, in each of which solder forming a connecting point 21c is then deposited to retain the ends of the conductors 16. It is therefore beneficial in this case to apply the conductive layer 23 to the substrate 19 by bonding or any other method of attachment familiar in the art. A more detailed description of this method of connection by soldering will be found in a French patent specification no. 7829845 which was filed in the name of the present applicant.It is of course understood that known methods of soldering, using metallised holes for example, may also be employed, but such techniques are for more complicated and call for at least part of the connecting points 21 to extend to the face of the strip intended to receive the device 11.
As is more clearly apparent from the embodiment illustrated in Fig. 2, each conductive zone 20 belonging to the conductive layer 23 is circular in shape and consists in essence of eight contact pads 25 which communicate respectively with the eight conductors 16 of each device 11 via the eight connecting points 21 corresponding to the holes 24.
Preferably, the area 26 complementary to the eight pads 25 is also covered by the conductive layer 23 in order, in particular, to increase the stiffness of the wafer 22 when it is detached from the strip 10 and to even up the surface of the wafer carrying the contact pads 25, and possibly to allow the wafer to be earthed. In addition, it is useful, when at the beginning the conductive layer 23 is a uniform continuous band and the etching operation is performed electrolytically, for all the conductive zones 20 to be connected together to form a common electrode. This is the case which is shown in Figs. 1 and 2, in which it can be seen that the contact pads 25 and the complementary area 26 of each zone 20 are connected by bridges 27 to two lateral buses 28.
The way in which the strip 10 is used is similar to that in which the strip 12 is used.
The strip, advancing step by step under a tool (not shown) in the direction of arrow 17, brings the axis of each circular conductive zone 20 into line with the axis of the cutting tool. The latter then detaches the zone 20 by cutting through the bridges 27 and the material 19 of the strip 10 to produce a wafer 22.
The severing of the bridge 27 isolates the contact pads 25 and the remaining area 26 from one another electrically.
Figs. 3 and 4 show an example of a wafer detached from a strip according to the invention, such as the wafer 22, applied to a portable card such as a credit card 30 of the kind described in the above-mentioned patent application No. 53214/76 (Serial No 1567784). This card is in the form of a single sheet 31 of plastics material which, in accordance with the above mentioned standard ISO/DIS 2894, has a thickness of 0.76 mm and carries characters 32 (produced by deforming the sheet 31 in the example illustrated) whose height may not be more than 0.5 mm above the upper face of the sheet 31. The wafer 22 is accommodated in a cavity 33 formed in the lower face of the sheet 31, with the device 11 enclosed in the cavity and the contact pads 25 preferably flush with the lower face of the card.For this purpose the cavity 33 has a circumferential shoulder 34 on which rests the periphery of the substrate 19 of the wafer 22. The wafer may be bonded or soldered to the shoulder 34 or, as shown, may be bonded by a ring of material 35 having two adhesive faces.
Figs. 5 and 6 show a modified embodiment of wafer 22' which can be obtained from a strip similar to the strip 10 of Fig. 1. The similarity is highlighted by the fact that in Figs. 5 and 6 the same reference numerals are used for the same items as are shown in the previous Figs. It can thus be seen that in the modified embodiment, each conductive zone 20 is associated with a plurality of integrated circuit devices 11 a, 11 b and includes a circuit 36 (36a to 36d) for interconnecting these devices. The format of the devices, which is determined by their dimensions, may be the same, as shown, or different. The same also applies to the type of device, which is determined by the functions of the circuits included in the devices.In case where the devices 11 a, 11 b are of different types and/or of different formats. it will be clear from the above description relating to Fig. 1 that the method of producing a strip according to the invention from which wafers 22' may be obtained then invovles a plurality of prior art strips 12 carrying devices of different respective types and formats.
Figs. 5 and 6 also show another modification. In effect. in the case of Figs. 1 to 4. it is the working face of each device 11 which is adjacent the substrate 19 of the strip 10. in Figs. 5 and 6 on the other hand the devices 11 a and 1 flibhave their backs to the substrate 19 of the strip while the conductors 16.
which originate from the working faces of the devices. are bent down for attachment to the connecting points 21. This modification is here due to the presence of the interconnecting earthing layer 36a on which the devices 11 a and 11 b rest on wafer 22'. In this way the earthing layer 26a also acts as a radiator to dissipate the heat released by the integrated circuit devices 11 a and 11 6. It is understood that this method of attaching the devices could also be employed in the case of Figs. 1 to 4, for example by turning over the basic strip 12 in Fig. 1.
Generally speaking. the material of the substrate 19 forming a strip according to the invention may also be of any kind. In the embodiment presently adopted, the material selected is that sold under the name "Kap ton". due to the fact that its thickness can be reduced to very small values (less than 0.2mm. the wafer 20 presently produced having a substrate 0.125 mm thick) whilst retaining good flexibility without breaking and whilst allowing conductive layers to be deposited on at least one of its faces. It is thus possible to accommadate a wafer, the wafer 22 for example, in a cavity 33 which need be a little more than 0.5 mm deep in a standard card 0.762 mm thick.
It will be realised how advantageous it is to have a continuous flexible and homogeneous film 19 as shown in Fig. 1, from which the substrate of the wafer may derive the requisite qualities of flexibility. Thus, any plastics material such as mylar or any relatively flexible material such as epoxy-glass would be suitable. On the other hand, in cases where the substrate of the wafers is required to be rigid, a possibility which may be envisaged is to form a complex strip in which the substrates 19 of wafers would each be obtained from tablets regularly disposed along the length of a flexible film in the openings of the film or added to it. As an example of a rigid material it would thus be in accordance with the invention. To sum it up, it is evident from the above description that a strip according to the invention can be used in the same way as a prior art strip 12.It is however more advantageous than the latter due to the fact that it provides a single (incorporating one integrated circuit device) or compex (incorporating a plurality of interconnected devices) complete assembly which is flexible or rigid and which is provided with output terminals which can be easily used in complex assemblies. An application which is readily deducible from what is said above consists in the production of integrated circuit packages, of the kind which is described for example in a French patent application no. 7829 844 applied for by the present applicant. Figs. 7 and 8 show an embodiment of package which can be produced in accordance with the invention. whilst Fig. 9 shows a modified embodiment of such a package.
Fundamentally, the structure of the package 40 shown in Figs. 7 and 8 is similar to the structure shown in Figs. 5 and 6. this fact being illustrated by the use of the same reference numerals. What distinguishes the two structures is essentially that in the package 40, the devices and at least part of their interconnecting circuit 36 (36ato 36a) is protected by an insulating encapsulating substance 41. In addition. in the event of the flexibility of the package being too great (because of the required thinness of the structure 19 for example) reinforcing means 42 are provided which increase the stiffness of the package. In the embodiment illustrated, these means are formed by four applied members formed from the same material as the substrate 19 which are disposed at the periphery of the substrate. To produce such a package.
it is clear that the encapsulating substance 41 and the reinforcing members 42 (if present) may be arranged on the strip itself before the wafers are cut out, in which case the wafers will themselves form the packages, or else they may be arranged after the wafers are cut out, which wafers are of the kind shown in Fig. 1.
A modified embodiment of package obtained from a strip according to the invention is shown in Fig. 9. The modification produces a relatively elaborate package 43 which may be obtained directly or indirectly from a strip according to the invention, as mentioned in relation to package 40. A first modification lies in the fact that the substrate 19 has at least one integrated circuit device on both of its faces. The second modification lies in the superimposition of conductive layers to form the circuit 36 for interconnecting devices on one and the same face. In the embodiment illustrated, one face of the substrate 19 carries two devices 11 a 11 b and the other face carries one device 11 C. The interconnecting circuit 36 connects the three devices together by means of through-connections 44 arranged in the substrate ~ 9 and comprises two layers 36', 36" superimposed on the face carrying the two devices. The devices on both faces of the substrate 19 9 are of course protected by an encapsulating substance 41 a, 41 b, possibly associated with stiffening means 42a, 42b.
The output pads 25 may be situated on either of the two faces of the substrate but it would also be possible for both face to carry them.
A wafer from a strip according to the invention may thus be used in a number of applications, by being inserted in a signal processing device such as a credit card or by itself forming an independent component, with or without modification or the addition of supple- mentary means, as in the case of an integrated circuit package.
In other words, the invention is in no way restricted to the embodiments which have just been described and illustrated and in fact covers all means of equivalent to the means described and illustrated, as well as combinations thereof conforming to the accompanying

Claims (26)

claims. CLAIMS
1. A strip of the kind formed by an electrically insulating substrate carrying conductive zones regularly distributed along its length each provided with at least one device for processing electrical signals and with contact regions, characterised in that the said device is provided with an array of conductors of which the outer ends are connected to respective connecting points belonging to the corresponding conductive zone.
2. Strip according to claim 1, characterised in that each of the said conductive zones is associated with a plurality of devices and comprises an interconnecting circuit which connects the devices together.
3. Strip according to claim 1 or 2, characterised in that each said device is arranged on the same face of the substrate of the said strip and the said contact regions are situated on the other face of the substrate, the said conductive zone containing holes passing through the substrate.
4. Strip according to claim 2, characterised in that the said devices and their interconnecting circuit are arranged on both faces of the substrate.
5. Strip according to claim 3 or 4, characterised in that the said holes form the said connecting points, the said conductive zone including portions which plug these holes at one face and the said outer ends of the conductors of the device being attached by solder contained in respective holes.
6. Strip according to any of claims 1 to 5, characterised in that each said device and at least a part of the said conductive zones, not including the said contact regions are embedded in an encapsulating substance.
7. Strip according to any of claims 1 to 6, characterised in that each conductive zone includes means for increasing the stiffness of the substrate which is intended to be detached from the strip.
8. Strip according to any of claims 1 to 7, characterised in that the substrate is a flexible, continuous and homogeneous film of the cine- matographic type.
9. Strip according to any of claims 1 to 7, characterised in that the substrate is a composite film formed from a continuous flexible part and rigid parts regularly distributed along the said strip and provided respective with the said conductive zones.
1 0. Method of producing a first strip formed by an electrically insulating substrate carrying conductive zones regularly distributed along its length each provided with at least one device for processing electrical signals and with contact regions, characterised in that it consists: ~in taking at least one second strip containing along its length a plurality of adjacent openings in which the said devices are carried by an array of conductors which respectively connect up with the output regions of the devices at one end and which at the other end rest on the said first strip, ~in taking a strip of electrically insulating material forming the said substrate of the said first strip, ~in forming on the said substrate, along its length, the said conductive zones including connecting points, ~in cutting away from the said second strip one of the said arrays of conductors, ~in arranging the said cut away array of conductors against one of the said zones at the first strip in such a way as to align the free ends of respective cut conductors with at least part of the said connecting points of the corresponding conductive zone, ~and in soldering the said free ends of the conductors to the said connecting points.
11. Method according to claim 10, characterised in that the above mentioned formation of each conductive zone on the substrate of the first strip includes the formation of holes in the said substrate at predetermined points in the said zone.
12. Method according to claim 11, characterised in that the above-mentioned formation of each conductive zone on the substrate of the first strip includes disposing parts of the donductive zone in such a way as to plug each hole at one face of the substrate; the said arrangement of the free ends of the conductors is represented by lining up these ends with respective holes at the unplugged face so that the said holes form the said connecting points, and the soldering of the ends of the conductors in the holes comprises introducing solder into each hole.
13. Method according to claim 12, characterised in that the said soldering of the ends of the conductors in the holes includes bending the ends of the conductors.
14. Method according to any of claims 10 to 13, characterised in that it includes applying an electrically insulating encapsulating substance which encapsulates at least part of each conductive zone to at least one face of the substrate but not to the aforesaid contact regions.
15. Method according to any of claims 10 to 13, characterised in that it includes increasing the stiffness of the substrate by adding reinforcing members to it at least at the point where each zone is situated.
16. Method according to any of claims 10 to 15 characterised in that the substrate is a continuous and momogeneous flexible film of the cinematographic type.
17. Method according to claim 16, characterised in that the aforesaid formation of each zone includes the application of a continuous conductive ribbon to at least one face of the substrate.
18. Method according to any of claims 10 to 16, characterised in that the substrate is a composite film formed by a continuous flexible part and rigid parts regularly distributed along the said strip and provided respectively with the said conductive zones.
19. Member for processing electrical signals, characterised in that it comprises a wafer extracted from the strip according to any of claims 1 to 9 and including at least one of the said conductive zones.
20. Member according to claim 19, of the credit card type, characterised in that the said wafer is fixed in a cavity in the sheet forming the said card.
21. Member according to claim 19, characterised in that it forms a package for at least one integrated circuit device.
22. Member according to claim 21, characterised in that it comprises the said wafer and an insulating substance which encapsulates at least part of the conductive zone of the said wafer on at least one of its faces but not the said contact regions.
23. Member according to claim 21 or 22, characterised in that it comprises the said wafer and means for increasing the stiffness of the said wafer
24. A strip substantially as hereinbefore described with reference to the accompanying drawings.
25. A method of producing a strip substantially as hereinbefore described with reference to the accompanying drawings.
26. A member for processing electrical signals substantially as hereinbefore described with reference to the accompanying drawings.
GB7929905A 1978-10-19 1979-08-29 A strip carrying devices for processing electrical signals, and a method of producing the strip Withdrawn GB2047474A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7829846A FR2439438A1 (en) 1978-10-19 1978-10-19 RIBBON CARRYING ELECTRIC SIGNAL PROCESSING DEVICES, MANUFACTURING METHOD THEREOF AND APPLICATION THEREOF TO A SIGNAL PROCESSING ELEMENT

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GB2047474A true GB2047474A (en) 1980-11-26

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JP (1) JPS5556639A (en)
DE (1) DE2942397A1 (en)
FR (1) FR2439438A1 (en)
GB (1) GB2047474A (en)
IT (1) IT7926626A0 (en)
NL (1) NL7905298A (en)
SE (1) SE7906961L (en)

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US4483067A (en) * 1981-09-11 1984-11-20 U.S. Philips Corporation Method of manufacturing an identification card and an identification manufactured, for example, by this method
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GB2169750A (en) * 1984-12-20 1986-07-16 Raytheon Co Flexible cable assembly
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US5647122A (en) * 1994-06-15 1997-07-15 U.S. Philips Corporation Manufacturing method for an integrated circuit card
US5850690A (en) * 1995-07-11 1998-12-22 De La Rue Cartes Et Systemes Sas Method of manufacturing and assembling an integrated circuit card
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DE2942397A1 (en) 1980-04-30
SE7906961L (en) 1980-04-20
NL7905298A (en) 1980-04-22
FR2439438A1 (en) 1980-05-16
JPS5556639A (en) 1980-04-25
IT7926626A0 (en) 1979-10-19
FR2439438B1 (en) 1981-04-17

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