GB1590404A - Methods of and apparatus for encoding and recovering binary digital signals - Google Patents

Abstract

In this method, which can be used, in particular, in transmission systems and in magnetic storage and recovery systems for digital data, for example three bits in each case (three time intervals T) of a binary data signal are combined to form one word. This word corresponds to data cells of the transmission or recording signal. A data cell (Z) exhibits six possible points of signal change (P1 to P6). The binary data signal is converted into a transmission or recording signal in such a manner that a minimum distance (3/2 T) and a maximum distance (6 T) is always ensured so that self-clocking is possible during the reading. Since it is not sufficient only to pay attention to the signal changes within one data cell (Z) but care must also be taken that two signal changes (P5 and P1) of adjacent data cells (e.g. Z4 and Z5) are not closer together than the required minimum distance (3/2 T), the present word is in each case compared with the preceding and following word. If it is found for a word, that a signal change should take place at a point (P5) which is not the minimum distance (3/2 T) away from the point at which a signal change (P1) for another word should take place, the two signal changes are combined at one point (P6). For this purpose, the device for carrying out the method has a coding device with three coders (17, 24, 29) for the present, preceding and following word and switching means (33) which provide a signal change at the boundary (P6) between the data cells (Z4, Z5) instead of the two prevented signal changes (P1, P5). <IMAGE>

Description

(54) IMPROVEMENTS IN METHODS OF AND APPARATUS FOR ENCODING AND RECOVERING BINARY DIGITAL SIGNALS (71) We, SPERRY RAND CORPORATION, a Corporation organised under the laws of the State of Delaware, United States of America, of 1290 Avenue of the Americas, New York, New York 10019, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following state ment: The present invention relates to methods of and apparatus for encoding and recovering binary digital signals, and has particular application to the recording of such signals on moving magnetic media.

Binary information is recorded in the magnetic surface of a disc or tape by changes in the direction of magnetisation.

In one simple system to be discussed below by way of example, a binary 1 or 0 is rep resented by a transition or the absence of a transition in the magnetisation in successive time intervals. In order to read information so recorded a clocking circuit is necessary, and this defines a recovery window for each consecutive interval, which is examined for the presence or absence of a transition.

To avoid the need for a separate clock channel it is desirable that the recording system used should be self-clocking. This is achieved by the use of a phase-locked oscillator which is synchronised with the re-.

corded signal, and which is employed to generate the recovery windows. To enable this to be done it is essential that the system of recording employed should ensure that no very long period can occur without a transition, otherwise it would be impossible to ensure that the phase-locked oscillator maintains its synchronism with the recorded signal, or, as is more usually the case, a selected harmonic of the signal.

A further problem that arises is that of bit-shift. When signals are recorded at a high density the recorded transitions are affected by interaction with neighbouring transitions, and when reproduced may be found to have shifted from their nominal positions. The amount of this bit-shift depends on the packing density and the extent to which the transitions adjacent to each side of the reproduced signal transition are asymmetrically disposed. This bit-shift sets an upper limit to the recording density, since if the signals are recorded at too high a density the bit-shift in some cases may be sufficient to bring some of the transitions outside their recovery window, so that they fail to be detected and the data recovered are erronous.

It is an object of the present invention to provide methods of, and apparatus for, encoding and recovering binary digital signals suitable for use in self-cocking systems and which permit signals to be recorded at a high packing density.

In a method according to the present invention of encoding an input stream of binary electric signals into an output signal stream the input signal stream is divided into words of uniform length, and each word is encoded into another word to produce a new series of words of uniform length and each having a greater number of digits, each encoded word being modified as necessary with reference to the preceding and following encoded words by merging l's within and/or between the encoded words so that in the output signal stream comprising the encoded words successive l's are separated by a minimum spacing greater than the least spacing of the input signal stream, and by a finite maximum spacing. The designation '1' applies to pulses, transitions, and the like. The input signal stream may be divided, for example, into words of three digits which are encoded into words of six digits in such a way that successive l's are separated by at least two zeros in the encoded digit stream.

If the encoded digit stream is now recorded, for example, on a magnetic disc in such a way that the l's are represented by transitions in the magnetisation, and the 0's by the absence of any transition, the relatively wide separation of the transitions ensured by the code allows the recording to be carried out at a higher density than would have been possible with the original digit stream before running into problems with bit shift.

The invention also includes apparatus adapted to carry out the method comprising an information shift register arranged to receive the input signal stream in series, means to divide the contents of the information shift register into three consecutive Words of uniform length, encoding circuits to supply the encoded digits of the second of the three words together with appropriate digits of the preceding and followinlg encoded words derived from the first and the third word respectively, to merging and gating circuits which supply the encoded second word, modified as necessary, in parallel to a signal shift register, and means reading out in series each encoded word from the signal shift register thereby to provide the output signal stream. Of course apparatus will be needed to decode the encoded digit stream and recover the original signals, and this may work on a similar principle, and may comprise a signal shift register arranged to receive the encoded words sequentially and to contain at each decoding cycle an encoded word and one or more end digits of the preceding encoded word, gating circuits operating on the contents of the signal shift register in parallel to decode the encoded word, including recovery of merged l's, and to supply the decoded word in parallel to an information shift register, and means for reading out in series the decoded words from the information shift register.

The invention also includes within its scope a complete data recording and recovery system comprising signal encoding apparatus as described above, arranged to provide encoded signals to magnetic recording and reading apparatus, and a decoder arranged to receive encoded signals from the magnetic recording and reading apparatus.

The invention will be further described by way of example with reference to the accompanying drawings, in which Figure 1 is a waveform diagram sho'v- ing a series of data to be recorded and the corresponding recording waveforms according to various prior art encoding systems and the system of the present invention.

Figures 2 and 3 are tables showing properties of the coding systems of Figure 1 respectively for the prior art and for the system of the present invention.

Figure 4 is a diagram of a single data cell, Figure 5 shows the recorded signal waveform of a data pattern taken by way of example to illustrate the present invention.

Figure 6 is a schematic diagram of an encoding circuit employing the invention.

Figures 7 and 8 are tables explaining the encoding process.

Figure 9 is a schematic diagram of a decoding circuit employing the invention. Figure 10 is a table explaining the operation of the circuit of Figure 9. Figures 1 la and 1 ib are timing diagrams relating to the operation of the circuits of Figures 6 and 9 respectively.

Figure 12 is a schematic diagram of a recording and recovery system incorporating the circuits of Figures 6 and 9, and Figure 13 is a table showing an alternative arrangement of code signal position. Figure 1 shows a number of waveforms representing recordings of data. The time axis extends from left to right of the Figure, and in successive time intervals, each of duration T, a binary 1 or 0 is to be recorded, the string of data being shown across the top of the Figure.

The first waveform shows the NRZI code. In this a 1 is represented by a Eansition in the centre of each interval T, while the absence of a transition indicates a 0. It will be apparent that the closest spacing Smin of the transitions is equal to T, and the recovery window is + 0.5T. The maximum interval that can occur without a transition, Sway, is unlimited, representing the case where there is an indefinitely long sequence of zeros. This code therefore is not suitable for a self-clockng system, in which the transitions must occur at reasonably frequent intervals to ensure proper synchronisation of the clocking oscillator.

The second waveform in Figure 1 is representative of the FM code, in which a transition at the centre of a bit interval represents a 1 and the absence of a transition represents a 0 as before, but an additional transition occurs at each boundary between bit intervals. These additlonal tran- sitions serve entirely for clocking purposes. In this case Spin = T/2 and Smax = T, and since there is at least one transition per bit interval the transitions can be used to synchronise a phase-locked oscillator and so provide the necessary clocking signals for generating the recovery windows. Since the minimum spacing of the transitions Smin = T/2, recording can be carried out at only about half of the density obtainable with the NRZI code before bit-shift becomes a limiting factor.

The clock signal must generate a recovery window of a half a bit interval, that is to say, + 0.25T in order to discriminate between the data transitions and the clock transitions.

The third waveform in Figure 1 represents encoding of the data in the Gabor code described in U.S. patent 3 374 475. In this code, which is more fully described in the above-mentioned patent, the encoded signal transitions occur either at the boundaries between the bit intervals, or at the 1/3 and 2/3 positions between the bound aries. With this code Smin = 2T/3. As explained in the U.S. Patent the density of recording which can be attained without problems of bit-shift is one-third greater than with the FM code. Smax = 4T/3 ensuring that transitions occur at a frequency suffi cient to ensure the proper synchronisation of a clocking oscillator.

The last of the prior art codes represented in Figure 1 is the MFM code. In this code a binary 1 is represented by a transition at the middle of a data cell, and an additional clocking transition is introduced at the boundary of a data cell if, and only if, there is no data transition in the preceding or following cell. With this code Smin = T, and Smax = 2T, so that the code allows the high packing density of the NRZI code while at the same time ensuring transitions occur at a sufficient frequency to ensure efficient synchronisation of a clocking oscillator. The properties of this code and of the other prior art codes are summarised in the table of Figure 2.

The lowermost waveform of Figure 1 shows the data of that Figure encoded in the form used in the preferred embodiment of the present invention. In this code the input data are grouped into three-bit words, which are then coded into six-bit words, which are modified as necessary with reference to the preceding and following words so as to produce a string of digits in which the l's which represent data transitions are separated from one another by at least two, but not more than eleven zeros. Bearing in mind that the coding replaces the threedigit input words by six-digit output words, it will be seen that Smin = 3T/2 and Smax = 6T. This code therefore allows a fifty percent increase in packing density over the MFM code before running into problems with bit-shift, and it ensures that there are sufficient transitions under all circumstances to allow adequate synchronisation of a clocking oscillator. The properties of this code, which will be referred to herein as 3PM (short for three-phase modulation), are summarised in the table of Figure 3.

Figure 4 is a diagram showing the timing of signal transition points during a time period corresponding to three data cells of Figure 1 in the coding system of the present invention. The period Z= 3T is subdivided into 6 periods of T/2 defining positions P1 to P6 at which transitions can occur. The input data signal is divided into three-bit words, and each word is encoded by means of a circuit, which will be described later with reference to Figure 6, into a six-bit word represented by a transition corresponding to each binary 1, each transition being recorded at one of the positions P1 to P6. Such a recording is shown in Figure 5.

Referring now to this Figure, it represents a waveform generated from the original input data by the circuit of Figure 6, and it can be understood by reference to the encoding table of Figure 7. The input data shown along the top of Figure 5 are divided into groups of three digits. The first group, 001, is encoded as shown in line 2 of Figure 7 into the form 000100, and the recorded transition equivalent to this is shown at data cell Z1 of Figure 5. The next group, 111, is encoded as 100100, and occupies cell Z2 of Figure 5. The third group, 010, is encoded as 010000, and occupies the cell Z3.

So far it will be observed that the conditions mentioned above have been met. No two transitions represented by l's in the output code are separated by more than eleven, or less than two, zeros. However, a new problem arises with the last two groups. 110 should be encoded in accordance with line 7 of Figure 7 as 100010, and 101 ought to be encoded in accordance with line 6 as 100000. This would lead to a transition at P5 of Z4, and a transition at P1 of Z5 separated by only one zero, that at P6, the boundary between Z4 and Z5, and so would break the rule that there must be at least two zeros between successive l's. In order to avoid this, the circuit of Figure 6 replaces the transitions at P5 of Z4 and P1 of Z5 by a single transition at P6 at the boundary between Z4 and Z5. This can be followed from the amplified table in Figure 8 at line 12, in which it can be seen that when the binary word 110 is encoded in circumstances in which the preceding word ends with a 0 and the following word begins with a 1, it takes the form 100001. Similarly, when 101 is to be encoded in circumstances in which the preceding word has ended with a 1, it takes the form 000000.

The encoded waveform is thus as shown in Figure 5.

Figure 6 shows in a schematic form the encoding circuit for carrying out the encoding process described above. The binary data to be encoded and recorded are applied to the input terminal 14 of a shift register 15. A bit clock signal (shown in Figure gila) is applied to the terminal 16 to shift the data one register stage for each pulse. The capacity of the shift register 15 is sufficient for three binary three-bit words, which at any time will comprise the word to be encoded and written, and the preceding and following words. Three binary-tooctal encoders 17, 24 and 29 are provided for encoding these words into their octal equivalents and converting them to a single signal on one of the lines BO to B7 for the present word, and A0 to A7, CO to C7 for the preceding and following words respectively. The outputs from these lines are ap plied via various gating circuits to a write signal shift register 20 in which the signal to be written is assembled, and this process will be described more fully below.

From the description of Figure 5 it wili be recalled that the digits at the ends of the six-bit output words in some circumstances required modification to avoid the occurrence of two successive l's with Iess than the minimum spacing of two 0's between them. This modification is carried out by the two sets of gates 25 and 30, receiving inputs from certain of the outputs from the encoder 17 and the preceding word encoder 24, and from the encoder 17 and the following word encoder 29, respectively. The working of these logic circuits is blest followed from the table of Figure 8.

The operation of the circuit will now be examined, taking by way of example the encoding and recording of the stream of data shown in Figure 5. The data are supplied to the terminal 14 of the shift register 15, in which they are stepped forward successively by bit clock pulses 18b, 18a, and 18c to 18e, shown in Figure lla, applied to the bit clock terminal 16. At a time represented by the beginning of data cell Z1 of Figure 5, and immediately following the leading edge of bit clock pulse 18a the first three-bit word 001 will be applied to the binary-to-octal encoder 17, which will produce an output at the terminal B1, and the following word 111 will be applied to the binary-to-octal encoder 29 where it will produce an output at the terminal C7. The three-bit word which is applied to the binary-to-octal encoder 24 and which precedes the word to be encoded, is 000 in the absence of a three-bit word proper and results in an output at the terminal A0 of the encoder 24.

The signal at B1 is applied through the OR gate 23 to the terminal S4 of the write signal shift register 20. The signal at the terminal A0 provides an output from the OR gate 26, but this is inverted by the inverter 27, which therefore does not apply an input to the AND gate 28. The signal at C7 is passed by the OR gate 31 to the AND gate 33; however, there is no signal at the other input of this AND gate, so it does not produce any output to terminal S6. The shift register 20 therefore receives an input at its terminal S4, but not on any of the other terminals. This is in accord ance with line 3 of the table in Figure 8.

Figure lla shows the timing pulses applied to the various shift registers. For each of the data cells of Figure 5 occupying a period of 3T, there are three bit clock pulses, 18c to 18e, for stepping the data through the shift register 15. There are six position clock pulses, 35a to 35f, for stepping the digits of the six-digit code through the signal shift register 20; and a word clock pulse 21a, and a transition in a "record" signal, for enabling the signal shift register so that it can receive the digits of the encoded word through the gating circuits. The position described above holds at the trailing edge of bit clock pulse 18a. At this time the word clock pulse 21a is still present at the word clock terminal 22 of the shift register 20. When the trailing edge of this pulse 21a has been reached, the information at the terminals S1 to S6 has been, and further information is prevented from being, gated into the write signal shift register 20. During the next data cell interval the position clock terminal 36 of the shift register 20 receives six pulses 35a to 35f, which successively step the signals S1 to S6 along the shift register and present them in turn to a flip-flop 37, the output from which may be applied to a magnetic recording system. During the same time interval three bit clock pulses 18c, 18d arid 18e will have been applied at the terminal 16 of the write data shift register 15, and will have stepped the contents of this register forward, so that the next group of three digits to be encoded is presented to the encoder 17, the preceding group previously recorded is presented to the encoder 24 and the following group to the encoder 29.

Referring now again to Figure 5, it will be seen that the encoder 17 receives the digits 111 and produces an output at terminal B7. The encoder 24 receives the digits 001 and will produce an output at Al, and the encoder 29 will receive the digits 010 and will produce an output at C2. The shifts of the shift registers will have been completed at the leading edge of bit clock pulse 18e, and when the word clock pulse 21b is present at the terminal 22, the shift register 20 will be receptive to the signals presented to its terminals S1 to S6.

Considering now these signals, the sig nal at B7 passes the OR gate 23 to produce a signal at S4. It also passes the OR gate 38 to provide one input to the AND gate 28.

There is no signal from the encoder 24 to the OR gate 26, so that the inverter 27 pro vides a second input to the AND gate 28 and a signal appears at terminal Sl. There is no signal from the encoder 29 to the OR gate 31. The inverter 32 provides an input to the AND gate 34, but there is no second input to this gate. At the time of the trail ing edge pulse 21b the shift register 20 has thus received a signal on its terminals S1 and S4, and on no others. This corresponds to line 14 of table 8, and during the next cycle the contents of the shift register 20 will be recorded, as described above, as transitions at points P1 and P4 of the data cell Z2 of Figure 5.

In the next cycle outputs will occur at the terminals B2 of the encoder 17 and A7 and C6 of the encoders 24 and 29 repectively. The signal at B2 will be passed by the OR gate 39 to provide a signal at S2 and this will appear in the recording as a transition at P2 of data cell Z3 of Figure 5.

In the following cycle there will be signals at encoder outputs A2, B6 and C5. The signal at B6 is passed by the OR gates 38 and 40, and is applied to one input of each of the AND gates 28, 33 and 34. There is input from the encoder 24 to the OR gate 26, so that the inverter 27 provides a second input to the AND gate 28 and there is a signal at S1. The signal at C5 is passed by the OR gate 31 and is applied to the inverter 32. There is no output from this inverter to the AND gate 34. However, the output from the OR gate 31 is also applied to the AND gate 33 which produces an output to the terminal S6. The shift register therefore has a signal at S1 and S6, and during the next cycle the six position clock pulses cause this pattern to be read from the shift register into the flip-flop and so to drive the recording circuits.

Coming now to the final data cell Z5 of Figure 5 the three bit word to be encoded is 101, and the outputs from the encoders 24 and 17 will be at terminals A6 and B5.

The output from the encoder 29 will depend on the next three-bit word to be encoded, which is at present unknown, but in fact, as will be seen, in this instance it does not affect the coding.

The output from the terminal B5 is applied through the OR gate 38 to one input of the AND gate 28. The output from terminal A6 is applied through the OR gate 26 to the inverter 27, so that there is no second input to the AND gate 28, and no signal is applied to S1. Since BO, B3 and B6 are none of them energised there will be no input to the OR gate 40, and therefore, whether or not there is an input from the encoder 29 to the OR gate 31, neither of the AND gates 33 and 34 will have more than one input energised. None of the terminals Sl to S6 therefore has a signal ap plied to it, and the coding transmitted to the flip-flop 37 during the ensuring cycle will be 000000, no transition occurring in the data cell Z5 of Figure 5.

It will thus be seen that the logic of Figure 6 produces a coding patternffn accordance with the table of Figure 8, which ensures that any two successive ls cannot be separated by fewer than two zeros. It also ensures that two ls cannot be separated by more than eleven zeros, and this may be seen at once from lines 9 and 8 of the table of Figure 8. A sequence of twelve or more zeros could only occur if line 9 were to be recorded twice in succession. This cannot occur, because the recording of 101 in the form indicated in line 9 of the table can only occur if there is an input from one of the gates AO, A3 or A6 indicating that a 1 has been recorded in the P6 position of the immediately preceding group.

Having encoded the information as described above for recording it will be necessary to decode it to recover the original information during the reading process.

This will now be described with reference to Figures 9 and 10, and the waveforms shown in Figure 1 Ib.

Referring first to Figure 9, and to Figure 10 which illustrates the operation of the circuit of Figure 9, the encoded signal pulse stream is applied to the input terminal 41 of a read signal shift register 42. Clocking pulses are also applied to this shift register at the terminal 43. The register has seven stages, and the contents of these stages can be transferred through gating circuits, as will be described below, to a three-stage read data shift register 46. In this shift register the decoded three-bit word represented by the six-bit encoded signal in the read signal shift register 42 is assembled so that it can be read out. The shift register 46 has a bit clock terminal 49' to which are applied pulses for stepping the data through the register, and a word clock terminal 48 to which word clock pulses may be applied, and a read terminal to which a low level read signal may be applied, for enabling the register so that it can receive input signals at its data terminals DO, D1 and D2.

Figure 1 lb shows the timing pulses applied to the various shift registers. For each of the data cells of Figure 5 occupying a period of 3T, there are six position clock pulses, 44b to 44g, for stepping the read signal through the shift register 42. There are three bit-clock pulses, 49a, 49b and 49c, for stepping the three digits of the threedigit word through the read data shift register 46, and a word clock pulse 47a for enabling the read data shift register so that it can receive the digits of the three-digit word through the gating circuits of Figure 9.

The decoding of the encoded waveform of Figure 5 by the circuit of Figure 9 will now be described to illustrate the operation of that circuit. It will be assumed that we are at a time just following the leading edge of the bit clock pulse 49a of Figure llb, and the contents of the first data cell Z1 of Figure 5 have been read into positions S1 to S6 of the read shift register 42. Since the cell contains a transition at P4 and no other transitions, there will be a signal at 54 and Sl, S2, S3, S5 and S6 will contain zeros. The position S6' will normally contain whatever digit was at P6 of the preceding data cell, and initially this will be zero.

The signal at S4 will be passed by the OR gate 51 and will provide a signal at DO in the read data shift register 46. None of the other OR gates in the system will receive an input, and although the output from the inverter 60 provides one input to the AND gate 55, there is no other input to this gate.

There are thus no signals reaching D1 or D2 in the shift register 46. The register therefore contains 001, which is the correct decoding of the contents of the data cell Zl of Figure 5.

Returning to Figure llb, after the trailing edge of the pulse 47a is reached and during the next 3T cycle six pulses 44b etc. are applied to the shift register 42, stepping the contents of this register through the register and reading in the information in data cell Z2 of Figure 5. This new data occupies positions S1 to S6, and, since there are seven stages in the shift register, the former contents of S6, being the signal representing a transition or absence of a transition at position P6 of Z1, remain in the register at position S6'. While this is happening three pulses have been applied to the bit clock terminal 49' of the read data shift register thereby reading out the three digits 001 on the line 50. At the end of this cycle the word clock pulse 47b enables the read data shift register 46 to receive the next set of digits.

Data cell Z2 contains transitions at P1 and P4, so that there will be signals at S1 and S4 in the shift register 42. The signal at S4 is passed by the OR gate 51 to produce a digit signal at DO in the read data shift register 46. The signal at S1 is passed by the OR gate 52 and the OR gate 56 to produce a signal at D2. Furthermore, the output from the inverter 60 provides an input for the AND gate 55, and the output of the OR gate 52 provides a second input for this gate, so that the gate provides an output, through the OR gate 51, to produce a signal at DO. The register 46 thus contains the binary word 111, corresponding to the contents of data cell Z2. This information is read out while the contents of Z3 are read into the shift register 42, in exactly the same way as described above for the previous cycle.

Z3 contains a transition at P2, so there will be a signal at S2 of the shift register 42. This is passed by the OR gate 54 to provide a signal at <RTI rence of the pulses of the encoded signal pulse stream are not identical with the signal transitions of the recorded encoded signal because of bit shift and other distortions inherent in the recording and recovery process. For this reason the encoded signal pulse stream is applied not -only to decoding circuit 62 but also to read clock generator 72. The read clock generator may include a phase-locked oscillator synchronised by the encoded signal pulse stream at a harmonic of the frequency corresponding to the period of minimum spacing between signal transitions, or more preceisely, at a frequency equal to 2/T, which is equivalent to the position clock rate. Under the control of the timing unit 63 driven by the read clock generator, the decoding circuit 62 regenerates the original binary data at its output.

While the presently preferred embodiment of the invention has been described with reference to an encoding scheme in which each binary data word consists of three bits and is represented by signal transitions at one or two selected positions of a total of six position in a data cell, it should be recognised that other logic configurations may be used within the ambit of the invention. For instance, each binary data word may be represented by a transition in one or both of two adjacent data cells each having a length equal to 1.5T and wherein each cell corresponds to one and a half binary data bits. An encoding scheme of this type is shown in Figure 13. It will be noted that in this case the data cell boundaries coincide with the P3 signal transition positions.

In order to maintain the desired minimum spacing of 3T/2 between signal transitions, the one bits at positions P2 and P1 of cell one and cell two respectively, corresponding to binary data word 100, will have to be merged into a transition at position P3 of cell one, that is at the boundary between cells one and two. Likewise, merging will be required in the case of binary data words 000, 011 and 110, for which a transition occurs at position P2 of cell two, when followed by any of the words 101, 110 or 111 for which a transition occurs at position P1 of cell one.

In addition to changing the data cell arrangement relative to a data word as explained in the preceding paragraph, it should be understood that other encoding circuit configurations may be used. For example a write data shift register responding to a bit clock signal and having a capacity of only one data word may be used in combination with encoding and logic circuit means which is actuated by a word clock signal to receive the data word from the data shift register and generate the code signals which in turn are applied to a modulator comprising a modified shift register controlled by a multiphase clock signal for performing the merging feature of the invention, together with the storing and shifting of the write data shift register.

WHAT WE CLAIM IS: 1. A method of encoding an input stream of binary electric signals into an output signal stream, in which the input signal stream is divided into words of uniform length, and each word is encoded into another word to produce a new series of words of uniform length and each having a greater number of digits, each encoded word being modified as necessary with reference to the preceding and following encoded words by merging l's within and/or between the encoded words so that in the output signal stream comprising the encoded words successive l's are separated by a minimum spacing greater than the least spacing of the input signal stream, and by a finite maximum spacing.

2. A method according to claim 1 in which the encoded words are modified as necessary by merging l's between encoded words and by merging those l's to an otherwise empty intermediate digit position which is either the last digit position of the preceding word or the first digit position of the following word.

3. A method according to any preceding claim in which the encoded words have twice as many digits as the words of the input signal stream.

4. A method according to claim 3 in which the input signal stream is divided into words of three digits each, and the encoded words have six digits each.

5. A method of encoding an input stream of binary electric signals substantially as herein described with reference to Figures 1, 3, 4, 5, 6, 7 and 8 of the accompanying drawings.

6. Apparatus adapted to carry out the method of any preceding claim, comprising an information shift register arranged to receive the input signal stream in series, means to divide the contents of the information shift register into three consecutive words of uniform length, encoding circuits to supply the encoded digits of the second of the three words together with appropriate digits of the preceding and following encoded words derived from the first and the third word respectively, to merging and gating circuits which supply the encoded second word, modified as necessary, in parallel to a signal shift register, and means reading out in series each encoded word from the signal shift register thereby to provide the output signal stream.

7. Apparatus according to claim 6 in which the signal shift register has a capacity of six digits and the information shift re

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (14)

**WARNING** start of CLMS field may overlap end of DESC **. rence of the pulses of the encoded signal pulse stream are not identical with the signal transitions of the recorded encoded signal because of bit shift and other distortions inherent in the recording and recovery process. For this reason the encoded signal pulse stream is applied not -only to decoding circuit 62 but also to read clock generator 72. The read clock generator may include a phase-locked oscillator synchronised by the encoded signal pulse stream at a harmonic of the frequency corresponding to the period of minimum spacing between signal transitions, or more preceisely, at a frequency equal to 2/T, which is equivalent to the position clock rate. Under the control of the timing unit 63 driven by the read clock generator, the decoding circuit 62 regenerates the original binary data at its output. While the presently preferred embodiment of the invention has been described with reference to an encoding scheme in which each binary data word consists of three bits and is represented by signal transitions at one or two selected positions of a total of six position in a data cell, it should be recognised that other logic configurations may be used within the ambit of the invention. For instance, each binary data word may be represented by a transition in one or both of two adjacent data cells each having a length equal to 1.5T and wherein each cell corresponds to one and a half binary data bits. An encoding scheme of this type is shown in Figure 13. It will be noted that in this case the data cell boundaries coincide with the P3 signal transition positions. In order to maintain the desired minimum spacing of 3T/2 between signal transitions, the one bits at positions P2 and P1 of cell one and cell two respectively, corresponding to binary data word 100, will have to be merged into a transition at position P3 of cell one, that is at the boundary between cells one and two. Likewise, merging will be required in the case of binary data words 000, 011 and 110, for which a transition occurs at position P2 of cell two, when followed by any of the words 101, 110 or 111 for which a transition occurs at position P1 of cell one. In addition to changing the data cell arrangement relative to a data word as explained in the preceding paragraph, it should be understood that other encoding circuit configurations may be used. For example a write data shift register responding to a bit clock signal and having a capacity of only one data word may be used in combination with encoding and logic circuit means which is actuated by a word clock signal to receive the data word from the data shift register and generate the code signals which in turn are applied to a modulator comprising a modified shift register controlled by a multiphase clock signal for performing the merging feature of the invention, together with the storing and shifting of the write data shift register. WHAT WE CLAIM IS:

1. A method of encoding an input stream of binary electric signals into an output signal stream, in which the input signal stream is divided into words of uniform length, and each word is encoded into another word to produce a new series of words of uniform length and each having a greater number of digits, each encoded word being modified as necessary with reference to the preceding and following encoded words by merging l's within and/or between the encoded words so that in the output signal stream comprising the encoded words successive l's are separated by a minimum spacing greater than the least spacing of the input signal stream, and by a finite maximum spacing.

2. A method according to claim 1 in which the encoded words are modified as necessary by merging l's between encoded words and by merging those l's to an otherwise empty intermediate digit position which is either the last digit position of the preceding word or the first digit position of the following word.

3. A method according to any preceding claim in which the encoded words have twice as many digits as the words of the input signal stream.

4. A method according to claim 3 in which the input signal stream is divided into words of three digits each, and the encoded words have six digits each.

5. A method of encoding an input stream of binary electric signals substantially as herein described with reference to Figures 1, 3, 4, 5, 6, 7 and 8 of the accompanying drawings.

6. Apparatus adapted to carry out the method of any preceding claim, comprising an information shift register arranged to receive the input signal stream in series, means to divide the contents of the information shift register into three consecutive words of uniform length, encoding circuits to supply the encoded digits of the second of the three words together with appropriate digits of the preceding and following encoded words derived from the first and the third word respectively, to merging and gating circuits which supply the encoded second word, modified as necessary, in parallel to a signal shift register, and means reading out in series each encoded word from the signal shift register thereby to provide the output signal stream.

7. Apparatus according to claim 6 in which the signal shift register has a capacity of six digits and the information shift re

gister has a capacity of nine digits, threebinary to octal encoders being arranged to operate in parallel on three digits each of the information shift register to divide its contents and to encode the three words, the outputs from the encoders being applied to gating means which supply the encoded second word to the signal shift register.

8. Apparatus for encoding an input stream of electric signals representing binary digital information, substantially as herein described with particular reference to Figure 6 of the accompanying drawings.

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9. Apparatus adapted to decode words of a binary digital signal stream encoded by a method according to any one of claims 1 to 5, -comprising a signal shift register arranged to receive the encoded words sequentially and to contain at each decoding cycle an encoded word and one or more end digits of the preceding encoded word, gating circuits operating on the contents of the signal shift register in parallel to decode the encoded word, including recovery of merged l's, and to supply the decoded word in parallel to an information shift register, and means for reading out in series the: decoded words from the information shift register.

10. Apparatus adapted to decode words of an encoded binary digitaI~signal stream substantially as herein described with particular reference to Figure 9 of the accompanying drawings.

11. A data recording and recovery system comprising encoding apparatus according to any one of claims 6, 7 or 8, arranged to provide an encoded signal stream to magnetic recording and reading apparatus, and a decoder arranged to receive an encoded signal stream from the magnetic recording and reading apparatus.

12. A data recording and recovery system according to claim 11 in which the input signal stream is divided into words of three digits, the encoded words are of six digits each and the signal shift register of the decoder comprises seven stages so that its logic circuits operate on the seven digits comprising the six digits of the recorded encoded word together with the final digit of the previous recorded word.

13. A data recording and recovery system according to claim 11 or claim 12, in which the decoder is in accordance with claim 9 or claim 10.

14. A data recording and recovery system substantially as herein described with particular reference to Figure 12 of the accompanying drawings.