GB1521029A - Synchronous digital systems - Google Patents

Synchronous digital systems

Info

Publication number
GB1521029A
GB1521029A GB4113174A GB4113174A GB1521029A GB 1521029 A GB1521029 A GB 1521029A GB 4113174 A GB4113174 A GB 4113174A GB 4113174 A GB4113174 A GB 4113174A GB 1521029 A GB1521029 A GB 1521029A
Authority
GB
United Kingdom
Prior art keywords
terminal
signal
clock
counter
zero
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4113174A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Post Office
Original Assignee
Post Office
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Post Office filed Critical Post Office
Priority to GB4113174A priority Critical patent/GB1521029A/en
Publication of GB1521029A publication Critical patent/GB1521029A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Abstract

1521029 Data transmission POST OFFICE 19 Sept 1975 [20 Sept 1974] 41131/74 Heading H4P A clock system for syncronous digital signalling apparatus, e.g. a data modem, comprises an oscillator 1 connected to a clock pulse output terminal 6; an input terminal 7 for the baseband signal with which the clock is to be synchronized; means to sample a signal applied to the terminal 7, including a zero-crossing detector 9 and a counter 16 arranged to respond to a predetermined number of zero-crossings detected by the detector; a tuned circuit 10 associated with zero-crossing detectors 8, 13 and arranged to oscillate in phase with the average phase of the sampled signal; and logic circuitry 14 associated with the counter 16, the tuned circuit 10 and a start/stop gate A, the arrangement being such that clock pulses are prevented from appearing at the terminal 6 during the sampling period, but appear at the terminal in phase with the oscillations in the tuned circuit 10 at the end of the sampled signal. The system may be used to achieve initial synchronization after transmission-reception change-over in simplex or half duplex operation, employing a 15 bit pseudo random binary sequence for the signal to be sampled. The long term synchronization is effected by comparing the timing of the clock pulses with the timing of the synchronous digital signal by means of an early/late gate 17, the result of the comparison being used to control, by way of a counter 18, a circuit 3 which adds or suppresses pulses from the oscillator I, thereby ensuring the provision of synchronized clock pulses at the terminal 6.
GB4113174A 1975-09-19 1975-09-19 Synchronous digital systems Expired GB1521029A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB4113174A GB1521029A (en) 1975-09-19 1975-09-19 Synchronous digital systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4113174A GB1521029A (en) 1975-09-19 1975-09-19 Synchronous digital systems

Publications (1)

Publication Number Publication Date
GB1521029A true GB1521029A (en) 1978-08-09

Family

ID=10418249

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4113174A Expired GB1521029A (en) 1975-09-19 1975-09-19 Synchronous digital systems

Country Status (1)

Country Link
GB (1) GB1521029A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012884A1 (en) * 1978-12-20 1980-07-09 International Business Machines Corporation Process and apparatus for detecting a pseudo-random sequence of two symbols in a data receiver using a double sideband modulation with quadrature carriers
FR2445079A1 (en) * 1978-12-20 1980-07-18 Ibm France METHOD AND DEVICE FOR DETECTING A PSEUDO-RANDOM SEQUENCE OF PHASE CHANGES OF 0O AND 180O OF THE CARRIER IN A DATA RECEIVER
EP0160464A2 (en) * 1984-04-25 1985-11-06 Nec Corporation Method of and apparatus for determining time origin of timer for modem
FR2619479A1 (en) * 1987-08-14 1989-02-17 Thomson Csf METHOD FOR RAPID SYNCHRONIZATION OF VOCODERS COUPLED BETWEEN THEM USING ENCRYPTION AND DE-RECTIFYING DEVICES

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012884A1 (en) * 1978-12-20 1980-07-09 International Business Machines Corporation Process and apparatus for detecting a pseudo-random sequence of two symbols in a data receiver using a double sideband modulation with quadrature carriers
FR2445079A1 (en) * 1978-12-20 1980-07-18 Ibm France METHOD AND DEVICE FOR DETECTING A PSEUDO-RANDOM SEQUENCE OF PHASE CHANGES OF 0O AND 180O OF THE CARRIER IN A DATA RECEIVER
EP0013343A1 (en) * 1978-12-20 1980-07-23 International Business Machines Corporation Process and device to detect a pseudo-random sequence of 0 degree and 180 degree phase changes of the carrier in a data receiver
EP0160464A2 (en) * 1984-04-25 1985-11-06 Nec Corporation Method of and apparatus for determining time origin of timer for modem
EP0160464A3 (en) * 1984-04-25 1987-09-23 Nec Corporation Method of and apparatus for determining time origin of timer for modem
FR2619479A1 (en) * 1987-08-14 1989-02-17 Thomson Csf METHOD FOR RAPID SYNCHRONIZATION OF VOCODERS COUPLED BETWEEN THEM USING ENCRYPTION AND DE-RECTIFYING DEVICES
EP0305261A1 (en) * 1987-08-14 1989-03-01 Thomson-Csf Method for quickly synchronizing vocoders coupled by enciphering and deciphering apparatuses
US4964165A (en) * 1987-08-14 1990-10-16 Thomson-Csf Method for the fast synchronization of vocoders coupled to one another by enciphering

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee