GB1491047A - Self-checking data processing system - Google Patents

Abstract

1491047 Verifying apparatus HONEYWELL INFORMATION SYSTEMS Inc 9 Dec 1974 [10 Dec 1973 (3)] 53048/74 Heading G4A A self verifying data processing system comprises two sub-systems (preferably the control apparatus of the central processing unit and the input/output controller), each including circuitry for controlling the operation of the subsystems and exercising both sub-systems and fault detection circuitry for detecting faults during exercising. As described each sub-system is provided with a control store memory storing a set of instructions (loaded from, e.g. a cassette), a subcommand generator translating instructions into control signals and an integrity check collection apparatus identifying an error condition and transferring information to a diagnostic message register. A diagnostic direct register can also be used to examine results of signal processing. Manual data may be introduced via a maintenance panel interface. A data bus links the two sub-systems to permit transfer of data. Three modes of operation are possible (1) normal operation by the sub-system's own control centre; (2) one control centre in master state controlling the other sub-system in slave state and (3) instructions extracted from the control store of one sub-system in master state for application to both sub-systems. Testing takes place in three stages. Stage 1 (Figs. 9-10, not shown).-Segments are successfully loaded in the IOC control store, any error in loading resulting in a retry, after 10 unsuccessful retries a halt being called. Otherwise a control store scan is effected followed by internal verification of the IOC basic master logic, an error in either resulting in a master error termination. When all the segments have been loaded and no errors detected a normal termination is effected. A similar process is then effected on the CPU. Stage 2 (Figs. 11-14, not shown).-Segments are again loaded into the IOC control store and providing no load or scan errors occur the IOC diagnoses the CPU master and extended master apparatus (which includes the control store array, control store addressing logic, main adder and verification apparatus), the control store of the CPU being successively loaded with segments, a halt being called if loading after retries is still unsuccessful and a IOC slave-error terminate occurring if a CPU error is found. The CPU then tests the IOC master in a similar manner. The CPU non-master apparatus (logic circuitry) is then tested by the IOC master apparatus followed by testing of the IOC non- master apparatus by the CPU master. Stage 3 (Figs. 15-17, not shown).-The CPU control store is again loaded and provided no loading or scan errors are detected the main memory diagnosis is effected. This is followed by testing of the buffer store. Finally the CPU/ IOC interactive apparatus is tested, the CPU and IOC acting under the control of the CPU.