GB1430257A - Programme-controlled data processing systems - Google Patents

Programme-controlled data processing systems

Info

Publication number
GB1430257A
GB1430257A GB3613473A GB3613473A GB1430257A GB 1430257 A GB1430257 A GB 1430257A GB 3613473 A GB3613473 A GB 3613473A GB 3613473 A GB3613473 A GB 3613473A GB 1430257 A GB1430257 A GB 1430257A
Authority
GB
United Kingdom
Prior art keywords
stores
store
redundant
processors
subsidiary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3613473A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1430257A publication Critical patent/GB1430257A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/06—Management of faults, events, alarms or notifications

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

1430257 Data processing system SIEMENS AG 30 July 1973 [18 Sept 1972] 36134/73 Heading G4A A data processing system comprising a number of processing units VE1-VEn and at least two, normally redundant, stores S1, S2 each connected in parallel to all processing units each of which has a comparator means V1-V3 for detecting incorrect redundant operation, is arranged selectively to operate the stores non- redundantly without loss of synchronism. To this end each processor requiring storage access sends a request signal to all the stores together with data specifying whether, and if so which, stores are not to execute the requested operation. The specified store(s) perform an idle cycle in order to maintain synchronism. Non- redundant operations are used, e.g. with less important data which is stored only in one store, more important data being stored redundantly in more than one store. In the event that two processors make simultaneous requests for non-redundant operations in different ones of two stores, both processors may be given access to their respective stores and idle cycles are avoided. It is stated that each store may be formed from a number of subsidiary stores M, N, &c. In the event that two processors make simultaneous requests for non-redundant operations in respect of different subsidiary stores in different ones of two such stores, it is necessary for the subsidiary stores in each store corresponding to that subsidiary store in the other store in which a non-redundant operation is being performed, to perform an idle cycle. For redundant operation the comparators V1-V3 compare both control and data signals exchanged between the stores and the processors. For non-redundant operation only the control signals are compared. It is stated that the stores may incorporate parity checking circuits to be used as an additional and the sole error check in the case of redundant and non- redundant operations, respectively. Simultaneous requests by two or more processors for the same store are resolved in accordance with the priorities of the processors.
GB3613473A 1972-09-18 1973-07-30 Programme-controlled data processing systems Expired GB1430257A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2245737A DE2245737A1 (en) 1972-09-18 1972-09-18 PROCEDURE FOR OPERATING A PROGRAM-CONTROLLED DATA PROCESSING SYSTEM

Publications (1)

Publication Number Publication Date
GB1430257A true GB1430257A (en) 1976-03-31

Family

ID=5856652

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3613473A Expired GB1430257A (en) 1972-09-18 1973-07-30 Programme-controlled data processing systems

Country Status (10)

Country Link
BE (1) BE804981A (en)
BR (1) BR7307195D0 (en)
CA (1) CA989075A (en)
CH (1) CH566055A5 (en)
DE (1) DE2245737A1 (en)
FR (1) FR2199898A5 (en)
GB (1) GB1430257A (en)
IT (1) IT993193B (en)
NL (1) NL7312720A (en)
ZA (1) ZA735361B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2220091A (en) * 1988-06-27 1989-12-28 Applic Specific Computers Limi A memory error protection system
GB2408355A (en) * 2003-11-18 2005-05-25 Ibm Verification of data consistency between two disparate systems

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3654121B1 (en) * 2018-11-14 2021-06-09 Siemens Aktiengesellschaft Redundant automation system with a plurality of processing units for each hardware unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2220091A (en) * 1988-06-27 1989-12-28 Applic Specific Computers Limi A memory error protection system
GB2220091B (en) * 1988-06-27 1991-05-22 Applic Specific Computers Limi A memory error protection system
GB2408355A (en) * 2003-11-18 2005-05-25 Ibm Verification of data consistency between two disparate systems
GB2408355B (en) * 2003-11-18 2007-02-14 Ibm A system for verifying a state of an environment

Also Published As

Publication number Publication date
NL7312720A (en) 1974-03-20
CA989075A (en) 1976-05-11
IT993193B (en) 1975-09-30
CH566055A5 (en) 1975-08-29
ZA735361B (en) 1974-07-31
BE804981A (en) 1974-03-18
FR2199898A5 (en) 1974-04-12
DE2245737A1 (en) 1974-04-04
AU5903573A (en) 1975-02-13
BR7307195D0 (en) 1974-07-11

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees