GB1310664A - Data handling systems - Google Patents

Data handling systems

Info

Publication number
GB1310664A
GB1310664A GB1310664DA GB1310664A GB 1310664 A GB1310664 A GB 1310664A GB 1310664D A GB1310664D A GB 1310664DA GB 1310664 A GB1310664 A GB 1310664A
Authority
GB
United Kingdom
Prior art keywords
fus
bus
erroneous
error
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1310664A publication Critical patent/GB1310664A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G06F11/167—Error detection by comparing the memory output
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2736—Tester hardware, i.e. output processing circuits using a dedicated service processor for test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Abstract

1310664 Data processing INTERNATIONAL BUSINESS MACHINES CORP 28 Jan 1971 3346/71 Heading G4A [Also in Division H4] A digital electric data handling system comprises a plurality of functional units (FUs) joined by a common bus BS, there being error detecting means E and unit isolating means A, I, G associated with each FU so that, if an FU is erroneous, all the non-erroneous FUs are disconnected from the bus so that the erroneous FU can be diagnosed. Each error detecting means E is connected to an error indicator L which, when set, enables AND gates A, the other respective inputs of which are connected through invertors I to means E. When an AND gate is activated a gate G disconnects the FU from the bus. A diagnostic unit DU is enabled by indicator L and operates on the erroneous FU or FUs connected to the bus BS. A bus CS enables all or some of the units to be disconnected or connected for other reasons by triggering indicator L and the invertors I. In another embodiment (Fig. 2, not shown) the FUs are memory units as described in British Specification 1,127,270, each FU comprising two identical halves which operate on the same data and issue an error signal when a comparator indicates disagreement. Gating circuitry then isolates units by stopping their clocks (Fig. 3, not shown). If more than one FU at a time has an error only one FU will be connected for diagnosis at a time due to a priority system. As with the system of Fig. 1 FUs can be connected or disconnected for other purposes. A failed FU can be replaced by a spare FU. In another embodiment (Figs. 4 and 5, not shown) a number of systems as in Fig. 2 can be combined using an interface and can have a common diagnostic unit, console &c. and an inter system priority arrangement. A telephone line and a printer are also mentioned.
GB1310664D 1971-01-28 1971-01-28 Data handling systems Expired GB1310664A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB334671 1971-01-28

Publications (1)

Publication Number Publication Date
GB1310664A true GB1310664A (en) 1973-03-21

Family

ID=9756587

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1310664D Expired GB1310664A (en) 1971-01-28 1971-01-28 Data handling systems

Country Status (6)

Country Link
JP (1) JPS5137131B1 (en)
CA (1) CA969664A (en)
DE (1) DE2164686C3 (en)
FR (1) FR2124700A5 (en)
GB (1) GB1310664A (en)
IT (1) IT944340B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514845A (en) * 1982-08-23 1985-04-30 At&T Bell Laboratories Method and apparatus for bus fault location
US4589090A (en) * 1982-09-21 1986-05-13 Xerox Corporation Remote processor crash recovery

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU575297B2 (en) * 1982-09-21 1988-07-28 Xerox Corporation Separate resetting of processors
DE3631086C2 (en) * 1986-09-12 1994-04-14 Telefonbau & Normalzeit Gmbh Circuit arrangement for error processing in microprocessor systems
FR2657182A1 (en) * 1990-01-15 1991-07-19 Cit Alcatel Device for aiding diagnosis

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514845A (en) * 1982-08-23 1985-04-30 At&T Bell Laboratories Method and apparatus for bus fault location
US4589090A (en) * 1982-09-21 1986-05-13 Xerox Corporation Remote processor crash recovery

Also Published As

Publication number Publication date
DE2164686B2 (en) 1979-03-15
DE2164686A1 (en) 1972-08-17
CA969664A (en) 1975-06-17
FR2124700A5 (en) 1972-09-22
DE2164686C3 (en) 1979-11-08
IT944340B (en) 1973-04-20
JPS5137131B1 (en) 1976-10-14

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee