GB1382312A - Retiming conditionally encoded diphase signals - Google Patents

Abstract

1382312 Digital transmission; synchronizing INTERNATIONAL STANDARD ELECTRIC CORP 11 May 1972 [21 May 1971] 22127/72 Headings H4P and H3A A synchronizing arrangement has means at the output of a shift register receiving data for extracting timing signals which are compared with a reference clock, the difference controlling register shifting circuitry to bring the received data into a determined phase relation. Incoming diphase signals enter a multistage shift register I where they are shifted by pulses from a controlled oscillator 2 of higher frequency than that of the initial diphase clock frequency. Timing data is extracted by a series arrangement of a sawtooth generator 3 and phase lock oscillator 4. Extracted timing signals are compared at 5 output from which is low pass filtered at 6 and which controls the frequency of oscillator 2. The delay introduced by shift register 1 is sufficient to bring incoming signals into synchronism with the reference clock. The arrangement described so far will follow slowly changing phase jitter hence to remove rapid jitter signals are passed through gated register 7, also controlled by the reference clock, which strobes signals about the centre of each pulse, i.e. remote from leading and trailing edges.