GB1332515A - Multiplex decoding system - Google Patents

Abstract

1332515 Stereophonic radio receivers; transistor amplifiers RCA CORPORATION 18 Dec 1970 [29 Dec 1969] 60162/70 Heading H3T and H4L A stereophonic radio receiver uses a phaselocked loop to control the subcarrier regenerator and is designed to make use of integrated circuits. As shown in Fig. 1 the received signal is supplied to a tuner-detector 20 and the resulting composite stereo signal is amplified at 24 and supplied to balanced synchronous detectors 36, 40, 60, 68. A voltage controlled oscillator 26 produces a squarewave output at 228 KHz which is an even harmonic of the 19 Kc./s. pilot signal and the 38 Kc./s. subcarrier, its resonant circuit 80, 82 being located outside the integrated circuit slip indicated by dotted line 22. The output of oscillator 26 is divided by two at 28 (114 KHz.), by three at 30 (38 KHz.), and after selection of a predetermined phase at 32 is divided by two at 34. The resulting 19 KHz. signal is compared at 36 with the received pilot signal to provide automatic frequency and phase control for the oscillator 26. The 38 KHz. output of divider 30 is supplied to the synchronous detector 40 which via matrix circuits 42, 44, and de-emphasis circuit 46, 48 produces the left and right signals respectively. A 19 KHz. signal in quadrature with that supplied by divider 34 and in phase with the received pilot signal is derived from divider 58 and compared with the received pilot signal at 60 to operate a stereo indicator 64 when the pilot signal is present. The output of detector 60 is also supplied via an OR gate 66 and circuit 70 to disable the stereo detector 40 in the absence of the pilot signal so that the L + R signal only is supplied to the output circuits. If it is desired to indicate stereo reproduction rather than stereo reception, the indicator 64 is connected to the output of the OR gate 66. Interference suppression.-Noise detector 68 is supplied with the 114 KHz. signal from divider 28 so that a voltage representing noise components is developed across capacitor 76. This voltage is compared with a reference value and via OR gate 66 controls the stereo disabling circuit 70. Circuit details.-The frequency dividers use bi-stable, and logic circuitry, Fig. 2 (not shown), as disclosed in Specification 1,332,516. The amplifier 24, Fig. 5, provides push-pull output signals via transistors 561, 563 respectively. The input signal is supplied via terminal T 1 to a differential amplifier comprising emitter followers 503, 549. Considering one half of the amplifier the signals are coupled to transistor 503 via Darlington-connected transistor 513. The collector current of transistor 503 is maintained substantially constant by feedback circuit from the collector coupled to the base of variable impedence transistor 505 via emitter follower 515, a current source transistor 517 and cascaded emitter followers 523, 525, 527. Bias is supplied to transistor 517 via emitter followers 537, 539, transistor 527 being direct coupled to transistor 523 in parallel with transistor 525. This ensures that the base voltages applied to transistors 517 and 505 are equal and the no signal collector currents are also equal. The second half of the amplifier is identical with the exception that the base of transistor 549 is maintained at a fixed voltage by resistor 551 and Zener diode 553. In operation the input signals tend to vary the collector current of transistor 503, 549 differentially but the feedback circuits vary the impedances of transistors 505, 559 to maintain the collector currents substantially constant, the base-emitter circuit of the output transistors 561, 563 being connected in parallel with the base emitter circuits of transistor 505, 559 respectively. In order to ensure rapid turn-on of the amplifier when power is applied the relatively large filter capacitor 78a, is charged via a transistor 565 which is switched to low impedance when the receiver is switched on. As the capacitor is charged a transistor 567 starts to conduct and when the charge reaches a predetermined voltage it turns off transistor 565 which remains cut off until the receiver is switched off and on again. Similar circuitry is associated with the capacitor 78b. The controlled oscillator 26, Fig. 6 (not shown) is of the type disclosed in Specification 1,317,625. The stereo decoder, Fig. 7, detects the L - R component and combines it with the L+R component to produce the left and right signals. The composite signal is supplied in push-pull to transistors 701, 703 which correspond to transistors 561, 563, Fig. 5, and whose collectors are connected to switching transistor pairs 709, 711 and 713, 715 respectively which are switched by the 38 KHz. output of divider 318 (30, Fig. 1). Push-pull L-R signals are developed across resistors 717, 719 respectively and via emitterfollowers 721, 723 are developed across resistors 725, 727 and combined with the L+R signals supplied via transistors 729, 731 respectively to produce the left and right signals. In order to compensate for the unwanted modulation of the base-emitter voltages of transistors 721, 723 as the collector currents of transistors 729, 731 vary, signals complementary to those supplied to transistors 729, 731 are supplied to transistors 737, 739 connected to the emitters of transistors 721, 723 respectively. Stereo disabling signals (from 70, Fig. 1) are supplied via transistor 741 to the base of a switching transistor 745 whose collector and emitter are connected to the collector and emitter of a transistor 751 biased via transistor 749 and resistors 753, 755, 757. When transistors 749 and 751 are conducting voltages V BE , 4V BE and 7V BE are developed across resistor 757, at the junction of resistors 753, 755 and at the emitter of transistor 749 respectively. Upon loss of stereophonic information or when the signal to noise ratio is poor transistors 741 and 745 switch off causing transistor 749 followed by transistor 751 to conduct the switching rate being increased by the feedback path including transistor 771. This caused transistors 759, 761 to conduct and disable the L - R detector and transistors 763, 765 to conduct so that the direct bias voltage to transistors 721, 723 is maintained equal for both stereo and mono reproduction. The noise detector and pilot signal presence detector are also described in detail Figs. 8 and 9 (not shown). The noise detector includes pulse stretching means by which it is arranged to discriminate between continuous noise (where switching to monophonic reception is desired) and the momentary pressure of high level start duration bursts of noise (where switching to monophonic reception is not desired). The reference signal level is arranged to be automatically increased for high signal levels. The pilot signal detector provides that short term fading of the pilot signal will not interrupt stereo reproduction. When the pilot signal is present but the signal-to-noise ratio is unacceptable, the stereo indicator light is switched off and the receiver reverts to monophonic reproduction.