DE2063525A1 - - Google Patents

Description

7122-70 / Kö / S
RCA 61,772
Convention Date:
December 29, 1969

RCA Corporation, New York, N.Y., V.St.A,

Decoder for multiplex signal mixtures

The invention relates to a decoder for multiplex signal mixtures, the at least one pilot frequency component and one Carrier-suppressed modulated subcarrier component with twice the Frequency of the pilot frequency included. The decoder is suitable especially for stereo broadcast receivers.

According to the standards currently in use in the USA for stereophonic FM broadcasting, the sum becomes a main carrier two stereophonically linked audio frequency signals, namely the Left signal (L) and the right signal (R), frequency modulated, where the carrier for compatible reception with either monophonic or stereophonic FM receivers. Of the The main carrier is also provided with stereophonic information in the form one suppressed, with the difference (L-R) of the two stereophonic. nically linked audio signals of amplitude-modulated subcarrier so * such as a continuous pilot signal for use in demodulating the suppressed subcarrier in the receiver, including in some cases yet another subcarrier frequency modulated with commercial background music (SCA) comes, modulates.

With a conventional FM stereo receiver, the output an FM detector or frequency discriminator the composite signal from the summed signal component (L + R), which is either in mono or can be used in stereo receivers and a Freauenz -

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range from, for example, 0 to 15,000 Hz, a 19 kHz pilot signal and sidebands of a suppressed 38 kHz subcarrier, in which the differential signal component (LR) and the one. Frequency range from 2.3 to 53 kHz include generated. The signal &'emic can also contain a background music (SCA) frequency modulated 67 kHz subcarrier and its sidebands, which range from 59 to 75 kHz, for example. This commercial component is generally removed in home receivers using tuned filter circuits.

To reproduce the stereophonic sound programs in the home receiver, the 19 kHz pilot signal is usually taken from the rest of the composite signal removed with the help of further matched filter circles ~ and becomes a phase matched to the 19 kHz pilot signal 38 kHz carrier for demodulating those in the sidebands of the suppressed subcarrier stuck difference signal information generated. For the generation of the 38 kHz carrier and its association with the difference signal information usually become different inductive elements (coils and / or transformers) used, These and other inductive elements required in the matched filter circuits mentioned above are proportionate bulky and expensive. They make the production of the receivers more difficult, since they usually have to be set and compared, for which complex electronic test devices are required. When using several inductive elements, these must be spatially arranged so that no undesirable interaction or coupling can take place between them.

Furthermore, the matched band filter circuits that normally Relatively high 0 values are used for the separation of the pilot signal and the restoration of the 38 Hz subcarrier, so they are quite phase sensitive. That is, one relatively small shift in the resonance frequency of the tuned circuit has a relatively large change in the phase response of the filter for signals of the nominal tuning frequency (IQ kHz or 38 kHz). In the case of an FM stereo decoder, such a change in the phase response of a filter worsens the separation of the stereophonic left and right signals (i.e. it

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crosstalk occurs between the two signal channels). Shifts of the type mentioned are often caused by changes the inductive or capacitive values as a result of operating temperature fluctuations or signs of aging.

The invention is therefore based on the object to provide a decoder for a multiplex radio receiver that is relatively few inductive circuit components. The decoder should preferably be designed so that it is in Can build integrated circuit form.

Relatively low-level signals of the abovementioned type which occur in FM stereo decoding circuits, can in fact be advantageously using monolithic integrated circuit die (ie, solid state circuits in which a \ ^r ielzahl ie of active semiconductor devices such as transistors and diodes as \ ^ passive formwork elements how capacitors and resistors and their interconnections are attached to a common substrate made of semiconductor material). Such integrated circuits are superior to conventional circuit arrangements with discrete components in terms of size, weight and reliability and, in some cases, also in economic terms.

When designing integrated circuits are, opposite Discrete component circuits take into account a number of economic considerations. While one, for example in the case of non-integrated circuits, the aim is to get by with as few active components as possible, since these are used as Discrete components are relatively expensive, in the case of integrated circuits it is not so important to use active components to save, as their production in integrated form is less expensive. On the other hand, in the case of integrated circuits, the aim is to Provide as many circuit functions as possible on the circuit board and with as few circuit elements as possible get along outside of the circuit board. Integrated circuits are not as attractive when combined with the circuit die Coils and / or transformers are provided

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have to. This is because such inductive circuit elements not only have a detrimental effect on costs, size, weight and reliability, but they also require one or more of the relatively few available connection contacts on the circuit board (e.g. sixteen in a typical version) for their interconnection. Furthermore, because of the relatively small dimensions of the circuit board (e.g. of the order of 2.5 x 2.5 mm or smaller) and the resulting close spacing between the supply lines for external circuit elements, the number of external supply lines for alternating current signals is desirable to be kept low in order to avoid undesirable couplings between the various parts of the circuit board as much as possible. Especially in the case of an integrated FM stereo decoder circuit, it is desirable that, f _; the 19 kHz and 38 kHz signals are processed exclusively within the circuit board, so that a coupling of out-of-phase signals to the 38 kHz recovery stages is prevented because, as mentioned above, phase errors in the 38 kHz subcarrier cause crosstalk between the left and result in the right tone channel.

It is therefore desirable for the frequency selection (band filtering) to use arrangements with active components without inductive components in an integrated circuit. Such a frequency choice can be done in such a way that a certain signal component with a corresponding locally generated carrier signal ^ is superimposed so that a zero frequency related or referenced Difference frequency signal arises, which then with the help can be filtered by simple RC filter circuits. One frequency selection in this way can advantageously be achieved with integrated circuits with the aid of amplifiers which are designed as symmetrical or push-pull synchronous detectors.

The decoder according to the invention for multiplex signal mixtures is characterized by a controllable oscillator for generating clock signals; a frequency converter that is under control by the clock signals a first reference oscillation with a predetermined phase relationship thereto and a second reference oscillation

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generated with twice the fundamental frequency of the first reference oscillation; a signal coupling arrangement, the signals from a source * of the multiplex composite signal transmits and its pass band essentially the entire frequency band of the multiplex composite signal includes; a first synchronous detector which is coupled to the signal coupling arrangement and which responds to the first reference oscillation and responds to the multiplex signal mixture and generates a control signal which shows the phase and frequency deviations between the first reference oscillation and indicates the pilot frequency component and is fed to an input of the controllable oscillator and this in Meaning of a minimization of the mentioned phase and frequency deviations regulates; and one coupled to the signal coupling arrangement, responsive to the second reference oscillation second synchronous detector, which is synchronous with the frequency of the second reference j vibration demodulated components of the multiplex signal mixture generated.

In one embodiment of the decoder for an FM stereo receiver, the only oscillator is tuned to a harmonic of the 19 kllz pilot signal Reference oscillation related in time to the oscillator output oscillation with a subharmonic (nominally 19 kHz) of the frequency of the oscillator output oscillation. The frequency converter is preferably free of inductive circuit elements. The AFPR circuit further includes the first synchronous detector, the vibration from the reference Λ and produces the signal demodulated in the receiver mixture ,, containing the received pilot signal, a DC voltage corresponding to the phase difference between the reference vibration and the pilot signal. A control arrangement coupled to the synchronous detector changes the phase and / or frequency of the oscillator in accordance with the DC voltage indicating the phase error in such a way that the oscillator output oscillation; maintains the predetermined frequency and time relationship with the received pilot signal.

at

An arrangement / is also coupled to the oscillator, which

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a 38 kHz subcarrier in a predetermined time relationship to the 19 kHz pilot signal for demodulating the stereophonic difference signal components (L-R) generated. The second synchronous detector, which includes the 38 kllz auxiliary carriers and the composite signal of the received differential signal sidebands are generated two output signals, the antiphase tone difference signal components (L-R) and - (L-R) represent. The antiphase tone difference including signal components and the demodulated composite signal the tone sum signal component (L + R) are fed to a matrix circuit, the separate left and right tone signals (L) and (R) for that produces sound. For example, these signals further amplified and then fed to loudspeakers.

fc With FM stereo receivers it is also desirable that the listener

is displayed when stereophonic ^ broadcasts are being received. Usually a lamp is used for this, which lights up when Im received Signal there is a pilot signal of adequate amplitude and duration.

In a further development of the invention, a stereo display is provided with the oscillator coupled arrangement is provided, which has a further, compared to the reference oscillation fed to the AFPR detector by 90 phase-shifted 19 kHz oscillation generated. Preferably this is Arrangement free of inductive circuit elements. A third synchronous detector is with the 19 kHz oscillation phase shifted by 90 and containing the received pilot signal fe composite signal is fed and generated when the Pilot signal is an output signal which is fed to a display device Is, which then visually indicates the reception of stereo broadcasts »

It is well known that in order to produce an acceptable stereo sound signal becomes the signal to noise ratio (the signal to noise ratio) of the received FM broadcast signals are larger than it is for monophonic ones Transfers; necessary 1st »From the point of view of the listener it can Therefore, under certain reception conditions it may be more advantageous if the received stereo signals are monophonic or monaural be played back

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In a further development of the invention, an arrangement is therefore provided which measures the signal-to-noise ratio of the received signal mixture and automatically switches to monophonic reception if the signal is too noisy for an acceptable stereophonic reproduction. The oscillator of the decoder is preferably set up in such a way that it operates at a frequency that corresponds to an even \ ^; is a multiple of the received pilot signal (19 kHz), the even multiple being chosen so that the oscillator frequency is above the frequency band of any signal component of the signal mixture (zE at the sixth or twelfth harmonic of the pilot signal). A fourth synchronous detector is fed with an over-band reference oscillation derived from the oscillator output and with the demodulated signal mixture including any interference components. A relatively low-frequency output signal from the detector, which represents the interference components, is compared with a predetermined acceptable interference threshold value Above the interference threshold value, a stereo indicator and / or an automatic stereo switching arrangement is supplied with a stereo blocking signal, so that the receiver can switch to mono operation if the processed signal mixture is too noisy for an acceptable stereo reproduction.

According to the preferred embodiment of the invention is

a single oscillator provided with a frequency of beitet ar \, which is an even harmonic of the pilot signal and the stereo difference subcarrier and is located above the highest signal frequency component of the composite signal. A number of inductance-free frequency divider arrangements are coupled to the oscillator and supply four synchronous detectors with four harmonically related reference signals. The synchronous detectors are also fed with the demodulated signal mixture and set up so that the oscillator is adjusted to a predetermined time relationship (phase relationship) to the pilot signal component of the signal mixture, that the presence of the pilot signal component is indicated that

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the stereophonic ^ difference signal component of the composite signal is demodulated and that the presence of over-band interference components is displayed in the composite signal.

The invention is explained in detail below with reference to the drawings. Show it:

Figure 1 shows the block diagram of an FM radio receiver with FM stereo decoder according to an embodiment of the invention ^

FIG. 2 shows the circuit diagram of a bistable counter unit with logic circuits that can be built up in integrated form Use as a frequency divider in the arrangement according to FIG

FIG. 3 shows a block diagram that illustrates how several counter units according to FIG. 2 are interconnected can be in order to generate the switching oscillations required in the arrangement according to FIG. 1 for the synchronous demodulation;

Figure 4 shows a series of waveforms in the arrangement switching vibrations generated according to Figure 3;

FIG. 5 shows the circuit diagram of an amplifier which can be built up in an integrated form for the stereo signal mixture in the arrangement according to Figure Ij

Figure 6 shows the circuit diagram of a buildable in integrated form voltage-controlled oscillator arrangement with AFPR push-pull detector for the arrangement according to Figure Ij

FIG. 7 shows the circuit diagram of a push-pull synchronous detector, which can be built up in an integrated form, for the stereophonic difference signal with automatic stereo switching arrangement and matrix amplifiers for obtaining left and right tone signals for the arrangement according to Figure Ij

FIG. 8 shows the circuit diagram of a push-pull synchronous detector, which can be built up in an integrated form, for over-band interference components with associated power supply for the Anordx tion according to Figure 1 j and

Figure 9 shows the circuit diagram of an integrated push-pull synchronous detector for the presence of the pilot

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signals with; associated stereo reception display and switching device for the arrangement according to Figure 1,

FIG. 1 shows the simplified block diagram of an M radio receiver for the reception of monophonic or stereophonic broadcasts. Numerous signal paths are shown as a single line that starts from one block and is divided into two lines before entering another block This indicates that the signals running over the lines concerned are push-pull signals (ie two signals out of phase by 180 and otherwise largely identical) The radio receiver has the usual FM receiving section 20 for selective reception, amplification and the demodulation of FM radio signals. The FM receiving section 20 supplies an input T. of an FM stereo decoder circuit 22 with either an audio-frequency sum signal (L + R) in the case of the reception of mono broadcasts or, in the case of reception of stereo broadcasts, with a stereo signal mixture, consisting of a sum signal (L + R), a control or pilot signal (19 kHz) and a Difference signal (LR) in the form of a carrier suppressed subcarrier. In addition, FM background music signals (SCA) can be present at the input T _{1 in both cases.}

For the sake of simplicity, the signal supplied to input T ₁ is always referred to below as a "composite signal". In the stereo decoder 22, all circuit elements and units within the dashed block are preferably built up in integrated form on a single semiconductor substrate. Terminals (connection contacts) T ₁ to T ₁ ^ are provided on the integrated circuit board for connection to external circuit elements, signal sources or other circuits.

The demodulated composite signal delivered to the terminal contact T _{1 of} the decoder 22 is fed to a stereo amplifier 24, which amplifies signals in the range from approximately 10 Hz to 150 kHz linearly, so that it delivers two essentially identical, but 180 phase-shifted (i.e. push-pull) amplified composite signals which different circuit elements

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are fed directly in the stereo decoder 22. The stereo decoder 22 also contains a voltage-controlled oscillator 26, which generally oscillates at a frequency of 228 kHz, an even harmonic of both the 19 kHz pilot signal and the 38 kHz S auxiliary carrier a parallel resonance circuit with a coil 82 and a capacitor 80 is determined, which is arranged outside the circuit board of the decoder 22 and to this via the connection contacts T ^ and T-. are connected. The 228 kHz output oscillation of the oscillator 26 is, as will be explained later with reference to FIG. 6, shaped to an essentially symmetrical rectangular shape. The output oscillation of the oscillator 2 6 is determined with the help of an automatic frequency and phase control circuit (AFPR circuit) in a predetermined time relationship to the received

The same 19 kHz pilot signal is held. The AFPR circuit contains a frequency divider arrangement coupled to the output of the oscillator 26, which generates an oscillation at a frequency (nominally 19 kHz) which is an integer sub-multiple (1/12) of the oscillator oscillation frequency and is in a predetermined time relationship to the oscillator output oscillation. The desired frequency division and time relationship are determined with the aid of a first frequency divider 28, which divides the output oscillation of oscillator 2 by 2 (to nominally 1.14 kHz), and a second frequency divider 30, which divides the output oscillation of frequency divider 28 by 3 (to nominally 38 kHz) and a phase selector 32 coupled to the frequency divider 30, which feeds a third frequency divider 34 with a predetermined one of two opposing phases of the oscillation of nominally 38 kHz. The frequency divider 34 divides the output oscillation of the phase selector 32 by two and feeds an AFPR push-pull synchronous detector 36 push-pull with an oscillation of nominally 19 kHz. The push-pull composite signal including the 19 kHz pilot signal from the stereo amplifier 24 is also fed to the AFPR detector 36. On a outside of the circuit board 22 arranged filter capacitor 38, which has connection contacts t. and t _P is coupled to the AFPR detector 36, a differential DC voltage is generated, itfelche the phase difference between the received

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the pilot signal and the nominal 19 kHz oscillation from the output of the oscillator 26 reproduces. This differential DC voltage is symmetrical or push-pull from the capacitor 38 the oscillator 26 coupled to its oscillation frequency and phase correct accordingly. The AFPR circuit holds the 19 kHz output oscillation of the frequency divider 34 essentially in a special 90 phase relation to the received 19 kHz filot signal.

The frequency divider 30 generates the required 38 kHz auxiliary Carrier oscillation for the demodulation of the difference tone signal (L-R) from the received sidebands of the suppressed 38 kHz subcarrier These sidebands, together with the rest of the signal mixture at the output of the stereo amplifier 24, become a push-pull Subcarrier push-pull synchronous detector 40 supplied. The one from the

locally generated 38 kHz subcarrier originating from the frequency divider, the kept in the correct phase and frequency by the AFPR circuit is in push-pull from the output of the Frequency divider 30 supplied to the subcarrier detector 40. The detector 40 is, as will be explained later, as "doubly symmetrical" Synchronous detector (synchronous ring demodulator) designed and therefore generates push-pull output signals including (L-R) and - (L-R), the desired difference tone signals. The positive ones and negative difference tone signals are matrix amplifiers 42 and 44, which also receive the summed audio signal (L + R) and the remaining part of the composite signal from amplifier 24.

The matrix amplifiers 44 and 42 generate uncompensated left and right tone signals (L) and (R) _{at their outputs T ^ 0} and T _{11, respectively.} These uncompensated left and right tone signals are fed to conventional equalization circuits 46 and 48, and the resulting compensated signals, after amplification in sound amplifiers 50 and 52, respectively, are coupled to loudspeakers 54 and 56, respectively. The equalization networks 46, 48 also remove the ultrasonic residues originating from the push-pull demodulation process and the pilot signal and modulation components of the 38 kHz subcarrier that are present in the composite signal at the output of the stereo amplifier 24.

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It is also ensured that the stereo decoder 22 indicates if in the signals supplied by the FM receiving part 20 stereo transmissions available. For this purpose, the presence of the pilot signal, which is only available for stereophonic, on the other hand, is not perceived in monophonic broadcasts. The stereophonic broadcast detector includes a fourth frequency divider 58, which is connected to a second output of the phase selector 32 is coupled to which an oscillation fed to the frequency divider 34 is phase-shifted by 180 even 38 kHz oscillation occurs. This second output oscillation of the phase selector 32 is divided by 2 in the frequency divider /, see above that a 19 kHz oscillation is obtained, which has a predetermined phase position of approximately 90 to the output oscillation of the frequency p divider 34 has and is substantially in phase with the received pilot signal. The pilot signal, along with the rest of the part of the composite signal from the stereo amplifier 24 is in push-pull coupled to a pilot signal push-pull synchronous detector 60. Furthermore, the detector 60 is the output signal of the frequency divider 58 fed in push-pull, so that capacitors 62a, 62b, which are coupled between terminal contacts T- or To and ground, differential DC voltages are generated.

The differential DC voltage between the connection contacts T_ and Tq is amplified in the detector 60, so that at the output / 0 -

Terminal T _Q, a DC voltage related to ground potential is provided, which indicates the presence of the pilot signal in the received signal. A stereo indicator 64 connected to the terminal contact T _Q , which typically consists of an incandescent lamp and a switch transistor, provides a visual display of the stereo reception »

Furthermore, an arrangement is connected to the subcarrier detector 40 , which blocks or switches off the subcarrier demodulation stages if the prolonged absence of a pilot signal of a certain minimum amplitude indicates that a non-stereophonic (monophonic) transmission is being received, or if the signal-to-noise ratio (the signal-to-noise ratio ) of the received signal is too bad for satisfactory stereo reproduction

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is. The blocking arrangement contains an OR gate 66, which has an input to the connection contact tg for the pilot signal detector and connected with a second input to an interference push-pull synchronous detector 68, the task of which will be explained later! sen is.

Upon receipt of a corresponding signal from the output of the pilot signal detector 60, the OR gate 66 provides an output signal to a stereo blocking circuit 70 which in turn is coupled to the subcarrier detector 40 so that the detector is blocked if either no acceptable pilot signal is present or the demodulated composite signal has an insufficient signal-to-noise ratio for acceptable stereo reproduction. When the subcarrier detector 40 is blocked, only monophonic information (L + R) is supplied to the matrix amplifiers λ 42 and 44. As will be explained in connection with FIG. 8, the stereo display 64 is connected to the output of the OR gate 66 instead of directly to the detector 60 when the stereo reproduction (instead of the stereo reception, as explained above) is to be displayed. The stereo blocking circuit 70 includes a delay element with a _{capacitor 72 coupled between the terminal contact T 1} - and ground and a resistor (not shown) which can be provided on the integrated circuit board 22, for example. The resistor and the capacitor 72 are dimensioned with such a large time constant, that the permanent presence of a pilot signal indicator on the output of the detector (one second, for example) is 60 for an extended period needed before the sub-carrier detector 40 is activated can \ be.

The interference detector 68 is fed with the push-pull composite signal from the output of the stereo amplifier 24 and the push-pull square wave with the fundamental frequency of 114 kHz from the frequency divider 28. A capacitor 76 coupled between the terminal _{contact T 1} - and ground connected to mmmm delfc ilusgSngf of the disturbance detector 68 generates a voltage which indicates disturbance components in the signal mixture whose frequencies are higher than the highest useful signal component. It has been found to be useful to have such over-band disturbances

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a frequency in the vicinity of 100 kHz. The special one Frequency of 114 WBz is here for simplicity in view chosen to be controlled by the voltage controlled oscillator 26 whose operating frequency is limited to a harmonic of both the 19 kHz pilot signal and the 38 kHz subcarrier is. The perceived over-band disturbances are in a suitable arrangement (shown in Figure 8) in the disturbance detector 68 compared to an allowable signal-to-noise ratio reference level, and if the perceived signal-to-noise ratio is below the allowable Is threshold value or reference level, the OR gate 66 is supplied with a blocking signal. As mentioned earlier, the stereo indicator can 64 be connected to the output of the OR gate 66, so that the stereo indicator lamp goes out whenever the stereo lock circuit 70 locks the subcarrier detector 40.

As can be seen from FIG. 1, further external connection contacts are provided on the decoder circuit board 22. For example, a connection contact Tg is connected to ground and a connection contact T _t "is connected to an external operating voltage supply B +. The connection contacts T 1 and T 1 are connected via numerous line connections (not shown) within the circuit board to various circuit elements within the individual blocks. The corresponding interconnections are shown in detail in the further figures.

Outer capacitors 78a and 78b are coupled between ground and the connection contacts T ₁ and T ₁ / r for the stereo amplifier 24. As will be explained with reference to FIG. 5, the capacitors 78a and 78b are used for signal derivation in the preamble circuits of the stereo amplifier 24

■ Λ

FIG. 2 shows a counter unit or circuit with input and output circuits which can be used for the frequency dividers 28, 30, % 9t _{s 34 FIG.} As shown in Figure 1, all

<2 β, ί, Ρ / * τ » 5 8 borrowed circuit elements of the frequency divider within the decoder plate 22. All circuit elements in Figure 2 can therefore be provided in integrated form on a single circuit plate.

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In the frequency divider or in the counter unit, transistors 201 and 203 together with collector resistors 205 and 207 form a bistable toggle or flip-flop circuit by connecting the collector of transistor 203 to the base of transistor 201, the collector of transistor 201 to the base of transistor 203, the interconnected emitter of transistors 201 and 203 to a bias source (+3 V _Rp , i.e. three times the base-emitter voltage drop of a conductive npn transistor on circuit board 22) and the interconnected collector resistors 205 and 207 to an operating voltage source (e.g. +6.2 volts ) are connected. The specified operating and bias voltages for the counter unit are based on a / reference level, which in the present case is ground.

Transistors 209 and 211 together with collector load resistors 213 and 215 form a second or commutation flip-flop which is switched in the same way as that described above Flip-flop, except that the emitters of transistors 209 and 211 are common to a trip or trigger circuit with a source of control or trigger pulses (e.g. the voltage-controlled oscillator 26 in Figure 1), which via a resistor 217 to the Base of a switch transistor 219 is coupled, are connected. The emitter of the transistor 219 is connected to reference potential (ground) and its collector is connected to a current limiting resistor 221 connected to the interconnected emitters of transistors 209 and 211.

In the flip-flop with the transistors 201 and 203 lies between the base and the collector of the transistor 203 the series connection of two touch diodes 223 and 225, which in the same sense as the Collector-base diode of transistor 203 are coupled, as well as the series circuit between the base and collector of transistor 201 two touch diodes 227 and 229 polarized in the same sense. The connection point of the diodes 223 and 225 is directly with the Connection point between the collector of the transistor 211 and the base of the transistor 209 connected. The connection point of the Diodes 227 and 229 is directly connected to the junction between the collector of transistor 209 and the base of the transistor

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211 connected. A clamping transistor 231 is on its base to the connection point of the emitters of transistors 201 and 203, with its collector on B + and with its emitter on Ver Connection point of the emitters of transistors 209 and 211 connected.

In operation, every time the base of transistor 219 a trigger pulse is supplied, either one or the other of the two transistors 209 and 211 and a corresponding one of the transistors 201 and 203 switched to the conductive state, so that the flip-flop with the transistors 201 and 20 3 its state changes. The transistors 209 and 211 in the commutation flip-flop then both switch back to the blocked state to the expected next trigger pulse. When the next trigger pulse occurs, that of the transistors 209, 211, the remained blocked during the previous trigger pulse, in the conductive state, so that the state of the flip-flop 201, 20 3 is changed again.

It is assumed that transistor 203 is conductive and transistor 201 is non-conductive. In the case of the bias voltage illustrated in FIG. 2, a voltage of +4 V _Rp (eg approximately +2.8 volts) is applied to the base of the conductive transistor 203 and the same voltage is applied to the collector of the non-conductive transistor 201. At the same time is applied to the collector of the conductive transistor 203 and at the base of the non-conductive transistor 201 a voltage of approximately +3 V ^, - plus the collector-emitter saturation voltage of the transistor 203 (for example a total of +2.2 volts). It can therefore be seen that the output voltages at the collectors of transistors 201 and 20 3 alternate between approximately +3 V and +4 V (the relatively low collector-emitter saturation voltage of approximately 0.1 volts is neglected in the following for the sake of simplicity). In the commutation flip-flop 209, 211, when the trigger pulse on transistor 219 is absent, neither transistor 209 nor transistor 211 is conductive. Since the collector of transistor 201 _{carries a voltage of +4 V x} , ^ and the collector resistor 213 of transistor 209 via diode 227 between this voltage and the operating voltage source (+6.2 volts), the

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is greater than 5 V ", the diode 227 is forward-biased into the conductive state, so that the base of the transistor 211 carries a voltage of +5 V". For similar reasons, the base of the transistor 209, because of its connection to the base of the transistor 201 via the diode 225, carries a voltage of +4 V _n ". When transistor 219 is turned on (driven to the saturation state) by a positive trigger pulse, the collector current of transistor 219 is controlled into transistor 211, since the voltage at the base of transistor 211 is more positive (+ Vpρ higher) than the voltage at the base of transistor 20Q. The transistor 211 was therefore controlled into the saturation state, so that its collector voltage tends to drop to a value which is essentially equal to the sum of the collector-emitter saturation voltages of the transistors 211 and 219 f. However, the clamping transistor 231 continues so that its emitter voltage remains at approximately +2 V ". The collector

of transistor 211 therefore essentially also has the voltage +2 Vpp, which is coupled from the collector of transistor 211 to the junction point of diodes 225 and 223: the base of transistor 203, which has been a voltage VOI1 since this transistor has been conductive + 4V, its voltage now drops to the sum of the above-mentioned collector voltage of transistor 211 (+2 Vp) and the voltage at diode 223 (V _n "). Since the emitter of transistor 203 carries a voltage of +3 V "", transistor 20.1 stops conducting. With increasing collector voltage of transistor 203, the transistor is controlled into the inlet μ was 201, and the switching of flip-flop 201, 203 is completed.

When the next trigger pulse occurs, the transistor 209 conducts so that the flip-flop 201, 203 changes its state again. Two ßmitterfolertransistors 233, 243, which are connected with their collectors to an operating voltage of + (, 2 volts

203

are, with their bases to the bases of the transistors 8 ¹ -Jr and

& 6 turned on. Logic voltage levels of +2 V and +3 V _ur , for direct feed to the synchronous detectors shown in FIGS. 7, 8 and 9, are generated at the emitters of the transistors 233, 243.

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The emitter of transistor 233 is also connected to a voltage divider made up of resistors 23 5 and 237, which with their center. point to the base of another emitter follower transistor 23 ^ are connected to ground. A resistor 241 couples the emitter output of the emitter follower transistor 239 to ground. The voltage divider reduces the logic voltage levels by a factor of 3/4 »and each of the emitter folder transistors 233 and 239 produces a voltage drop of 1 V _Dr in the signal passing through it. The logic voltages generated at the resistor 241 are then for the two logic states +1/4 V _11n and +1/2 V _n “above the gate voltage. These logic voltage levels are particularly suitable for switch transistors whose emitters are essentially zero or ground potential.

A similar conversion takes place through the series connection W of two resistors 247 and 249, which form a voltage divider emitter load for the emitter follower transistor 243. The center point of resistors 247 and 249 is connected to the base input of a transistor 245. The transistor, which is designed as an emitter follower circuit, has its collector connected to the operating voltage of +6.2 volts and its emitter connected to ground via a resistor 251, at which logic output voltages can be taken.

Considering the operation of the counter unit according to Figure 2, it is seen that the counter as a frequency divider, for example a frequency divider 28 in Figure I, ver \ can be used. If the trigger input signal fed to transistor 219 is a square wave with the fundamental frequency of 2.28 kHz, as supplied by oscillator 2i in FIG. 1, the counter according to FIG kHz, as required for the frequency divider 28. Furthermore, through suitable interconnection of several counters in the manner of the arrangement according to FIG. 2, the further frequency division and selection processes which the frequency dividers 30, 34, 58 and the phase selector 32 in FIG. 1 have to carry out can be accomplished.

An interconnection of two or more such counters takes place

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-IQ-

advantageously with the aid of circuit elements !! which fulfill logical IJHi) and ODF-R functions. If, for example, the counter according to FIG Fulfill logical OUER function with the help of an additional transistor, which is connected with its base to an output of the second counter and with its collector and emitter directly to the corresponding electrodes of the transistor 219. Such an OR function results from the application of the positive term (ie a logical "1" is defined by a higher voltage "than a logical" (I "). A logical Γ '-" ^ - function with suffixes In the present case, von Fosit ivlicür can expediently be fulfilled by providing an ODI ¹ JI-point i.on in "egativlogic" using the complements of the data and then reversing the output variable of the OR-clause.

7 * The counter shown is complemented by logic Outbreak of frayed counter transistors such as the transistor 2 ^ 9 removed, and the emitters of all output transistors for a particular negative OR operator are to a single Resistor coupled as resistor 241. A suitable one Inverter stage is switched by one in the manner shown "· Ransistor 25? Is formed.

If any of the complemented logical output variables at the resistor, e.g. resistor 241, is a logical "1" (1 1 4 λ *) during operation, a "1" is sent to the base of transistor 253 via resistor 255, * so that this leads. The Triggereinran * T to transistor 210 is blocked, and the flip-flop 201 ,? .O t does not change its state when a trigger pulse occurs. If, on the other hand, the input variable of "transistor 253" is a logic "0" (V _R _.- '2, as described above "!), The trigger pulse reaches transistor 21Q, so that flip-flop 201, 203 switches over.

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Several output variables can easily be taken from both sides of the flip-flop 201, 203 by parallel to transistor 239 additional transistors, for example one Transistor 2 57, switches, which can be connected to a logic element of the type of transistor 2 53.

FIG. 3 shows in block form several counters with connecting logic circuits. Each counter can be designed in the same way as the arrangement according to FIG. 2, while the logic functions (AND and OR) can be fulfilled in the manner described above with the aid of the "corresponding arrangements according to FIG. 2. The use of positive logic is assumed below. For the sake of simplicity, positive logic AND gates are shown as logic elements in Figure 3. As mentioned, however, the AND operation in the present case can be achieved particularly easily by using a circuit arrangement such as the resistor 255 and the transistor 253 in connection with the Transistor 219 is supplied with the complement of a particular signal.

In Figure 3 (see also Figure 4) the voltage-controlled supplies te 228 kHz oscillator 26 a substantially sinusoidal continuous oscillation to a limiter circuit 310, which at its output a square wave with a base frequency of 228 kHz (Signal curve A, Figure 4) generated. This 228 kHz square wave A is the trigger input (T) of a first frequency dividing bistable toggle or flip-flop circuit 312, which at their outputs ("0", "1") complementary 114 kllz square waves (Signal curves B, B, Figure 4) with positively and negatively directed Level transitions, those with the positive level transitions coincide in signal A. The 228 kHz square wave output of the limiter 310 is also fed to an inverter stage 314 which has a 228 kHz square wave at its output (Signal curve Ä, Figure 4), which is the complement of the Represents output oscillation of limiter 310 provides. That is, the individual negative level transitions in the signal A essentially coincides with the positive-going level transitions in signal A, and vice versa.

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A second flip-flop .316 that its state synchronously with only certain of the positive level transitions in signal A changes, delivers an asymmetrical pulse at its output ("1") ■ signal (signal curve C, Figure 4). The positive and negative ones Level transitions in signal C essentially coincide with certain positive transitions in signal A together. The way in which the signal C is generated will be explained later will.

A third flip-flop 318, the complementary square wave output generated with a base frequency of 38 kHz is on its input (T) with the simultaneous occurrence of a positive transition in signal A and a "high" level ("1") in Signal C triggered. The triggering of the flip-flop 318 is done by that the 228 kHz output oscillation of limiter 310 (signal A) and the asymmetrical output oscillation of flip-flop 316 (Signal C) are coupled to a UMD element 320. The output signal of AND gate 320 is sent to the trigger input (ϊ) of the Flip-flops 318 coupled so that this at its outputs ("0", "1") complementary square waves (signals D, D) with a Base frequency of 38 kHz generated. The output oscillations D, D of the flip-flop 318 can be fed to the synchronous detector 40 in FIG will. The combination of flip-flops 312, 316 and 318 is the frequency dividers 28 and 30 in Figure 1 equivalent and serves to the 228 kHz output swing of limiter 310 (signal A) through 6 to share. The individual level transitions in signals D and D occur synchronously with a positive level transition in the 228 kHz signal A.

A fourth flip-flop 322 generates complementary square-wave output oscillations (signal curves E, E) with a fundamental frequency of 19 kPIz. The triggering of the flip-flop 322 takes place in that the 228 kHz output oscillation of the limiter 310 (signal A), the asymmetrical output oscillation of the flip-flop 316 (signal C) and one of the 38 kHz output oscillation of the flip-flop 318 (signal β) is an AND gate 324 can be supplied. The output signal of the AND element 324 arrives at the trigger input ( ^T ) of the flip-flop 322, which is the one required for the operation of the AFPR detector 36 in FIG

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19 kllz vibrations generated. The individual level transitions in the Signals E, E occur in relation to one another in time positive level transition in signal A, as is the case with the 38 kllz oscillations D, T). The over-fermented in the / initial oscillation of the lip-flop 3 °? - therefore fall in time essentially with level transitions in the output signal of the flip-flop 318 together. The positive level over range in signal E coincide with negative level transitions in signal D. Through this synchronous relationship ", which is constantly maintained, since the flip-flops, 318 and 3? 2 triggered in parallel by the A signal are, an accurate synchronous demodulation of the stereo phonic difference signal information is ensured, so that a Crosstalk is largely prevented, as will be explained with reference to FIG. A fifth flip-flop 3 28 generates complementary ones Square wave output oscillations (signal curves F, F) with a fundamental frequency of 19 kHz and a phase shift of essentially 90 with respect to the signals E, E. The triggering of flip-flop 328 occurs when one of the 38 kHz output swings of flip-flop 318 (signal D), one of the 19 kHz output oscillations of flip-flop 322 (signal E) and one of the 19 kHz output oscillations of the flip-flop 328 (signal F) are fed to a U> D element 330. Furthermore, the other output oscillation is the Flip-flops 318 (signal D), the other output swing of the Flip-flops 322 (signal E) and the other output oscillation of the Flip-flops 328 (signal F) are fed to a further AND gate # **! ·.

The output oscillations of the U ^ D elements 330, 332 are combined in an OR element 334, the output of which is connected to the trigger input (T) of the flip-flop 328. While each of the flip-flops 312, _S 316, 318 and 322 is triggered by one of the 228 kHz signals A, A, the flip-flop 328 only receives trigger information from other of the associated flip-flops. The signals F, F are therefore somewhat delayed compared to the basic clock signals A, A. This delay does not affect the basic mode of operation of the pilot signal detector 60, which processes the signals F, F, except that it supplies a somewhat reduced output voltage. In contrast, the delay is advantageous for the operation of a pulse stretching circuit; exploited,

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BATH ORIGINAL

as will be explained with reference to Fijnir 8.

It will now be explained how the asymmetrical output oscillation (signal C) of the flinflop .1If * is generated. That of the flip-flop .110 takes place in that the 228 kHz output oscillation of the inverter stage 314 (signal A), the 114 kHz output oscillation of the flip-flop .312 (signal P-) and the 38 kHz output of the flip-flop .118 (signal I. )) to an AND gate .336. Furthermore, the 228 kHz output oscillations of the inverter stage 314 (signal A), the other 114 kHz output oscillation of the flinflop Tl? (Signal B) and the other 38 kllz output oscillation of the flip-flop, 318 (signal Ϊ5) fed to an FVD element 33S. Furthermore, the 228 kHz output oscillation of the inverter stage 314 (signal A), the first-mentioned 38 kHz output oscillation of the flip-flop 318 (signal D) and the output oscillation of the flip-flop 31 ( ^; (signal C) are fed to a ^T> 'D element 340 The output variables of the AND elements 1.1 ("," 3b, 340 are combined in an OR element 34 2, the output of which is connected to the Hggereinfang (T) of the flip-flop 316. Since all UVD elements 33t-, 338, 340 the 228 kHz trigger signal Ä is supplied, and since, as explained in connection with Figure 2, the i-lipflop? K (as well as the other flip-flops shown) changes its state, if at all, only when a positive trigger pulse is supplied , it is clear that the flip-flop 316 changes its state when certain of the positive, directed transitions occur in the signal A. In contrast, the other flip-flops 312, 318, 322, 328 change their state essentially when positive transitions occur in the signal A, the a h albe period of the 228 kHz oscillation are shifted in relation to the positive-going transitions in the signal Ä. Another feature of the output oscillation of flip-flop 316 is that the high ("1") and low ("0") signal portions have unequal duration (ie signal C is asymmetrical). Such an asymmetrical waveform is particularly useful for generating the 38 kHz oscillations D-, D are advantageous, for which the 228 kHz oscillation A must be divided by 6 (ie a number that is not an integer power of 2).

In the above-described frequency divider arrangement works

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BATH ORIGINAL

the oscillator 26 at a frequency that is an integral harmonic the 38 kHz subcarrier frequency and an integer harmonic which is 19 kKz pilot frequency. This choice of working frequency of the oscillator 26 facilitates the generation (or timing adjustment) of the individual leading and trailing edges of the 38 kHz switching signal from a single polarity of the oscillator clock pulse output oscillation. The central axis passages of the 38 kHz switching oscillation are precisely controlled in this way, so that a good separation of the demodulated stereophonically linked Sound signals result, as will be seen "

Other timing relationships are possible; However, the system described above has the advantage, - that the linkage ^ and frequency divider circuits are particularly simple.

Mary can also make the required sets of complementary Generate square waves using different linking functions than in the arrangement according to FIG. For example can be used to generate the output signal of the flip-flop 316 the AND gate 340 the input signals A, C and B instead of the input signals A, C and D as in FIG. One receives on in each case the same signal forms as in FIG. 4 · Also in other ways Modifications are possible.

Each of the flip-flop, the two logic states have one or the other ( "1" or ⁿ 0 ") upon initial power of the system. In order to obtain the desired relative time relations W between the outputs of the various flip-flops which this upstream link circuits have these two For example, the flip-flop 316 can initially have one of the two states ("1" or "0") when a trigger pulse is supplied via the OR gate 342. The AND gate 340 ensures that the positive and negative directed transitions in signal C, as shown in FIG

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Result in signal curves.

The manner in which the square waves B, B, D, 5, E, E and F, F are utilized in the decoder arrangement 22 will be explained with reference to FIGS. 6, J, 8 and 9.

Figure 5 shows the circuit diagram of a stereo amplifier, accordingly the amplifier 24 in Figure 1, for the generation of balanced push-pull stereo signal mixtures. The stereo amplifier according to FIG. 5 is particularly suitable for the construction in integrated form on the circuit board 22 according to FIG. 1.

In FIG. 5, the composite signal supplied by the FM receiver is coupled to a symmetrical or push-pull differential amplifier circuit via a capacitor 501 arranged outside the circuit _{board 22 and the terminal contact T 1 of the circuit board 22.} The two halves of the push-pull amplifier circuit each form an emitter follower stage with a shunt regulator in the emitter load impedance. One half of the differential amplifier circuit contains an emitter follower transistor 503 with signal-variable emitter load impedance, which contains the collector-emitter path of a shunt regulating transistor 505, the emitter of which is connected to ground via a resistor 507. The collector of transistor 505 is connected directly to the emitter of emitter follower transistor 503 and to one end of an output load resistor 509. The collector of the transistor 503 is connected to an operating voltage source (B +, for example +8.5 volts) via a resistor 511.

The composite input signal is from the terminal contact T via an emitter follower transistor designed in a Darlington configuration 513 coupled to the base of emitter follower transistor 503. Of the The collector current of transistor 503 is increased with changes in the input signal mixed by a feedback from the collector of the emitter follower transistor 503 to the base of the variable impedance transistor 505 is kept substantially constant. The feedback circuit includes an emitter follower transistor 515 as well a DC voltage transmission network with a power source

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transistor 517, which with; its emitter through a resistor 5 ^ 9 is connected to ground and its collector is connected to the emitter of transistor 515 via a resistor. The collector of the current source transistor 517 is connected to the base of the transistor 505 via a cascade of emitter follower transistors 523, 52 5 and 527 each with an emitter load resistor 529 connected to ground, 531 or 533 coupled. A resistor 53 5 is between the emitters of transistor 523 and the base of transistor 525 are coupled.

The base of the current source transistor 517 is biased via emitter follower transistors 537 ^and 539 with emitter load resistors 541 and 543, respectively. The transistor 537 is overall electrically via a resistor 535 resistor 545 equal to the emitter-follower transistor 523 in parallel with the emitter follower transistor 52 couples 5 w. AC signals are derived at the input of the transistor 537 through a capacitor 78a which is arranged outside the circuit board 22 _{and is connected between the connection contact T 1} and ground (FIG. 1).

The circuit configuration described above ensures that the current source transistor 517 and the bypass control transistor 505 equal base bias voltages (DC voltages) obtain. Both transistors 505 and 517 get theirs Base bias from the same source (the emitter of transistor 52 3) through substantially identical circuit elements. The bases of the transistors 505 and 517 can have DC voltage be viewed as-directly connected to each other. The Emitterar ™ series resistance 507 of transistor 50 5 is twice as large as the emitter working resistance 519 of transistor 517 · However is the resistor 519 is also connected to a corresponding current source transistor ^ 547 of the other half of the differential amplifier and therefore receives a direct current twice as large as resistor 507. The direct voltage drops across the resistors 507 and 519 are therefore the same, and the base-emitter voltages are DC of transistors 505 and 517 are essentially the same. The collector quiescent glitch currents (in the absence of a signal) of transistors 505 and 517 are therefore essentially the same when there are are identical transistor designs, as it is with

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an integrated circuit is the case.

,. . The second half of the differential amplifier is designed the same as the first half, with the exception of the fact that the base of the emitter follower transistor 549 with constant collector current is not fed with signals, but is kept at an essentially fixed DC voltage by means of a voltage divider with a resistor 551 and a zener diode 553, which are connected between a voltage source (B +) and ground, and with their connection point with a designed in Darlington circuit emitter follower transistor 555 a, the base ⁿ of the transistor 549 is coupled. The base of the transistor 513 in the differential amplifier half described above is also connected to the Zener diode 553 via a resistor 557.

In the same way as described for transistors 505 and 517, the collector quiescent currents of transistors 547 and 559 are equal to one another and, due to the differential circuit via resistor 519, all four collector quiescent currents (517> 505 »547 ) 559) are essentially the same. Also, all base biases at corresponding points in the two amplifier halves are essentially the same (e.g., the voltages at the bases of transistors 517 and 547 and the voltages at the bases of transistors 50 and 549 are the same). The amplifier therefore gives good common mode rejection of the bias voltages. Furthermore, due to the differential circuit across resistor 519, the base bias voltages of a plurality of output transistors, such as transistors 561 and 563, are all the same. In the quiescent state (signal-free state), essentially no current flows in the resistor 509 coupled between the emitters of the transistors 503 and 549. That is, these emitters have essentially the same DC voltage around 2 V _n -

below the voltage on the zener diode 553.

In operation, the connection contact T ₁ via the capacitor 501 supplied signal mixtures endeavor to modulate the collector current of the transistors 503 and 549 in a differential manner

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or change ₀ However, 505 and 559 changes due to the feedback from the collectors of transistors 503 and 549 to the bases of transistors 50 5 and 559, the impedances of the transistors in such a sense that the collector currents of the transistors 503 and 549 is substantially constant If, for example, the input signal mixture increases in a positive direction in a sense that increases the current conduction of transistor 503, the base of transistor 505 receives a less positive signal via the associated feedback, so that the resistance of transistor 505 increases. At the same time, the current conduction of the transistor 54.9 is lowered by the input signal (which is fed to the emitter of the transistor 549 via the transistors 513 * 503 and the resistor 509), while due to the feedback in the second. Amplifier half the flow line ™ of transistor 559 increases so that the collector current of transistor 549 remains essentially constant «The current is fed from transistor 503 via resistor 509 to transistor 559 * The decreased collector current of transistor 50 5 and the increased collector current of the transistor 559 represent the amplified input signal mixture. Amplified push-pull output signal mixtures are obtained in that, for example, the base-emitter paths of one or more transistors, for example transistors 561 and 563, are connected in parallel to the base-emitter paths of transistors 50 5 and 559, so that Current amplifiers for coupling the output signals to, for example, detectors 36, 40, 60 and 68 in FIG. 1 result in »

The stereo amplifier 24 provides a linear signal amplification in the frequency range from 10 Hz to 150 kHz and couples the amplified Signals through transistors 561 and 563 to a number of variable impedance load or consumer elements.

To enable the amplifier 24 to be switched on quickly when it is switched on of the receiver are measures to quickly charge the relatively large filter capacitors 78a and 78b hit. The charging arrangement for the capacitor 78a contains a transistor 565 whose collector is connected to the operating voltage supply (B +), with its emitter across the

109852/1100

circuit contact T ₁ - is connected to the capacitor 78a and with its base ar a switching signal source. The switching signal source switches the transistor 565 to a conductive or low-resistance state when the receiver is switched on and to a non-conductive or high-resistance state after a predetermined time interval. The switching signal source contains a transistor 567 whose collector is connected to the operating voltage supply (B +) via the series connection of two resistors 569 and 571, its emitter to ground via a resistor 573 and its base to the base of transistor 517, for example. The collector of transistor 567 is connected directly to the base of transistor 565.

The arrangement of positions for the capacitor 78b contains two additional transistors and an emitter resistor (not shown) which are connected to the operating voltage supply B + in the same way as the transistors 565, 567 and the resistor 573. The base of the additional transistor corresponding to transistor 567 is connected to the base of transistor 547, while the emitter of the additional transistor corresponding to transistor 565 is connected to terminal contact T ₁ ^. The operation of the charging circuit for the capacitor 78a will now be described; the similar charging circuit for capacitor 78b operates in the same way.

When the main power supply (B +) of the receiver is switched on, the transistor 565 conducts essentially immediately since the voltage B + is applied directly to its base. The transistor 567 is in the high-resistance state at this point in time. The capacitor 78a is charged very quickly via the transistor 565, and the bases of the transistors 537, 539, 517 and 567 receive their operating voltage. When transistor 567 begins to conduct, the voltage at the base of transistor 565 drops, so that transistor 565 is driven towards the blocked state. When the capacitor 78a has a predetermined rest target voltage, the transistor 565 is blocked and remains in this state is turned off until the receiver again and turned on.

109852/1100

Figure 6 shows the circuit diagram of a controlled oscillator, which is particularly good for production in integrated form is suitable and is set up for an operating frequency of 228 kHz, as indicated in FIG. The same circuit elements in FIG. 6 and 1 are denoted by the same reference numerals.

The controlled oscillator is from that described in the United States patent application Serial No. 862,705 by the same applicant (filed on October 1, 1969) described Art.

The controlled oscillator 26 provides essentially square wave output waves (Signals A, Ä, Figure 4) with a fundamental frequency of 228 kHz and a predetermined phase relation to the 19 kHz pilot signal at the output of the stereo amplifier 24 for the clocking to the frequency divider circuits in Figure 3.

The oscillator 26 includes an amplifier arrangement with a Matched LC network in a feedback branch between the output and input of the amplifier. The designed as a differential amplifier Amplifier includes emitter coupled transistors 611 and 619 with a common emitter resistor 613, which is connected to ground. The matched LC network consists of a coil 82 and a capacitor 80 connected between ground and a common input output point 607 of the differential amplifier are coupled, this common point being the base of a Darlington pair with the transistor oll interconnected transistor 609 is. Of the Transistor 6I9 is also similar to transistor 617 in one Darlington circuit connected. The collectors of transistors 609 and 611 are directly connected to the operating voltage supply (B +), while the collectors of transistors 617 and 619 are connected to B + via a load resistor 615. The interconnected collectors of the transistors 617 and 619 are connected to the input starting point 6O7 via a DC voltage transformer arrangement connected to a pnp transistor 6O3, the emitter of which is connected via a resistor 621 B +, with its base connected to resistor 6I5 and with its collector is connected to the connection point between the anode of a diode 62 3 and the base of a transistor 6ÖI. The Ka-

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method of diode 623 is grounded. A resistor 605 is connected between the emitter of transistor 601 and ground, while the collector of transistor 601 is connected directly to the base of transistor 609 (ie, input exit point 609) .

As mentioned in connection with FIG. 1, the coil 82 and the capacitor 80 are located outside the integrated circuit board 22 and are connected to it via the connection contacts T ₉ and T _n . The base of the transistor 617 is connected to the connection contact T », a point at which the direct voltage is essentially equal to the connection contact T ₂ connected to the base of the transistor 609. Output signals developed at resistor 615 are coupled to output terminals A and A through emitter follower transistor 677 and suitable voltage transfer and inverter arrangement 671.

The resonance circuit with the coil 82 and the capacitor 80 is assigned a current sensor arrangement with a constant current transistor 625 designed in an emitter follower circuit which is coupled to a bypass control or load-variable transistor 627. The base of the transistor 62 5 is biased to an essentially fixed voltage by a reference voltage source consisting of the series connection of a resistor 629 and a Zener diode 031 connected via the voltage supply B +. A feedback for the shunt regulation of the current in the emitter follower transistor 625 takes place from the collector of the transistor 625 to the base of the transistor 627 via a direct voltage transmission network with a forward-biased diode 63 Sy a Zener diode 637 and a resistor 639 connected to ground. The emitter of the transistor 625 is directly connected to the Connection contact T ″ for the coil 82 connected. The collector of the transistor 627 is connected to the connection contact T "via the emitter-collector path of a line-controllable transistor 64I". The transistor 641, together with a similarly operating transistor 643 and the transistor 627, forms a current splitter arrangement for the provision of a controllable reactive current parallel to the coil 82, as described in detail in the US patent application

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Serial No. 862 759 by the same applicant (filed on I.IO. 1969). Differential control DC voltages for Changing the reactive current flowing parallel to coil 82 turns transistors 641 and 643 through emitter follower transistors 645 and 647 supplied by the AFPR push-pull synchronous detector 36. The detector 36 includes a first differential amplifier detector with a first composite signal current source transistor 649j of the is connected to one of the push-pull outputs of the stereo amplifier 24 according to FIG. For example, the transistor corresponds to 649 to transistor 561 in FIG. 5 «The first differential amplifier detector according to Figure 6 further contains two switch transistors 65I and 653) with their emitters together to the Collector of the current source transistor 649 »with their collectors to a corresponding one of the outputs T- and T_ and with their bases to a corresponding one of the complementary 19 kHz square wave outputs (E, E) of flip-flop 322 in Figure 3 are connected.

The detector 36 further includes a second differential amplifier detector having a second composite signal current source transistor 655 of the two with its collector connected to the emitter of switch transistors 657> 659 is connected (like the transistor 563 in Figure 5). " The base of transistor 655 is connected to the other of the two push-pull outputs of the stereo amplifier in FIG. The bases of the transistors 657 and 659 are connected to the complementary square wave outputs E and E of the flip-flop 322 in FIG. The collectors of the transistors 657 and 659 are connected to the output contacts T- and T. That is, the collectors of the transistors 651, 653, 657 and 659 are cross-connected. The cross-connected collectors of transistors 653 and 657 are connected via a collector working resistor 66I and the collectors of transistors £ j and 659 are connected to an operating voltage source (B +) via a collector working resistor 663. Instead, in order to minimize the effects of a possible mismatch between the resistors 66I and 663, one can also use smaller sized resistors (eg 6K) and those from the connection contacts

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T, and Τ_ remote ends of these resistors together

4 5
and connect it to the operating voltage via an additional common resistor (e.g. also 6K, not shown). A ^p filter capacitor 38 for the output signal is outside of the integrated circuit chip between the terminal contacts T. and T-coupled. Further filter capacitors 673, 675 are connected outside of the circuit board between the connection contacts T. or T_ and ground. The capacitors 673 and 675 serve to reduce the dynamic range of the demodulated signals. The emitters of the current source transistors 649 and 655 are grounded through resistors 665 and 667, respectively, and are cross-coupled through a resistor 669 to increase the gain in the detector.

During operation, the oscillator circuit generates an essentially sinusoidal _{oscillation at the connection contact T 0 with a nominal}

frequency of 228 kHz, the mainly dure * Me coil 82 and the capacitor 80 is determined.

The sinusoidal oscillation generated at the resonance circuit 82, 80 becomes through the differential amplifier 6Ο9, oll, 617? 619 with associated Circuit elements are limited symmetrically, so that a symmetrical one Square wave with a fundamental frequency component of 228 kHz is generated at resistor 615. This square wave will via the transistor 677 with the associated DC voltage transmission arrangement coupled to terminal A and is there as one of the two complementary 228 kHz square wave output waves ready. The second 228 kHz square wave output at terminal A is due to the additional voltage transmission and Inverse arrangement 671 generated. Typically, they create tension Transmission arrangements Square waves with upper and lower voltage levels of almost 2 volts and zero level.

The square wave output oscillations A, A are in the context of Figure 1, 3 and 4 in frequency divider and logic circuits' to inter alia complementary 19 kHz switching signals E, E m'.t predetermined phase position to the 228 kHz square wave ^; .-. i, _} Ä, corresponding to the relevant signal curves in Figure 4 »ver

1 09852/1 100

is working. All positive and negative directed transitions ln < Signal E coincide with positive-going transitions in signal A, the positive-going transitions in signal E respectively coincide with every twelfth positive-going transition in signal A.

The phase of the 19 kHz switching oscillations E, E is recorded in the AFPR detector 36 with the phase of the 19 kHz pilot signal from the stereo amplifier 24 compared. At the connection contacts T. and T_

4 5

differential DC voltages generated whenever the Piloj; The signal component at the output of the stereo amplifier 24 is not phase-shifted by 90 with respect to the 19 kHz switching oscillations E, E. The polarity of the DC voltage at the connection contacts T. and T- indicates whether the pilot signal follows or follows the switching oscillation rushes. The differential DC voltages are the current splitter transistors 641 and 643 supplied so that a reactive current is generated parallel to the resonance circuit 82, 80, the size of which is sufficient to the phase and / or the frequency of the oscillator 26 im Meaning of a re-establishment of the required 90 phase relationship to change between the 19 kHz oscillations. The numerous Output signals of the flip-flops shown in FIG. 3 are therefore in a predetermined phase relationship with the 19 kHz output pilot signal of the stereo amplifier 24 so that the recovery of the pilot signal, stereo difference signal and over-band interference information can be done with the help of synchronous detectors, as will be explained in connection with FIGS.

The non-synchronous components (ie all components with the exception of the 19 kHz pilot signal) of the supplied stereo signal mixture and the _{19 kHz switching oscillations E, E supplied to the bases of the transistors 65I 5} 653 * 657 »659 do not generate any DC voltage components due to the synchronous nature of the detector 36 the output contacts T., T-. Other high-frequency components which are generated by the detector 36 are removed at its output by the low-pass filtering of the capacitor 38 and the associated resistors.

An initial setting of the working frequency of the oscillator

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gate 26 can be done by applying the DC voltage to the Terminal contacts T. and T_ measures in the absence of a received stereo signal, the receiver is tuned to a stereo signal and then changed the inductance of coil 82 (e.g. with the aid of a tuning core) so that the previously measured voltages to be restored. The oscillator 26 then operates with its nominal frequency of 228 kHz in the desired phase relationship to the received 19 kHz pilot signal. This comparison is usually carried out in the factory, but can easily be done by a service technician at home as it is very simple and does not require complicated testing equipment. this is the only frequency adjustment that is carried out for the entire decoder circuit 22 according to FIG. 1 and the other figures must become.

Figure 7 shows a particularly good for the execution in an integrated Form and connection to the stereo amplifier 24 (Figures 1 and 5) and the flip-flop 318 (Figure 3) within the integrated Circuit board 22 suitable differential signal detector and Matrix amplifier circuit for demodulating the differential signal component (L-R) of the stereo signal mixture and the union of this component with the audio sum signal component (L + R) below Generation of stereophonically linked left and right channel audio signals.

The differential signal detector contains a double symmetrical synchronous detector (ring demodulator) with two current source transistors 701 and 703 »which correspond to transistors 561 and 563 in Figure 5 correspond. The bases of the transistors 701 and 703 are each connected directly to one of the push-pull outputs of the stereo amplifier 24 connected in Figure 5. The emitters of transistors 7OI and 7O3 are connected to ground via a resistor 705 or 707. Of the The collector of transistor 701 is directly connected to the interconnected emitters of a first pair of switch transistors 709, 711, while the collector of transistor 703 is connected directly to the interconnected emitters of a second pair of switch transistors 713 * 715 is connected. The bases of transistors 709 and 713 are connected to one of the complementary ones

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38 kHz square wave outputs (D) of flip-flop 318 (Fi »τιν .3) connected, while the Eases of transistors 711 and 715 on the other of these complementary 38 kHz square wave outputs (D) are connected. An operating voltage source (3+) is via an output resistor 717 to the collectors of the two Transistors 7OQ and 715 and via a resistor 717 essentially the same output resistance 719 to the collectors of the two transistors 711 and 713 connected.

Push-pull output signals containing the demodulated T, ifferenzsignalkomponenten / (LR) and - (LR) J , are generated at resistors 717 and 719 and coupled to emitter follower transistors 721 and 723, respectively. The transistors 721 and 723 serve as voltage sources and generate the desired push-pull differential signal components at resistors 725 "and 727 and 731 generated, which are connected with their collectors to the resistors 72 5 and 727 and with their bases to one of the counter clock outputs (at which L + R is available) of the stereo amplifier 24. The emitters of the transistors 729 and 731 are each connected via a resistor 733 or 735 to ground. The transistors 723 and 731 form the matrix amplifier 42 (FIG. 1), whose output signal (eg R) via the connection contact T _1. , The equalization, 11

network 46 and a sound amplifier to a sound reproduction device, for example a loudspeaker is paired. The transistors 721 and 729 form the matrix amplifier 44 (Figure 1), its output signal (e.g. L) via the connection contact T-, q> the equalization network 48 and a second sound output amplifier is coupled to e.g. a second loudspeaker.

To the modulation of the base-emitter voltages of the Transisto _T ren ^to reduce 721 and 723 by collector current variations of the transistors 729 and 731 are on 729 and 731 supplied to signals complementary signal mixtures supplied from the stereo amplifier 24 with respect to the transistors to the bases of condensation transistors 737 and 739th The collectors of transistors 737 and 739 are connected directly to the emitters of transistors 721 and 723, respectively.

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closed. The emitters of the transistors 737 and 739 are each connected to ground via a resistor 741 and 743, respectively.

The current conduction of the transistors 731 and 739 changes by mutually equal amounts in accordance with the changes the output signals of the stereo amplifier 24 (push-pull input signals) . The sum of the collector currents of the transistors and 739 (which load transistor 723) therefore remains essentially constant. Likewise, changes in the output of stereo amplifier 24 do not cause changes in the load on the transistor 721, as the sum of the collector currents of the transistors 729 and 737 when the output signal of the stereo amplifier changes 24 remains essentially constant. An exact matrixing the sum and ^ ifferenzsignalkomponenten is therefore guaranteed.

During operation of the difference signal detector according to FIG. 7, the complementary 38 kHz square wave output oscillations of flip-flop 318 (D, D) are kept in the correct, predetermined phase relationship to the received pilot signal component, as explained in connection with FIGS. 3 and 6, so that synchronous demodulation of the difference signal is achieved . The push-pull synchronous detector with the transistors 701, 709, 711 and the transistors 703, 713, 715 supplies complementary signal components including voltage components, which reflect (LR) and - (LR), at the resistors 717 and 719, respectively and 723 and, before equalization, combined at the resistors 725 and 727 with currents which represent the sum signal component (L + R) supplied by the amplifier 24. The sum signal current components are fed to the corresponding load resistors 725 and 727 via the current source transistors 729 and 731. By superimposing the differential signal voltages and the total signal currents, the desired matrixing results, which is essentially independent of the load on the output contacts T and T ₁₁ . The equalization networks + tr and fHr coupled to the contacts T and T ₁₁ modify the matrixed signals in such a way that the desired left and right tone signal components (L)

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BATHROOM ORIGINAL

- 3ο -

and (Κ) result. Because of the double-symmetrical nature of the synchronous detector and the low-pass characteristics of the equalization networks 46, 48, no components other than the desired left-tone and right- tone signals occur at the output filter capacitors of networks 46, 48.

Correct matrixing of the sum and difference signal components depends in part on the matching of the current source transistors 701, 7O3j 729> and 731 delivered streams. Such an adaptation can be done in the case of an integrated circuit relatively easily achieved by using essentially identical transistors 701, 703, 729, 731 and essentially same emitter resistors 705, 707, 733 and 735 close together on the circuit board 22 attaches.

The correct matrixing also depends on the ratios of the resistors 717 and 719 to the resistors ^ 2 5 and 727. In the present double-symmetrical synchronous detector arrangement, the so-holder transistors 709, 711, 713, 715 are fed with symmetrical 38 kHz rectangular oscillations of the correct phase position, so that a full-wave or two-way demodulation of the 38 kHz differential signal carrier takes place. The resulting peak-to-peak value of the audio frequency components of the demodulated difference signal is linked to the peak-rectified carrier at the output of the detector by the factor 2 / ff . The peak differential carrier for the composite signal is set in accordance with the standards for stereo broadcasting so that it is equal to the peak sum component for a Murlink signal or a right-only signal. In order to obtain a perfect matrixing of the sum and difference signals, one dimensioned the resistors 717 and 719 ^/ 7T / 2 times as large as the resistors 725 and 727 at which the sum signal components are generated.

The synchronous detector according to FIG. 7 also contains an arrangement which the differential signal demodulation circuits automatically blocks or switches off if either the prolonged absence of a pilot signal exceeding a predetermined amplitude indicates that a non-stereophonic (monophonic) program

10985271100

is felt, or the signal-to-noise ratio (signal / interference ratio) of the received signal than for a satisfactory stereo reproduction is not considered sufficient. The way in which a stereo blocking signal is obtained is illustrated with reference to the figures 8 and 9 explained. For now, suffice it to say that a such a blocking signal is generated in the above two cases.

In the arrangement according to FIG. 7, the stereo blocking signals are fed to an amplifier with a first transistor 741, which has its collector to the operating voltage source (B +), its base to a source of the stereo blocking signals and its emitter via a resistor 743 to the base of a switch transistor 745 is connected. The emitter of the transistor 745 is connected to ground, and an output switching signal is taken from the collector of this transistor via a resistor 747 connected to the operating voltage source. The output of switch transistor 745 is connected to a multiple V "bias source from the US patent application Ser. Ko. 680 4 8.1 by the same applicant (filed on 3 x 11 x 1007). The term "V" here denotes the forward voltage drop at the base-emitter junction of a normally conducting transistor (eg approximately 0.05 to 0.7 volts for silicon transistors such as those found in integrated circuits). Reference voltage sources (usually within the integrated circuit) that contain one or more integer multiples of V "_ above zero potential

on

providing low impedance, are referred to as "multi-V _B _-voltage sources". In the present case, the multiple V voltage source contains a transistor 749 in a collector circuit and a transistor 7 51 in an emitter circuit, which are connected together with negative feedback. The collector of the transistor 749 is connected to the operating voltage source, while several resistors 753, 755? 757 are connected in series between the emitter of transistor 749 and ground. The junction of resistors 755 and 757 is connected to the base of transistor 751. The emitter of transistor 751 is connected to ground, while the collector of transistor 751 is connected directly to the base of the transistor

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sistor 749 is connected. As explained in the last-mentioned USA patent application, there is a voltage equal to V _ßE at the resistor 757 when the transistors 749 and 751 are conducting. The quick value of the resistor 7 57 is dimensioned smaller than the base emitter resistance of the transistor 751 * and the additional resistors 7 53, 7 55 are dimensioned smaller than the input resistances of the corresponding stages to which they are coupled. In this case, a voltage is generated across each of the series-connected resistors 7 53 and 7 55, which is equal to the product of V_ "and the ratio / between the respective resistor (753 or 7 55) and the resistor 7 57 7, a voltage of 7 V is generated at the emitter of transistor 749 and a voltage m. of 4 V is generated at the connection point of resistors 753 and 755.

The junction of resistors 753- * and 755 is connected to the bases of white stereo blocking transistors 759 and JfI . The emitters of the transistors 7 59 and Jβ 1 are connected to the interconnected emitters of the ^c switch transistors 7 ^ 9? 711 or the interconnected emitters of the switch transistors 713, 715 are connected. The collectors of transistors 7 59 and 7 ^ 1 are connected together and connected to the emitters of current splitter transistors 7 ^ 3 and 7 ^ 5 via an emitter resistor 7 ^ 7 or Jf9. The bases of the transistors 7 ^ -3 and 765 are connected directly to the emitter of the transistor 749 (7 V if the multiple V-ρ voltage source works). The collectors of the transistors 7 ^ 3 and JiS are connected to the resistors 717 and 719, respectively. bound.

A feedback device is connected between the input and the output of the switchable multiple Vp voltage source in order to increase the speed with which the arrangement switches from stereo to mono operation. This feedback circuit contains a transistor JJ1 which is connected with its collector via a resistor 773 to the base of the transistor 745, with its base via a resistor 775 to the emitter of the transistor 74 '·' and with its emitter to ground.

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In operation, when the arrangement to be explained in connection with FIGS. 8 and 9 indicates that stereo information suitable for reproduction is not present or is no longer present, the voltage at the base of transistor 741 falls below a predetermined value (for example 1 volt) , and the transistors 741 and 741 begin to switch to the non-conductive state. The voltage at the base of the transistor 749 stiffens in a positive ilichtune, so that the transistor 749 and then the transistor 751 conducts, whereby the multiple -Y _p p- voltage source is switched on. 'this ^c; The switching process is supported by transistor 771, which, together with transistors 74 ^ and 751, begins to conduct. The transistor 771 switches off the transistor 745 very quickly as soon as the switching process begins. A positive voltage remaining at the junction of the .vi of the stands 753 and 755: (4 Vr ,, -,) causes the stereo blocking transistors 75 ^ and Jt 1 to conduct. Likewise, a positive voltage (7 V _RE ) available at the emitter of transistor 749 causes current splitter transistors 7 & 3 and 7 ^ 5 to conduct.

When transistors 759 and 701 are conductive, they are connected together Emitter of switch transistors 70? and 711 as well as to the interconnected emitters of the switch transistors and 715 a positive voltage (3 V. ",) coupled, which is sufficient to block these switch transistors and thereby the differential signal detector to lock or switch off. The push-pull supplied via the current source transistors 701 and 703 Composite signals are then passed through blocking transistors 759 and 76I derived and cancel each other out at the connected collectors of transistors 759 * 7 ^ 1. There are also the DC components of the output signals of the current source transistors 701 and 703 are combined. These combined direct current components are then passed through resistors 767, 769 and the transistors 7 ^ 3, 7 ^ 5 split into equal components that on the load resistors 717 and 719 are coupled. It will therefore the DC biasing voltage across the matrix transistors 723 and 723 for both stereo and mono playback kept the same. If this were not the case, i.e. if

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switching of the arrangement from one to the other operating mode the bias would change, so would one in the speakers thud can be heard. Such an unwanted sound is prevented by the arrangement described above.

The differential signal detector will remain state in the out operation, switched to by the presence of an appropriate pilot signal corresponding input signal to the transistor 741, the transistors 741 and 745 and thus the multiple V - voltage source and the blocking and splitter steps are switched off.

As noted above, an input signal greater than about 1 volt (low current V of transistor 741 plus moderate current V _r of transistor 745) is sufficient to keep transistors 741 and 745 conducting (and hence stereo operation If, on the other hand, transistors 741 and 745 are switched off and transistor 771 is switched on (ie in mono operation), a positive voltage of more than volts is required at the base of transistor 741 to restart stereo operation, since in this case the resistors 743 and 773 are parallel to the input (base-emitter path) of the transistor 745 via the transistor 771 as a voltage divider. Namely, an input voltage of approximately 3 V (approximately 2 volts) is required at the base of transistor 741 to switch to stereo operation. The difference between the voltage levels required at the base of the transistor 741 for switching on the stereo operation or for maintaining it results in a desirable hysteresis characteristic, as a result of which the stereo reproduction, once it has been initiated, is retained even if there are brief fluctuations in either the received pilot signal level or occur in the signal-to-noise ratio of the demodulated signal.

When a stereo information suitable for Xtf playback is received and processed in the receiving part (indicated by the arrangement to be explained in connection with FIGS. 8 and 9), the base of transistor 741 receives a positive input

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voltage sufficient to make this transistor conductive α The transistor 745 also conducts, so that the input signal 3. of transistor 749 is not positive enough to render transistor 74Q conductive. It therefore becomes the multiple A 'voltage source with the transistors 749 and 751 and all transistors 759j 76I, 76.3 and 765 are switched off. Under these conditions operate the differential signal detector stages so that in Signals (L-R) and - (L-R) are generated in the manner described above. The transistor 771 is also under these conditions switched off.

FifTur δ shows an arrangement for perceiving the signal-to-noise ratio the received composite signal and to provide a stereo locking final, when this signal-to-noise ratio is below a predetermined threshold suitable for acceptable stereo reproduction. This signal-to-noise ratio detector with the associated stages is suitable particularly good for building in integrated form and for the Interconnection with the stereo amplifier 24 (Figure Ϊ and 5) and the flip-flops 312, 318, 322, 328 (Figure 3) within the integrated Circuit board 22.

The signal-to-noise ratio detector contains a push-pull synchronous detector u8 with two current source transistors SOI and 803, the bases of which are connected directly to one of the push-pull outputs of the stereo amplifier 24 in FIG. The emitters of the transistors SOI and 803 are connected to the cash register via a common emitter resistor 805. The collector of transistor 80I is directly connected to the interconnected emitters of a first pair of switch transistors 807, 8OQ, while the collector of transistor 803 is connected directly to the interconnected emitters of a second pair of switch transistors 8II, 813. The bases of the transistors S07 and Sl1 are connected to one of the complementary 114 kHz square wave outputs B ₅ B of the flip-flop 312 (FIG. 3), while the bases of the transistors 800 and 813 are connected to the other of these two outputs B, B. An operating voltage source (B +) is connected directly to the collectors of the transistors SO "and S13 so that

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as connected via the series connection of a forward-biased voltage drop diode 8I5 and a resistor 817 to the interconnected collectors of the transistors 809 and 8II. The interconnected collectors of the transistors 809 and 8II are also connected to the terminal contact T ₁ . of the integrated circuit board and connected to the operating voltage source (B +) via a Zener diode 819. A capacitor 76, which determines the bandwidth of the signal-to-noise ratio detector 68, is coupled outside the circuit board between the terminal contact T 'and ground. An interference threshold regulator, consisting of a regulating resistor 821 coupled via the operating voltage source and one between the connection contact T ₁ . and series resistor 823 coupled to the wiper of resistor 82I, may be provided outside of circuit die 22 to allow adjustment of the signal to noise level at which stereo blocking signals are generated. Instead, it is also possible to set an acceptable signal-to-noise ratio solely with circuit elements within the circuit chip 22, so that the circuit elements 821 and 823 can be omitted.

A transistor 825 and two Darlington-connected transistors 827 and 829 form a differential amplifier for noise perception. The base of the transistor 829 is connected to the terminal contact T ₁ -. The base of the transistor 825 is connected to a reference voltage source 831. The reference voltage source 831 is fed from a DC voltage balancing arrangement with transistors 5 ^ 7 and 83 5, which belong to the stereo amplifier 24, which are designed in a differential circuit. The bases of transistors 567 and 835 are directly connected to the bases of transistors 517 and 547 in FIG. The collectors of the transistors 567 and 835 are connected to the operating voltage source B + via the series connection of the resistors 569 and 57.1. A DC reference voltage taken from the junction of resistors 569 and 571 is coupled directly to the base of transistor 82 5. This reference DC voltage supply arrangement corresponds in terms of DC current to the interference detector elements 8OI-8I7 and supplies a DC voltage that changes in the same way as the quiescent DC voltage that the interference detector at the base of the

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Transistor 829 provides.

The output signal of the differential amplifier with the transistors 825, 827, 829 is generated at a resistor 843 which is connected between the operating voltage source B + and the collectors of the transistors 827 and 829 which are connected together. Connected to resistor 843 is an average value detector having an arrangement for increasing the duration of fault-indicating pulses. The mean value detector contains a detector transistor 845 'whose emitter is connected to ground via a resistor 847, its collector is connected to the operating voltage source B + via an operating resistor 849 & ⁿ and its base is connected to a pulse stretching circuit 851. The collector of the transistor 845 is connected to the connection contact To of the integrated circuit board (FIG. 1) and to the OR gate 6 ( in the case of the stereo blocking circuit (FIG. 1). The capacitor 62b (FIG. 1), which is also connected to the connection contact To, filters this Output of transistor 845

The pulse stretching circuit 85I includes a flip-flop with two transistors 853 and 855? as a flip-flop from Set-reset type are designed. Fault indication pulses generated at resistor 843 are applied to the set input of the flip-flop (i.e. the base of transistor 853) via a voltage transfer and Amplifier circuit with a transistor 8 57th, a Zener diode 8 59j a resistor 86I, a resistor 863 and a transistor 865 coupled. The circuit elements 857, 859, 86I and 863 are connected via the operating voltage source B + in the order mentioned. The resistor 843 is connected to the base of the Transistor 857 (which is of the opposite conductivity type to the vast majority of transistors on the integrated circuit die) while the base of transistor 865 is connected to the junction point of resistors 861 and 863 is. The collector of transistor 865 is connected to the base of transistor 853 and the collector of transistor 855. the The base of transistor 855 (the reset input of the flip-flop) is connected to a source of periodically repeating pulses, obtained by combining the output signals of the flip-flops 318,

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322 and 328 are obtained .. And that a 19 kH-i square wave output iJf? of flip-flop 322, which combines a 19? u? z output oscillation (F) of flip-flop 328 and a 38 kHz output oscillation (D) of flip-flop 318 by ORing and reversed twice in an amplifier with transistors 867 and 869. The collector of transistor 869 is connected to the base of transistors 855 and 871 (as well as to the collector of transistor 853). The extended output pulses of the flip-flop 853, 855, which are generated at the collector of the transistor 853, pass through a voltage transfer stage with the transistor 871, resistors 873 and 875 _? a transistor 877 and a resistor 879 to the base of the detector transistor 845

In the operation of the arrangement according to FIG. 8, that of the circuit 831 reference DC voltage supplied to the quiescent DC voltage, that is supplied to the base of transistor 829 by disturbance detector 68 is related. That is, the current source transistors 801 and 803 are in the same manner as the transistors 5 & 7 and 83 5 biased, and since only half of the direct current supplied by transistors 801 and 803 the load resistance. 817 is reached, the corresponding working resistance is 569 in the Reference voltage source 831 is only half as large as the work resistance 8I7 »The resistance 571 simulates the effect of the Switch transistors 809, 8II in detector 68. Diode 815 supplies as well as the base-emitter conduction threshold of transistor 829 part of the desired threshold shift between the Inputs of the transistors 825 and 827. Since the reference voltage source 831 and the detector 68 come from a common operating voltage source B + powered and in the same area on the circuit board 22 are arranged, fluctuations or changes in one DC voltage also occur in the other DC voltage and it is avoided that such changes affect the operation of the disturbance detector 68.

As is well known in FM receiver art, the Peak amplitude of audio signals (and higher frequency signals) at the output of the FM demodulator 20 independently of the respective Reception conditions (i.e. RF signal level and receiver noise) in the

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essentially constant. This means that the peak-demodulated amplitude is set by the frequency deviation on the transmitter side and the transmission characteristics of the demodulator, but not by the received signal amplitude. The stereo amplifier 24 gives a stable gain characteristic. An essentially constant DC voltage can therefore be used as a measure of the signal level at the output of amplifier 24. This DC voltage supplied by circuit 831 can then be compared with perceived noise components in order to measure the signal-to-noise ratio. The variable resistor 821, if present, is set by hand (in the manufacturer's works) so that the resulting bias voltage, the transistors 827 and 829 _{, are kept blocked for all detector output signals at the terminal contact T 1} , which are smaller than that given by this setting acceptable out-of-band noise levels. I.

The push-pull output signals of the stereo amplifier 24 are fed to the current source transistors 801 and 803. The switch transistors 809 and 811 are alternately switched between the saturated and the blocked state by the 114 kHz square-wave input signals B and B supplied to them by the flip-flop 312. Interference components in the output signal of the amplifier 24, the frequency of which is at or near the 114 kHz switching frequency, are transmitted by the superposition effect of the detector 68 in a frequency band ranging from zero upwards, while other components in the signal mixture outside the low-pass range of the filter with the Capacitor 76 and the associated resistors (e.g. resistors 821 and 823) are transferred. The ™ capacitor 76 is dimensioned in connection with the mentioned resistors so that the desired interference detector frequency response results. Interference components within the predetermined bandwidth around II4 kHz generate pulses _{at the connection contact T 1.} The transistors 827 and 829 respond to positively directed pulses, the amplitude of which, together with the bias voltage generated across the resistor 821 at the capacitor 76, is sufficient to overcome the bias voltage supplied by the transistor. Any such positive-going pulse that indicates the presence of excessively strong out-of-band interference is passed through the circuit with the

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Transistors 827, 829, 857, 865 with associated circuit elements transferred and reversed in polarity. The corresponding negatively directed pulses reach the base of transistor 853, so that flip-flop 8, 53, 855 is set (ie transistor 853 non-conductive, transistor 855 conductive and Auspanpssifnal for transistor 871 in the high-voltage or "1" state). <~, as' ^? lipflon $ 53, 855 remains in the "1" state until from transistor 8f? the next negative level transition to the Rücketzeinpanp at the base of the transistor 8 55 arrives. The generation of the reset pulses is illustrated in Figure 4 by the three signals - "E + F", "E + F + D and L + '+ O. When generating these reset pulses, the fact mentioned in connection with FIG output signal of the Plipflons 3-8 to a small interval (e.g., ^P. in fe of the order of 5 microseconds) versus d.en level transitions of the main trigger signals from the oscillator 2 (is delayed. the Rücksetzimnuls generated during this short delay interval.

If the flip-flop 853, 855 ^ ^{m is} "1" + .. (presence of excessive disturbance), the transistors 871, 877 and 845 are all conductive and the capacitor discharges (2b. If the excessive disturbance is present for a sufficiently long time , the capacitor 62b discharges to such an extent that the OR gate (C and thus also the stereo blocking circuit 70 is activated, as described in more detail in connection with FIG.

^ In the absence of interference-indicating impulses at the setting entrance of the flip-flop 8 53, 8 55, the pulses fed to the base of the transistor 8 55 keep the flip-flop 8 53, 8 55 in the »reset state, so that transistors 871, 877 and 845 are all turned off are. The voltage on capacitor 62b then only indicates the presence or absence of the pilot signal (see Figure Q), and the stereo lock circuit 70 operates accordingly.

The circuit with the flip-flop 8'53, 8 55 and the flip-flop 3 22 stretches the demodulated interference-indicating pulses, so that there is an effective increase in the demodulation gain of these interference pulses results, without the amplitude (the dynamic range)

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must be increased by signals, e.g. from the detector trensistor 845 and the upstream transistor stages will.

Namely, the interference pulses randomly occurring, which characteristically have a short duration and varying amplitude, during processing in the flip-flop 85.3, 855 i ⁿ pulses of variable duration (depending on the relative phase of the reset pulses, and the demodulated interference pulses) and a fixed amplitude (as determined by the "1" output voltage of 8 53, 855) implemented. Depending on the relative phase of the reset pulses and the demodulated. Interfering pulses, the Plipflop 85.3, 8 55 can have the "1" state on the output side over a period in the range from zero to the 19 kHz period. The mean duration of the treated pulses supplied by the flip-flop 853, 85 ^ is therefore half of the "

Mifcr · - period of the supplied reset vibration (ie about 25 i seconds).

The DC voltage at the output (collector) of the Detector transistor 845 is therefore due to the pulse stretching im Flip-flop S53, 8 55 with associated circuits increased or enlarged .

In contrast to a simple interference integrator or a high-gain interference amplifier, the present, Disturbance detector working with pulse stretching between the permanent presence of relatively low-level disturbances, the are greater than the preset interference threshold (a state in which switching to mono reception is desired), and the current one Presence of high-level, short-term vibration trains static interference (a condition that is temporary so that switching to mono reception is undesirable). While that is to say the interference threshold circuit 825, 827, 829 supplies an output signal which has the amplitude characteristic of the demodulated interference contains, the bistable flip-flop 853, 855 normalizes the amplitudes of the supra-threshold interference pulses. The 853 flip-flop, effectively amplifies the short-term impulses compared to the long-term impulses by increasing each of these types of impulses on average the same width determined by the reset frequency of the flip-flop

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853j 8 55 (19 kHz in the present case), stretched, will. The amplitudes of the interference impulses that the flip-flop 8 53,% 55 trigger are not at the output of the flip-flop 853, 855 from each other distinguishable. The normalized output signal of the flip-flop page 73, 8 55 then arrives at a signal integrating arrangement (capacitor 62b) which converts the extended duration of the demodulated pulses into Converts stress amplitudes. The downstream stereo-mono switching arrangement (FIGS. 7 and 9) responds to a relatively high voltage on the capacitor 62b, which indicates the permanent presence of disturbances exceeding the preset disturbance threshold indicates. The short-term presence of disturbances of large amplitude, which exceed the permissible disturbance threshold, calls a comparatively low voltage across the capacitor 62b? her- ^ before, so that the operating mode switchover arrangement is not activated will.

In Figure δ a voltage supply is provided which supplies voltage levels of, for example +6.2 volts and +3 V _R p volts, which are used in other parts of the circuit board 2 2 (for example for the flip-flops according to Figure 2 and 8). Numerous circuit designs can be used for this, and the arrangement shown here is only one possible embodiment.

In the voltage supply circuit shown in FIG. 3, an external B + _T voltage source (of, for example, +8.5 volts) is connected via the connection contact T ₉ to the collector of a first emitter follower transistor802. The emitter of transistor 802 is connected to ground via the series connection of a resistor 804 and a plurality of transistors 806, 808,810 and 812. The transistors 8Ο6 and 8IO are each connected as a diode in that their collector and base are directly connected to one another. The emitters of transistors 8Ο6 and 810 are connected to the bases of transistors 8Ο8 and 812, respectively. The collectors of transistors 806 and 808 are coupled together and connected to the end of resistor 804 remote from the emitter of transistor 802. The collectors of transistors 810 and 812 are tied together and connected to the emitter of transistor 808. The emitter of transistor 812 is grounded. The basis of the

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Transistor 802 is biased by means of a _{voltage divider coupled between terminal contact T 1} "and ground, which also consists of a series connection of a resistor 814, a Zener diode 8l6 (with a nominal zener voltage of 5.5 volts) and the transistors 810 and 812. An amplifier with a low output resistance is connected to the junction of resistor 8U4 and the interconnected collectors of transistors 806 and 80S. The amplifier contains a collector load resistor 8.18, which is between the terminal contact T _iO and the collector of a

1 λ

Transistor 820 is connected, a further transistor 822 whose collector is connected directly to the emitter of transistor 820, an emitter resistor 824 connected between the emitter of transistor 822 and ground, and a feedback branch with one between the collector of transistor 820 Λ and the Base of transistor 822 connected Zener diode 826 and a resistor 828 connected between the base of transistor 822 and ground.

During operation, the transistor 802 is biased into the conductive state by the biasing network with the circuit elements 814, 816, 8IO and 812. The transistors 810 and 812 are conductive and provide a nominal DC voltage of +2 V "_" at the base of the transistor 810 (V _n "is defined as a range of

Kb Kt,

Voltage values that are present at the base-emitter junction of a transistor when this junction conducts). In the present arrangement, transistor 812 conducts more strongly than transistor 810, so that the base-emitter voltage of transistor 812 is actually M somewhat greater than that of transistor 810. However, this difference is insignificant in the present case and is therefore ignored.

As transistor 802 conducts, a voltage drop of V _{RE is} created across its base-emitter junction. The voltage at the emitter of transistor 802 is therefore equal to the sum of the voltage at Zener diode 816 and 1 V (eg approximately +6.2 volts).

The transistors 820 and 822 are also biased into the conductive state, the base of the transistor 820 due to

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the operation of the transistors 8O6, 8O8, 810 and 812 a voltage of + 4V ₁₅₁ -, leads. The emitter of transistor 820 is therefore kept at +3 ν_ _Γ (eg approximately 2 volts) and forms a low-resistance voltage source for the numerous flip-flops on circuit board 22.

FIG. 9 shows an arrangement which indicates the reception of stereo broadcasts suitable for reproduction. The arrangement, which contains a detector for the presence of the pilot signal as well as a circuit for providing automatic stereo switching signals, is particularly suitable for the construction in integrated form and is connected to the stereo amplifier 24 (FIGS. 1 and 5), the flip-flop 328 (FIG. 3 ), the stereo blocking circuit (Figure 7) and the interference perception ^{circuit (FXf 1} Ur 8) in the integrated circuit board 2 2 can be connected.

The pilot signal detector contains a doubly symmetrical synchronous detector with two current source transistors 901 and 90 3. The bases of transistors 901 and 903 are each connected to one of the C4-segment outputs of the stereo amplifier 24 in Figure 5 is connected. The emitters of transistors 901 and 903 are across a resistor 905 and are connected via a resistor 907 or 9Ο9 Dimensions. The collector of transistor 901 is directly connected to the interconnected Emitters of a first pair of switch transistors 91Ij 913 are connected, while the collector of the transistor 903 directly to the interconnected emitters of a second Pair of switch transistors 915? 917 is connected. The bases the transistors 9II and 915 are connected to one of the complementary outputs F, F of the flip-flop 328 in Figure 3 connected, while the bases of the transistors 913 and 917 to the other of the complementary Outputs F, F are connected. The collectors of transistors 9II and 917 are connected to an output terminal Tg while the collectors of transistors 913 and 915 with an output terminal T_ are connected. The filter capacitors 62a and 62b arranged outside the circuit board 22 are between the Connection contacts T_ and Tq on the one hand and ground on the other hand switched. The base-emitter junction of a clamping transistor 921 is connected between the connection contacts T_ and T ^. One

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P>etriebKST> annungsquelle (B +) is directly connected to the collector of the transistor 921 through the resistor 849 (see Figure 8) to the collectors of the transistors 911 and 917 as well as the _row: connection of resistors 923 and 925 to the collectors of Transistors Ql3 and 915 connected. A differential amplifier with transistors 927 and 020 is connected to the connection contacts T_ and Tn. The emitters of transistors 927 and 929 are connected to ground via a common resistor Q.31. The base of the transistor 9-7 is supplied with the output signal generated at the collectors of the transistors 911 and 917, in that this base electrode is connected to the connection contact To. The output signal of the transistor 845 (FIG. 8), which indicates the presence of disturbances, is also fed to the connection clock To. The base of the transistor 9? 9 is connected to the connection point of the divider resistors 923 and 922 and thus receives the output signal generated at the collectors of the transistors 913 and 915. Me V / i resistors 923 and 925 are dimensioned such that the transistor 9'9 is kept in the conductive state in the absence of a differential voltage (ie in the absence of an indication of the presence of a pilot signal) between the connection contacts T_ and To. The collector of the transistor Q29 is connected directly to the operating voltage source (B +), while the collector of the transistor 927 is connected to the operating voltage source (B +) via a load resistor 933. Signals generated at resistor 933 indicating that both a 19 kHz pilot component and no excessive interference are present at the output of amplifier 24 are passed to a level transfer stage having an emitter follower transistor 935, an emitter working resistor 941 and one between resistor 941 and Zener diode 939 connected to the emitter of transistor 935. The collector of transistor 935 is connected to the operating voltage source. The connection point of the resistor 941 and the diode 939 is connected in parallel via resistors 945 and 943 of the same type to the bases of a first transistor 937 in an emitter circuit and a further transistor 947 in an emitter circuit. The collector of the transistor 947 is connected to an operating voltage (+6.2 volts) via a load resistor 971. The signals generated at resistor 971

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are coupled to the stereo blocking input of transistor 741 (FIG. 7) via an emitter follower transistor 973 and a time constant network 97 5. The time constant network 07 5 contains an emitter resistor 977 connected between the emitter of transistor 973 and ground, a relatively large series coupling resistor 979 connected between the emitter of transistor 973 and the base of transistor 741 and the filter capacitor 72 connected between the base of transistor 741 and ground The capacitor 72 arranged outside the circuit board 22 is connected to the circuit board 22 _{via the connection contact T 1 -.}

The second load coupled via the resistor 941 contains the collector of the transistor 937, which is connected to the operating voltage source (B +) via the series connection w of a resistor 949 and a diode 951.

The collector of the transistor 937 is also connected to an emitter follower transistor 955. The transistors 937 and 955 with the associated circuit elements operate as a regenerative switch or "blocking circuit" with two stable states, generally denoted by ^ * f ». For this purpose, the series connection of a Zener diode 9ö3 and an emitter resistor 957 is connected between the emitter of the transistor 955 and ground. An emitter resistor 959 is connected between the emitter of transistor 937 and ground. A diode 961 is connected between the ends of resistors 957 and 959 remote from ground. An output signal is obtained from the transistor 955 by means of a resistor 965 connected between the junction of the resistor 957 and the Zener diode and the output terminal T _{Q of} the circuit board 22. The output signal generated at the connection _{contact T Q} is coupled to the base of a lamp supply transistor 967 in a grounded emitter circuit (outside the circuit plate 22). A pilot signal indicator lamp is connected between the collector of transistor 967 and an external DC power supply sufficient to illuminate lamp 969.

When the pilot signal detector is in operation, the stereo signals

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~ 55 ~

Amplifier 24 the current source transistors 901 and 903 fed push-pull signal mixtures from the stereo amplifier 24 with the help of the switch transistors QHj 917 _S 915 »913 fed complementary 19 kHz square waves F, F synchronously demodulated. If the composite signal contains a continuous 19 kHz pilot component, which indicates the reception of stereo transmissions, then differential DC voltage components are generated by the detector arrangement on capacitors 62a and 62b. The arrangement (especially the phase rings of flip-flop 328) is set up in such a way that, when the oscillator 26 is operating correctly, the resulting DC voltage component on capacitor C2b is more positive than the DC voltage component generated on capacitor 62a. The transistor 927 is therefore made conductive when the pilot signal is present. If the transistor conducts 927, the power line is reduced like the transistors 93 5 and 937 · In the case of decreasing current conduction of transistor 937, the power line increases the transistor 955 · The voltage at the emitter of transistor 955 becomes more positive, and if the sum of the Zener breakdown voltage Diode 963 plus the forward voltage of diode 961 exceeds, a positive voltage is coupled to the emitter of transistor 937, which blocks transistor 937 and keeps it blocked. At the same time, when the emitter voltage of transistor 955 is sufficiently positive, transistor 967 is turned on. The indicator lamp 969 or other display device (for example an electromagnetically deflected iron wing indicator) is therefore energized, so that the reception of a stereo broadcast is indicated to the listener.

Under these conditions (when through the power line of the Transistor 927) also becomes the transistor 947 non-conductive and the transistor 973 conducts · The capacitor 72 starts over the transistor 973 and the resistor 979 to a positive voltage at a predetermined rate. After a predetermined duration of the In stereo reception (e.g. 1 second) the capacitor 72 has reached this point charged that the transistor 741 (Figure 7) is conductive and thereby the duty cycle described in connection with Figure 7 to Activation of the stereo difference signal detector is initiated.

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The delay caused by resistor 979 and capacitor 72 is dimensioned in such a way that ongoing stereo playback, once initiated, is reasonably assured.

If at the output of the stereo amplifier 24 an essentially continuous or permanent 19 kHz pilot signal component not is present, the DC differential component is between the connection contacts To and T_ are not positive enough to to keep transistor 927 conductive, and because of the differential circuit of transistors 927 and 929, transistor 929 tends to direct to it. The resistors 923 and 925 are dimensioned so that the transistor 929 under this condition (i.e. absent a 19 kHz pilot signal) to the conductive state

fe will. When transistor 927 stops conducting, transistor 93 5 conducts and supplies transistor 937 with an input signal which renders that transistor conductive. However, the transistor 937 remains non-conductive until the transistor 935 conducts sufficiently to overcome the reverse voltage coupled from the transistor 955 to the emitter of the transistor 937. When this reverse voltage is overcome and transistor 937 conducts, transistors 955 and 967 are switched off. This will extinguish the stereo indicator light 969. At the same time the transistor 947 } conducts since the transistor 93 5 conducts. The transistor 947 is designed in a grounded emitter circuit, so that it reverses the polarity of the signal fed in and, as a result, the transistor 973 is rendered nonconductive. The capacitor 72 discharges

φ is proportional to that given by the resistors 977 and 979 slow speed, so that after a predetermined time interval during which no pilot signal is perceived, the capacitor 72 has discharged so far that the transistor 741 (Figure 7) is also blocked. Thereupon, the stereo blocking circuit explained in connection with FIG Arrangement switched to mono playback.

It can be seen that the voltage delay caused by the switching on of the transistor 937 and by the discharging of the capacitor 72 conditioned time constant delay the Indicator lamp 969 switched on for a while or the

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Stereo switching transistor 741 remain switched off for a while, after the pilot signal level has dropped below the level initially required for switching to stereo reproduction /. Thereby it is achieved that by short-term loss or failure of the pilot signal the stereo playback is not interrupted.

When a pilot signal sufficient for stereo reproduction is present, but the signal to noise ratio for acceptable stereo reproduction is not enough, the following happens. As explained in connection with Figure 8, an unacceptable signal-to-noise ratio becomes indicated by transistor 845 conducting. When transistor 845 conducts, the voltage at connection contact To (occurs the base of transistor 927) to a relatively low Value. The clamping transistor 921 ensures that the voltage at the terminal contact Tq only drops to a value, the ™ is approximately 1 V '"less than the voltage at the terminal contact T_, so that the correct bias of the pilot signal synchronous detector is not disturbed under these conditions. The transistor 929 is due to its fixed base bias across the resistors 923 and Q2 5 are held conductive and transistor 927 becomes locked. Due to the presence of the pilot signal at the output of the stereo amplifier 24, the voltage not changed at the capacitor Ir. The stereo indicator lamp 969 is therefore turned off and transistor 741 goes on Lock signal fed so that the arrangement on mono playback switches.

We shall now consider certain relationships that exist between different parts of the stereo decoder arrangement to rule.

The stereo decoder with the circuit board 22 and the associated external circuit elements are different Respect set up so that a high performance results in the presence of interfering components in the treated signal mixture and a decision is made against such interference components in favor of the useful signal components. The way in which the stereo works switched off when excessive interference is present

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described in detail in connection with FIGS. 7 , 8 and 9. The signal-to-noise ratio detector arrangement according to FIG. 8 and the additional devices according to FIGS. 7 and 9 for switching between mono and stereo reproduction are also set up in such a way that a distinction is made between actually unacceptable interference conditions and certain acceptable signal conditions which could be misinterpreted as excessive interference .

If, for example, the one supplied by the stereo amplifier 24 A mixed signal contains particularly high-level signals (e.g. repeated drum or cymbal beats in an orchestra performance), such signals can also be accompanied by ultrasonic interfering components, which are the result of overmodulation and the result of this resulting generation of harmonic distortion components arise in the transmitter. It is likely that such harmonic interference components fall within the frequency band to which the Disturbance detector (Figure 8) responds. This disturbance detector is therefore arranged so that it automatically determines the acceptable level of Ultrasonic components (e.g. in the vicinity of 114 kHz) changes and as a result, the continuous stereo reproduction of such high-level signals even in the presence of a relatively high ultrasonic level is retained »A fault detector whose response threshold remains fixed under such signal conditions could be undesirable Way to switch to mono operation.

In Figure 8, the automatic disturbance threshold setting takes place due to the way in which the transistors 801, 803, 807, 809, SU and 813 are designed. And work when normal level or relatively low-level signal mixtures from Stereo amplifier 24 are supplied to the current source transistors 801 and 803, the switch transistors 807, 809, 811 and 813 as a synchronous detector generating an output signal at the resistor 817, which is relatively linearly related to the 114 kHz components of the composite signal. A flows into resistor 817 relatively constant quiescent direct current. In the case of high-amplitude signal mixtures, on the other hand, one of the transistors 80I and 803 becomes controlled in the locked state, while the other this

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Transistors in the highly conductive state is controlled. This is due to the common connection of the emitters of the transistors 801 and 803 to the resistor 805.Under these conditions, a direct current component is generated in the resistor δ 17 that is greater than the normal quiescent direct current component Resistor 817 * and the resulting reference voltage across capacitor 7θ decrease. The level of the demodulated interference components, which is required to exceed the response threshold of the transistors' 820 * 827, increases as a result. It is automatically increased so at high-level signal mixtures of-accept at face t ^J egel of components to 114 kHz.

It can also be said that the disturbance detector is the most desirable Property of a disturbance detector, which at weak signal modul Jj lation is more sensitive to interference than with strong signal modulation.

Due to this self-regulation of the interference detector for high and low level signals and the interference amplitude compression the interference pulse stretcher described in connection with FIG. 8 can have a wider demodulation bandwidth for the interference detector as it would be practical without these features

Typically, (determined essentially by the capacitor 7t ', the resistor 817 and the resistors 821 and 823 * if present) are working in the order of 20 kHz, which gives an acceptable sensitivity to interference in the disturbance detector for manknit a bandwidth. Due to the self-adjustment or self-regulation, the threshold adjustment elements 821, 823 can also be omitted without the tolerances of the other elements of the interference detector being excessively restricted.

Certain other features of the arrangement contribute to a smooth, interference-free stereo reproduction. And that is the 3§ IcHz differential channel subcarrier restored to be substantially free of spurious modulation components found in conventional Circuits to restore the subcarrier occur, through the signals with a bandwidth of at least 1-2 kHz

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ßAD

can walk through.

Typical catfish contain arrangements for doubling the pilot signals a matched 19 kHz band pass circuit, two or more frequency doubler rectifiers and a matched 38 kllz band pass circuit. The 38 kHz subcarrier recovered in such an arrangement is contaminated by AM interference components which, if they are in the audio frequency range or close to it the demodulation cause audible noises in the loudspeakers. Furthermore, the deprecated subcarrier is at a such an arrangement contaminated with FM and PM interference components, which impair the stereo separation of the demodulated audio signals.

Wk While some of the undesired interfering components in the auxiliary

Carrier recovery channel ^{can be eliminated by narrowing the 3} bandwidth of the matched bandpass filters, in practice there is a lower limit to this bandwidth because of the phase sensitivity of a narrowband filter. That is, if the bandwidth of the channel is reduced, the rate of change of the phase error increases as a function of the deviation from the center frequency of the bandpass filter. A relatively small detuning of a narrow-band channel therefore produces a relatively large error in the phase of the restored subcarrier, as a result of which the stereo separation is impaired. Furthermore, narrowband subcarrier recovery circuits generally have an asymmetrical bandpass characteristic, as do the ™. Help carrier phase changes. and results in a loss of stereo separation in the presence of interference. Oscillators that are dragged or synchronized by the input of the separated pilot signal also tend to interfering modulation of their output oscillation, since a signal of considerable strength is required for a sufficiently rigid phase synchronization * The oscillator cannot decouple sufficiently from interfering modulation components of the pilot signal to prevent these components from affecting the output signal phase and amplitude

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In the present arrangement, a 38 kHz switching oscillation or a regenerated subcarrier is generated by frequency division the output oscillation of the oscillator 26 generated, the durci the synchronous AFPR circuit 36 (Figure 6) in a fixed time Relationship to the received pilot signal is maintained. A characteristic of this arrangement of the oscillator 26 and the AFPR circuit 36 is that the oscillator 26 is essentially insensitive against amplitude, phase or frequency modulation of the Pilot signal due to interfering components in the audible spectrum or in its vicinity. The 38 kHz switching subcarrier, which is derived from the output signal of the oscillator 2 6 is obtained, is therefore also free of such undesirable interference coraponents.

This is because of the synchronous 90 -phase relationship between the received pilot signal and that to the AFPR detector 36 " 19 kHz reference switching oscillation supplied, the control output voltage of the detector 36 is essentially free of interference-related Fluctuations in the amplitude of the pilot signal. The phases (as well as the amplitudes) of the output oscillation of the oscillator 26 and the generated 38 kllz switching oscillations are therefore both free from the Effects of such interfering components.

With regard to noise-induced frequency and phase modulation components of the Pilats signal, the bandwidth of the AFPR detector S 36, which is determined by RC filter elements rather than tuned circles, can be made extremely small (on the order of 10-20 Hz) while the feedback loop gain of the APPR circuit is dimensioned so that it is sufficient to bring about and maintain the phase and frequency synchronization of the oscillator 26 Almost completely removed from the AFPR signal by the narrow-band RC filter at the output of the AFPR detector 36. This filtering removes the oscillator 26 (and consequently the 3S kHss switching oscillation generated by the aim ) from the phase and frequency modulation BkoiBpoaunted the pilot signal in presence of interference in reception accompany signal, decoupled; "

1Q98S2 / 11Q0

The scheme, with. Using a narrow-band AFPR detector to synchronize an oscillator and thereby a narrowband? jps Obtaining subcarrier recovery system can also be used in realize another shape. Through a narrow-band subcarrier recovery system reduces the interference in recovered stereo signals when receiving weak signals. A Oscillator with a center frequency of 19 kHz can be used with the 19 kHz synchronous output signal of the phase detector can be automatically phase and frequency controlled, and by frequency doubling The 38 kllz auxiliary carrier for the Synchronous detector of the stereo auxiliary channel can be obtained. In this case the frequency doubler is a frequency converter arrangement, the subcarrier input of the synchronous detector for the stereo auxiliary channel couples to the 19 kHz oscillator, and the input subcarrier of the AFPR synchronous detector is from the 19 kHz oscillator delivered by myself. The term "frequency converter" here denotes either a frequency multiplier or a frequency divider, and the frequency converter may have an output that provides a signal that is out of frequency with respect to the input signal is changed.

While above the invention in its application to a Complete stereo decoder arrangement has been explained, various of the described subunits of the arrangement can be used Can also be used separately or individually. Furthermore, for example, all coils or inductances can be omitted by adding a a different oscillator is used.

Except for the United States patent applications mentioned in the above description the following applications are also mentioned (all filed on 29.12.1969), which the stereo amplifier (Composite signal amplifier), the disturbance perception order or the Matrix amplifier arrangements concern:

U.S. Patent Notice Serial No. 888 391J U.S. patent application serial no. 888 365; U.S. Patent Application Serial No. 888 390.

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Claims (1)

Claims (η decoder for multiplex signal mixtures that contain at least a pilot frequency component and a carrier suppressed modulated Subcarrier component with twice the frequency of the pilot frequency included, marked by cb a controllable oscillator for generating clock signals; a frequency converter arrangement which, under control of the clock signals a first reference oscillation in a predetermined phase relationship thereto and a second reference oscillation "with the double the fundamental frequency of the first reference oscillation generates one Signal coupling arrangement, the signals from a source of the multiplexed signal transmits mixed and whose pass band comprises essentially the entire frequency band of the multiplex signal mixture; f a first synchronous detector coupled to the sifmal coupling arrangement, which responds to the first reference oscillation and the multiplex signal mix and generates a control signal that the phase and indicates frequency deviations between the first reference oscillation and the pilot frequency component and an input of the controllable oscillator is supplied and these in the sense of a minimization of the phase and frequency deviations mentioned regulates; and a second synchronous detector which is coupled to the signal coupling arrangement and is responsive to the second reference oscillation, which generates demodulated components of the multiplex signal mixture that are demodulated synchronously with the frequency of the second reference oscillation. 2. Decoder according to claim 1, characterized in that the first synchronous detector is an amplifier with two outputs, which when a signal is received from the Signal coupling arrangement generates anti-phase signals of the same amplitude, a low pass filter with at least two inputs as well Synchronous switch, each input of the low-pass filter respectively alternately in each half-wave of the first reference oscillation switch one and the other of the two amplifier outputs, ■ "■ - ■ · '■ -" · - ■ - ■■ · i' ~. · <Ϊ́ · « ■ · ■ · -_ ■ '■ contains, such that the control signals are generated. 10 9 ^ 2 M ■ (· Α ■ 3. Decoder according to claim 1 or 2, characterized in that the first synchronous detector contains an arrangement for restricting the hand width of its Auseanfssipnal ^ to the bass frequency range .. 4. Decoder according to one of the preceding claims, d a characterized in that the frequency uni-setter arrangement · a "reouenzverdonplteil for generating the second EezujS "sschwinguni? · -unri a coupling part3. to exceed the Clock signals without frequency conversion for the purpose of generating the first '-rezugschwingunp contains. 5. Decoder according to claim 1, 2 or 3>. characterized, that the frequency converter arrangement has a frequency divider part for generating the first reference oscillation and a coupling part for transmitting the clock signals without i-reauenzumetzung contains for the purpose of generating the second reference oscillation. 0. Decoder according to claim 1, 2 or 3? as a result. indicates that the frequency converter arrangement a first frequency divider for generating the first reference oscillation and a second frequency divider for generating the second Contains reference oscillation. 7. Decoder according to claim L, characterized that the frequency converter arrangement has a third frequency divider for generating a third reference oscillation, their orundant rhyme zcomponent e by 9 ^ compared to the f'rundfrequenzverbindungen the first or the second reference oscillation is shifted, as well as one with the ^ iftnalkopoelanordnung "coupled ^ th third synchronous detector, which on the third Pezugssclvwinp-ung responds and synchronously with the frequency of the reference vibration unit over there generated demodulated components of the signal mixture contains. 8. Decoder according to claim 5, ('- or 7 »characterized in that the frequency converter arrangement has an output which has an over-band reference oscillation with fundamental ^; · ■■■ · ■ - ■ 109852/1100 frec.-uenzkoma ^ nente above the Freoueaxbancles, which by erheblioh star!: en components of the Sisnalfemisch is taken, delivers, as well as an overband synchronous detector coupled to this output contains, which is also coupled to the signal coupling arrangement is- and synchronous with the freruenz of the over-abundant BezurrH-schv.'irumner demodulated over-band accompanying the composite signal Components generated. ⁿ . decoder according to claim 7 and / or 8, rekennzei chnet by a controllable switch arrangement, a receiving mode / display arrangement · and a 'source of a hit voltage, said arrangements being connected in a loop and at least one of the synchronous detectors with except for the first and second? ynchrondetektors display control signals for the controllable switch arrangement provides similar. 10. Decoder according to one of claims 7, S and 9 or according to claim 7 and 3, 'characterized by a controllable arrangement which blocks the second synchronous detector when receiving blocking control signals from at least one of the synchronous detectors with the exception of the first and second Synchronous detector are supplied. 11. decoder according to claim 0 and 10, characterized in that that the synchronous detector, which supplies the lock control signals, an arrangement for restricting the contains marginal width of the lock control signals; that the synchronous detector, ™ which provides the display residual control signals, an arrangement for restricting the bandwidth of the display residual control signals; and that the /nordnun.iT to limit the bandwidth of the lock control signals this limited to a narrower width than the Arrangement · to restrict the bandwidth of the display control signals their bandwidth is limited. 109852/1 100 Blank page