GB1085528A - Improved calculator - Google Patents

Abstract

1,085,528. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 17, 1965 [Aug. 11, 1964], No. 32643/64. Heading G4A. In a calculator, corresponding-order digits of two operands are added in a full-adder, the result being modified or not in accordance with its value and the radix used and then fed back to the adder input via a delay line which together with the adder and modifier forms a calculation loop holding in series the digits of the operands and result. Fig. 2 shows a circuit for multiplying two binary-coded decimal operands A, B, applied serially by bit, to get a result C, by halving and doubling. The sum output of the adder 1 is passed to first and second four-bit shift registers 3, 4 to the latter 4 via a second fulladder 2 which adds the filler digit 6. Halving is done by shifting from the penultimate stage of the first register 3 to get three bits and taking the fourth bit from the carry output of the first adder 1. If the ignored bit in the first register 3 is 1, ten is added into the first adder 1. Doubling is done by applying the digit to both inputs of the first adder 1, the result being passed to the (magnetostrictive) delay line 13 from the first or second register 3, 4 depending on whether the first adder 1 produced a carry. The decimal digit distribution of the operands A, B and result C in the calculation loop is as follows: . . . CBCBCBAAA . . . A (early end) most significant A digit and least significant B and C digits first. A slight modification to perform sequential multiplication A x B = C, C x D = E, &c. is described briefly. Fig. 5 (not shown) shows means for inserting digits from punched cards into the appropriate positions of the calculation loop and printing out digits from the loop. A counter scans a matrix in synchronism with the loop circulation, the matrix gating pulses from the card reader into the loop at the appropriate times for read in, and actuating print drivers when the appropriate digits in the loop agree with digit identifying signals from the card mechanism for print out. Fig. 6 (not shown) shows an embodiment for performing calculations of the form on serial-by-bit signed binary-coded-decimal operands by halving and doubling and successive subtraction and addition. A delay line, with a digit distribution as follows: DB . . . DBDBACAC . . . AC (early end) least significant digits first, feeds a series combination of a first four bit shift register, a first adder/subtracter, a second register and a second adder/subtracter, the latter feeding the delay line. Provision is made for carry to/ borrow from the next decimal digit, and for addition of filler digit when there is a carry from the first adder or when a carry would be generated from the 8-bit of the first adder output by addition of the filler.