DE1296425B - Computing arrangement for performing the four basic arithmetic operations - Google Patents

Description

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The invention relates to a computing device. However, the arrangement has the disadvantage tion for carrying out the four basic arithmetic operations that for carrying out the relevant arithmetic scheme

functions according to the scheme Al *. + _D by ^a re f Richer effort to control means and numerous

C rich time-consuming value transfers between the fetched operand halving, doubling, addition of 5 different registers are necessary, and subtraction, with the respective basic operation The arithmetic operands of the arithmetic scheme are set to be realized with unit by the fact that, under the effect of digit-by-digit serial processing of the operands that are either strictly a control unit, the fixed arithmetic binary or binary-decimally encrypted operands. i ₀ . /, ^ d ₄ .. , j «· ■.

The German Auslegeschrift 1 101 818 describes ^schema < ^fl ± ® T ^{using the ρ} » ^ηζ Φ * der

a calculating machine for calculating an amount of continued addition and subtraction is running. the

A pressure ^ _7, wherein the divisor C at least desired elementary arithmetic is adjusted by zero-C ° or EMS setting certain operand,

is half the size of the dividend B, but it is after 15 This computing unit is not possible method of halving and doubling works bills in different monetary systems, and in which the multiplication and division at the same as £ and DM to perform (German In the case of this known calculating machine 1 190 705).

is a device for forming the difference between two It is also known in calculating machines that work with a value with addition or subtraction, a mechanically rotating memory for operand doubling, a halving device for storing the operands and and a device for introducing the result the result of an arithmetic operation on a communal halving device in a result memory, the revolving track digit-by-digit, if the result of the above-mentioned difference device is to be stored (German patent 1 074 890). It is intended to be positive. These devices 25 are supposed to avoid the need for separate operands so that in each of several up and result registers as well as controllable transfer successive arithmetic operations the first path between the registers is avoided of the dividend B or the doubled remainder for the optional execution of all four basic values of the preceding difference forms the arithmetic operations.

doubling device doubles the residual value and the object of the present invention is to provide the halving device the multiplier A to provide a computing arrangement with which it can be halved. This process is implemented in that the control and time expenditure for the execution of four parallel-connected multiple shift arithmetic operations based on the step register principle are provided, of which three would have to be used for halving and doubling operands . B, C and the fourth serve as a reduce and, according to this principle, not only serve as multi-intermediate registers. After storing the plications and divisions, but also additions of operands, an operation begins by checking and performing subtractions to determine whether the content of the divisor register is less than half the maximum capacity of this register. 40 solved that the digits of the operands in the sequence C ₀ , If this condition is met, a ^ ₀ , C ₁ , A ₁ , C ₂ , A ₂ ... C _n , A _n , B ₀ , D ₀ , B ₁ , D ₁ ... B _n , D _{n are} equal to the content of the divisor register with which are stored in a serial memory and reß registers. Thereupon the previously fetched begins in a through the serial memory and an explained arithmetic process, within which the added adding - subtracting - device formed main additions and subtractions circulate through a loop that one from the output to the entries between the registers are carried out The auxiliary loop originally containing the operand B is provided; the run-time register is used as the result register. delay in the size of a digit time that doubles the divisor remainder is a return loop with the same sign of A and C both inputs, which is assigned to the divisor register 50 of the adding-subtracting device to the C _x - and and in a doubler circuit is located. ß _s digit times for the purpose of doubling the operand A is halved by switching C _x and B _x into the main loop and a similar feedback loop in which there is a halving circuit after each doubling of the subsequent A _x. Transmission paths are provided between the individual or D ^ digit times of the one input of the registers, the adding / subtracting device for the purpose of BiI-over gate circuits from a control circuit selection of A _x - C _x or D _x + B _x can be brought into effect in the auxiliary loop. it is switched that if the signs of

This calculating machine has the advantage that A and C, at the C _x and β _x digit times, have a binary position shift implication and "division" in the relatively complicated arithmetic operations "multi-main loop" in the simpler arithmetic direction for the purpose of halving of C _x and B _x operations "addition" and "subtraction" and is made effective and after each halving back to the operations of doubling and halving, which are very simple in the binary system, to the following A _x or £> _{X digit times} - The one input of the adding-subtracting device can be performed. Another advantage of this calculating machine, known for the purpose of forming A _x + C _x or D _x - B _x , is that 65 is switched to the auxiliary loop and that the sequence of arithmetic operations in number systems runs different times in the main loop until A and / or B have become the radix, for example the pound sterling zero, so that the result is available as the D- value available at that time.

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As a result of the continuous circulation of the operand adding-subtracting circuit 58, half of the base and intermediate results in the main loop and through R / 2 are added to the digit,
the reduction of the transfer operations between the different parts of the serial memory currently running through the shift register 52 should not be halved to the digit, this is from which a minimum comes the arithmetic unit according to the last 5 stage of the shift register 52 via an AND invention despite the Complicated calculation scheme, circuit 53 is fed to one input of the adding sub after which it operates, with a relatively tracing circuit 58. The AND circuit, which requires little control means and time 53, is opened by the signal H ,
the end. The additions and subtractions are in the

Various advantageous developments of the Erio adding-subtracting circuit 54 carried out, the invention are described in the subclaims. optionally to be set to addition and subtraction. The following is an exemplary embodiment of the invention. While the digit of one operand (e.g. A) is supplied to the adder-subtracter circuit 54 via the shift register 50, explained in more detail with reference to the drawing, the corresponding In is passed to the arithmetic 15 digit of the shown in the drawing second operands (eg C) via an arrangement, the four operands, A, B, C and D, sub-loop from the output of the add-subtract constantly circulate in a loop. This loop is circuit 58 and a first slide (54el) of the adding-subtracting circuit 54. The verb register 50, a first adding-subtracting circuit 20 delay of the sub-loop corresponds to a 54, a second shift register 52 and a second digit time. Formed by an AND circuit 59 and an add-subtract circuit 58. As in the delay element 64, a transmission loop of the delay line 56 is indicated, the digits are formed which transmit the transfer from one bit position to the next digit of the operands C and A and B and D.

wisely nested. C and A run ahead, 25 The sum is correct if there is no carry before B and D. The lowest digit of the hand is, otherwise a correction digit F must precede each operand. In the execution (with decimal numbers 6) are added. The sum example is assumed that the operands are represented as and the correction digit F are represented as a Uber-binary-coded decimal number. Carrying circuit 60, which represents a carry signal Therefore, the delay line 56, generated by 30, when viewed from the 8-bit of the tetrad in the left to right, the first C is the ones digit, the addition with the correction digit F or from the second C. the tens etc. of the operand C, 8-bit of the tetrad in the adding-subtracting circuit the first A is the ones digit, the second A is the tens - a carry is generated. The carries from the digit etc. of the operand A represent. The decimal carry circuit 60 are in the bits representing the adjustment with the values 1, 2, 4 35 delay element 55 and the AND circuit 57 and 8 are also like this ordered that in each case the formed delay loop, which leads by one bit time 1-bit. delayed, back to the receipt of the transfer

The basic algorithm 60 used according to the invention is carried out.

mus is: double B and C, if A and C have the same that carry one decimal place of signs, then carry out the output signal of the carry circuit 60 => A and D + B = > D showing operation AC 40 . If, on the other hand, it is in a delay element 62 to have a sign different sign, halve B and C with a time delay and via an AND circuit 61 and instead of doubling and form A + C => A the delay element 64 simultaneously with the low and DB => D and repeat until the A first bit of the next higher decimal digit becomes the one or B zero. The exact result is equal to the D 45 output of the adding-subtracting circuit 54, and is obtained when A becomes zero and an un- The output signal of the carry circuit 60 when B is zero, but not A. also reaches after passing through of delayS;

To double the number (B or C) the member 62 becomes an AND circuit 63, which sends the signal H to an input (54 e 2) of the add-subtract switch and the bits of the correction number F (in the case of decimation 54 direct and the second input (54el) via 50 numbers six) are fed. The correction is carried out by an AND circuit 51, which is generated by a signal D ge in the adding-subtracting circuit 58 in that it opens, from the output of the shift register 50 to the result fed to the adding-subtracting circuit 54 the correction number is added. In order to halve the data in the shift loop formed by the AND circuit 65 and the ver register 52, they are shifted to the right by 1 bit, 55 delay element 67 so that they are carried from the penultimate stage via the AND circuits from one bit position to the next device 66. This is transferred in a controlled manner.

in that an AND circuit 66 is opened by a Si The output signals of the add-subtract signal H. To get the correct halved number (58) into delay line 56, an addition of half of base 60 must be given.

to the digit (five in the case of decimal numbers) In operation, this means that in a certain time, if the next higher decimal digit is an odd point, a digit of the number C or B in register 52. The lowest non-zero bit of this and the corresponding digit from the number A or D, the next higher digit of the same operand, will be in register 50. The digit of the number C or A in register 50 at the same time that the first ⁶ 5 is doubled or halved by the adder sub-digit leaves register 52. This bit runs via tracer 58, from where it is sent via the AND circuit 68 and opens the AND circuit delay line 56 as well as via a gate circuit 70 together with the control signal H, so that the device 72 runs to with the digit of the number A or D,

output from the shift register 50 to be combined. One digit time later, the new digit of number A or D in register 52 will be ready for the correction operation, and another digit of number C or B will be in shift register 50.

The signs of the numbers A and C are indicated by a nine or a zero in the most significant place and must be checked with each cycle. One flip-flop (not shown) stores the previous sign and another flip-flop stores the changes in the sign of the number A, both controlling the change between halving and doubling as mentioned above.

The circuit according to the invention can also be used to process operands in a different number representation, e.g. B. in purely binary representation, can be used. In this case, the bits in the delay line can be nested directly into one another. There is no correction by adding a number F , and only the transfers from bit to bit have to be taken into account.

If a different radix is to be used in a number system, different values must be used for the correction number F and the correction value R / 2 when halving.

Claims (9)

Patent claims: 1. Computing arrangement for performing the four basic arithmetic operations according to the scheme -Ρ 1- D by repeated halving, doubling, adding and subtracting operands, whereby the respective basic operation is set by setting certain operands of the calculation scheme to zero or one, with digit-by-digit serial processing of either purely binary or binary-decimally encrypted operands, thereby characterized that the digits of the operands in the sequence C ₀ , A ₀ , C ₁ , A ₁ , C ₂ , A ₂ ... C _n , A _n , B ₀ , D ₀ , B ₁ , D ₁ ... B _n , D _n are stored in a series memory (56) and repeatedly circulate in a main loop formed by the series memory and an adder-subtracter (54, 58) that one from the output (SSa) to the input (54el) of the adder -Subtracting device leading auxiliary loop is provided, which has a delay in the size of a digit time that with the same sign of A and C, both inputs (54 el, 54 el) of the adding-subtracting device to the C _x - and Z? _x digit times for the purpose of doubling C _x and B _{x are switched} into the main loop and after each doubling for the subsequent A _x or D _x digit time each input (54el) of the adding-subtracting device for the purpose of formation from A _x -C _x or D _x + B _{x is switched} into the auxiliary loop, so that if A and C to the C _x and B _{x digit times are not the} same, a binary position shifter (52, 66) located in the main loop is used for the purpose the halving of C _x and B _{x is made} effective and after each halving for the subsequent A _x or D _x digit time, the one input (54el) of the adding-subtracting device for the purpose of forming A _x + C _x or D _x - B _{x is switched} into the auxiliary loop and that the sequence runs so often in the main loop until A and / or B have become zero, so that the result is available as the D value present at that time. 2. Computing arrangement according to claim 1, characterized in that the series memory (56) ats Run time memory is formed. 3. Computing arrangement according to claim 1 and 2, characterized in that the position shifting device from an additional tap (66) of the penultimate stage one connected in the loop Shift register (52) consists. 4. Computing arrangement according to claims 1 to 3, characterized in that the adding-subtracting device consists of two adding-subtracting works (54, 58) arranged one behind the other in the loop, of which the in relation on the first used for operand doubling, addition and subtraction and the second to correct the results when the odd operand digits are halved Addition of half the base to the next lower operand digit and to correct the result digits when using an unused binary group encryption (pseudotetrads) by adding a correction value (6 for binary decimal encrypted values). 5. Computing arrangement according to claims 1 to 4, characterized in that a gate circuit (70) is provided, which is supplied with half the base value of the number system used and the lowest bit of an operand to be halved for the transmission of the half the base value for the second adding-subtracting work (58) is controllable. 6. Computing arrangement according to claim 5, characterized in that the tapping of the lowest bit of an operand to be halved takes place at the input of a shift register (50) which is used to receive an operand digit (A _x , B _x , C _x or D _x ) and the first adder-subtracter (54) is connected upstream in the loop. 7. Computing arrangement according to Claims 1 to 6, characterized in that a transfer checking circuit (60) is provided, which is the pseudotetrad correction value on a trial basis to the result digits of the first add-subtract work added and with a one in the most significant bit of the result tetrade a control signal with the corresponding Delay to an AND circuit (63) supplies, which thereby for a transmission of the Pseudotetrad correction value is opened to the second adder. 8. Computing arrangement according to claim 7, characterized in that the carry check circuit (60) with a shift register (52) is connected in parallel to the output of the first adder-subtracter (54) and that this shift register for receiving an operand number (A _x , B _x , C _x or D _x ) is used and the second adder-subtracter (58) is connected upstream in the loop. 9. Computing arrangement according to claims 1 to 8, characterized in that the transit time memory (56) is a magnetostrictive delay line. 1 sheet of drawings