FR2656754A1 - System for coding digital signals which are intended to be transmitted and/or stored - Google Patents

Abstract

System for coding digital signals which are arranged in information blocks, comprising a source coder followed by a transmission channel coder, and noteworthy in that, in the case in which the source coder is a variable-length coding chain (10) particularly comprising a flow-rate regulation circuit, the channel coder comprises: (A) a block-length coding stage (100), provided for defining, along a block, an accumulated length of codewords output by the said source coder, and for carrying out coding of the block lengths thus determined; (B) a stage (200) for selective protection of the said information blocks; (C) a stage (300) for multiplexing the signals output by the said length coding and selective protection stages. Application: television signal coding.

Description

"DIGITAL SIGNAL CODING SYSTEM FOR USE
TRANSMITTED AND / OR STORED '
The present invention relates to a system for coding digital signals arranged in information blocks, said system comprising a source coder followed by a transmission channel coder.

 The digitization of television signals means that a very large amount of binary information has to be transmitted with a speed of the order of 220 Mbits / second. Such a bit rate cannot be ensured at a reasonable cost by the existing transmission channels, and various techniques for coding information have been proposed in order to reduce the quantity of information and therefore the bit rate. Such an objective is achieved in fact by reducing the redundancy of information, but, then, each of the information transmitted becomes essential. Possible transmission errors, which can be fairly easily corrected if the information to be transmitted is redundant, have increasingly serious consequences when this redundancy is reduced. Indeed, the extent of the defects due to transmission errors unfortunately increases more faster than the flow reduction factor.

In the presence of a transmission channel providing noise, it has therefore been sought to protect against these transmission errors or to reduce the effects thereof. One of the techniques thus proposed consists, for the coding of information, in associating with a coding reducing the bit rate (also called source coding) an error correcting coding (also called channel coding) making it possible to selectively protect the information most susceptible to transmission errors. A coding method and system ensuring such protection are for example described in the State patent
United States of America No. 04555.729.

 The recent use, in source coders, of variable length codes which further improve the performance of these coders, leads to a further reduction in the redundancy of information. As a result, said information is even more vulnerable to transmission errors. On the other hand, variable length coding leads to allocating to blocks of information of the same dimensions a number of bits variable as a function of the information contained in each of the blocks. In this case, the presence of transmission errors can cause the correct segmentation of the coding words corresponding to a block to be lost, or even cause synchronization between blocks to be lost, which leads to the appearance of false patterns as well as spatial shifts in the image.

 These faults are difficult to correct with current error correction techniques, since, with variable length coding, the positions of the important information in the binary sequence are not known. An error on the most significant bits of the DC component, for example, is much more perceptible than an error on the last bits of an information block. However, due to the variable lengths of the coding sequences (or words), current techniques prove to be powerless to correct this type of error in an appropriate manner.

 An object of the invention is to propose a system for coding digital signals remedying the above-mentioned faults when it is desired to selectively protect information which has previously undergone variable length coding.

To this end, the invention relates to a coding system characterized in that, in the case where the source coder is a variable length coding chain comprising in particular a rate regulation circuit, the channel coder comprises:
(A) a block length coding stage, provided for determining a cumulative length of code words along a block originating from said source coder and ensuring the coding of the block lengths thus determined
(B) a stage of selective protection of said information blocks
(C) a stage for multiplexing the signals originating from said length coding and selective protection stages.

 The structure thus proposed provides an effective solution to the problems mentioned. Indeed, on the one hand a good synchronization between blocks is restored, even for fairly critical error rates, on the other hand the length of the correcting code words is adaptable to the length of the blocks, the added redundancy being variable thanks the presence of flow control means. Furthermore, these good performances are obtained with a structure complexity which remains very reasonable, all the more so since a single regulation subset can be adopted for the source coder and the channel coder.

The features and advantages of the invention will now appear more precisely in the description which follows and in the appended drawings, given by way of nonlimiting examples and in which
- Figure 1 is a block diagram showing, in a digital signal transmission chain, the source encoder / channel encoder and channel decoder / source decoder combinations
- Figure 2 shows the essential circuits of the coding system according to the invention
FIGS. 3 and 4 respectively show an example of an embodiment of the length coding stage and of the selective protection stage of the coding system of FIG. 2.

 As seen above, a known technique for protection against transmission errors consists in associating with a source coder a channel coder. This technique is shown diagrammatically in FIG. 1 which comprises on the one hand a source encoder 1 and, between it and a transmission channel 3, a channel encoder 2. Symmetrically, there is at the output of channel 3 a channel 4 decoder then a source 5 decoder. In the present description, we will exclusively consider all that concerns the coding assembly situated upstream of channel 3, that is to say the assembly constituted by the coder source 1 and channel encoder 2.

 The coding system according to the invention is shown in FIG. 2 and comprises the following elements, namely a variable length coding chain 10, which constitutes the source coder, and a channel coder 20, here comprising a stage 100 for coding the cumulative lengths of the code words of a block (the description will be made more concise by speaking of block lengths) originating from the coding chain 10, a stage 200 of selective protection of the information blocks originating from the chain coding 10, and a stage 300 for multiplexing the signals from said stages 100 and 200 for coding lengths and selective protection.

 It will be specified that here, by information blocks, we mean subsets of signals of the same dimensions, resulting from a subdivision of the batches of information (for example images in the case of television) initially considered and of which we wants to ensure coding then transmission and / or storage. It will also be recalled that a variable length coding chain essentially comprises, conventionally, an orthogonal transformation and quantization circuit, a variable length coding circuit, and a rate regulation circuit including a buffer memory. In addition, the information blocks undergoing said orthogonal transformation can, by operations of comparison with thresholds, be classified according to their greater or lesser activity (linked to the contours, to the contrasts, to the greater or lesser uniformity of the blocks), and a signal C expressing this classification is then emitted by the orthogonal transformation and quantization circuit, and transmitted.

Likewise, the flow regulation circuit comprises a feedback loop carrying a normalization signal N, and this signal N must also be transmitted. Signals C and N will in fact be useful, on the reception side, for carrying out the operations opposite to those provided for transmission, with a view to the reconstruction of the blocks and the reconstitution of lots of information similar to the initial information lots.

 The block length coding stage 100 is shown in FIG. 3 in a particular embodiment. This stage 100 firstly comprises a bit counting circuit 101 and a block counting circuit 102.

The number of bits corresponding to a block is counted by the circuit 101, while an EOB signal at the end of the block is supplied by the orthogonal transformation and quantification circuit of the chain 10 to the block counting circuit 102 whose content increases of a unit at each signal reception
EOB. The block length determined by the circuit 101 is then stored in a memory 103, and the counting circuit 101, reset to zero by command of the signal EOB (connection RS1), is available for a new block length counting.

In the embodiment described, it is also the signal EOB which controls the writing into memory 103 (connection WR).

A decision circuit 104 determines, here by comparison with a prerecorded number, from which number of blocks - and therefore of determined lengths - the memory 103 can be read. This circuit 104, which is here a comparator, is placed at the output of the block counting circuit 102 and delivers (connection RD) a command to read memory 103 when the content of circuit 102 (the number of blocks whose lengths have been determined) is equal to the pre-recorded number. This read command signal is also sent back to circuit 102 to reset it (connection
RS2). In the embodiment described here, the pre-recorded number is equal to 4, and the memory 103 therefore reads when four lengths have been determined and successively memorized. The circuits 101 and 103 therefore constitute, in stage 100, an example of means for determining the length of each block after variable length coding, and circuits 102 and 104 an example of means for counting the number of blocks whose length has been determined.

 The four block lengths, which here represent a maximum of 40 bits of information when the bit counting circuit 101 is a 10 bit counter, are supplied in sequence to an encoding circuit 105. In the embodiment described, this circuit 105 is a systematic linear binary coder, known as a "block *" coder, chosen for its ability to correct y errors for x information received. In the present case, the number x of bits received supplied by the memory 103 to the coding circuit 105 is, on saw it, at most equal to 40, and the maximum number of errors that we want to correct for such a number of information received is equal to 2. The binary code then chosen is noted C (52, 40) , 40 representing said maximum number of bits received and the remaining 12 bits being parity bits. The output of coding circuit 105 constitutes that of stage 100 for coding block lengths.

The stage 200 for selective protection of the information blocks is shown in FIG. 4 in a particular embodiment. This stage 200 here comprises first of all a memory 201 constituting a circuit for classifying bits according to the sensitivity of the latter to errors caused by the transmission channel. For code words resulting, as here, from variable length coding, this sensitivity is determined from prior statistical analyzes, the results of which are grouped in a table associated with the memory 201. The bits delivered by the string 10 variable length coding are stored in the memory 201 and then re-read according to a sequence of addresses contained in the table, with a view to reordering these bits (generally in decreasing sensitivity order) before they these are only supplied to a selective coding circuit according to said classification. In the embodiment described here, this selective coding circuit is an encoder 202 called Blokh
Zyablov, chosen for its ability to allow several levels of coding according to the classification of bits previously carried out.

In all cases, this coder 202 is capable of coding at most K bits. If the length L of an information block is less than this coding capacity K, the unused (KL) bits give rise to zeroing in the information chain of length K processed by the coder
Blokh-Zyablov 202. If on the contrary the length L is greater than the capacity K, only K bits are coded. The remaining (LK) bits are not coded and are subsequently multiplexed with the code words delivered by the coder
Blokh-Zyablov, in multiplexing stage 300.

 In the present case, it has been chosen for example to have four coding levels, that is to say selective protection at four levels. The coding method implemented in the coder 202 is as follows.

ce qui donne
(................. ligne 1 ...........0)
C = GtM = ( m2. ...) (....... k2.........)
( m3....) ( k3 )
(..... m4....) ( k4
Comme on le constate, du fait de la structure de la matrice G qui ne diffère de la matrice unité que par le contenu de sa première colonne, le mot de code produit par bloc (constitué par la succession C1 à C4 des quatre lignes de la matrice C ci-dessus) est quasi-systématique puisque la multiplication matricielle effectuée a conduit, pour la ligne 1 non portée en détail par souci de simplification, à une combinaison linéaire de bits masquant une partie des bits initiaux et réalisant donc une perte de ces bits d'information. Cependant, on retrouve quand même une partie des bits d'information dans les lignes suivantes, ce qui facilite le processus de raccourcissement.Le codeur Blokh-Zyablov 202 est en effet suivi d'un circuit de raccourcissement 203, qui permet de supprimer éventuellement les (K-L) bits mis à zéro, et la sortie de ce circuit 203, qui constitue celle de l'étage 200, est envoyée vers l'étage de multiplexage 300.Let ki (with i = 1 to 4) be the number of bits for each of the four coding levels used here, in the case of a block of length K, these numbers k1, k2, k3, k4 therefore being associated respectively with each of the four levels. We then add to each of the ki bits a corresponding number mi of parity bits linked precisely to the degree of protection sought for each level. In the example described here, we have chosen m1 = 14, m2 = 2, m3 = 2, m4 = 1, the choice of the pairs (mi, ki) having to allow the arrangement of the code words thus constituted in a memory with I lines and J columns (with
I = imax = 4 and J = n / I columns, n being an integer close to the average length of the blocks) with a disposition which is therefore the following, by calling M the matrix (I, J) corresponding to the content of this memory
(..... m1 ...) (.......... k1 .........) (..... m2 ...) (..... ..... k2 ........)
M = (.... m3 ...) (.............. k3 ...............) (... m4. ..) (............. k4 ............)
For the coder described here, at four levels of protection, the four code words are then obtained by multiplying by this matrix M the transpose Gt of the following matrix G

Which give
(................. line 1 ........... 0)
C = GtM = (m2. ...) (....... k2 .........)
(m3 ....) (k3)
(..... m4 ....) (k4
As we can see, because of the structure of the matrix G which differs from the unit matrix only by the content of its first column, the code word produced by block (constituted by the succession C1 to C4 of the four lines of the matrix C above) is almost systematic since the matrix multiplication carried out has led, for line 1 not carried in detail for the sake of simplification, to a linear combination of bits masking part of the initial bits and therefore achieving a loss of these bits of information. However, there are still some of the information bits in the following lines, which facilitates the shortening process. The Blokh-Zyablov 202 encoder is in fact followed by a shortening circuit 203, which makes it possible to possibly suppress the (KL) bits set to zero, and the output of this circuit 203, which constitutes that of stage 200, is sent to the multiplexing stage 300.

 In the case where the block lengths are less than or equal to the coding capacity K, all the bits received by the coder 202 are coded. When, on the contrary, these lengths are greater than K, the stage 300 ensures the multiplexing not only of the signals originating from the length coding and selective protection stages, but also from the excess (LK) bits which could not be coded by the encoder 202. The multiplexing is carried out, in one or the other case, by a multiplexer 301, and the latter is followed by a buffer memory 302 provided for regulating the bit rate of the output signals of the system coding, that is to say here the output signals from the multiplexer 301. Of course, it is possible to combine the flow regulation means of the present coding system and the flow regulation circuit of the chain 10 of variable length coding in a single flow control subset.

Claims (11)

1. Coding system for digital signals arranged in information blocks, said system comprising a source coder followed by a transmission channel coder, characterized in that, in the case where the source coder is a coding chain variable length including a flow control circuit, the channel encoder includes  (A) a block length coding stage 1 provided for determining along a block a cumulative length of code words originating from said source coder and ensuring the coding of the block lengths thus determined  (B) a stage of selective protection of said information blocks  (C) a stage for multiplexing the signals originating from said length coding and selective protection stages. 2. Coding system according to claim 1, characterized in that the length coding stage comprises  (A) means for determining the length of each block of information after variable length coding, themselves comprising  (a) a bit counting circuit, designed to receive the variable length coded signals delivered by the source coder in association with each block and to count the number of bits of such signals for each block  (b) a memory for storing the output of said bit counting circuit  (B) means for counting the number of blocks whose length has been determined, themselves comprising  (c) a block counting circuit, designed to receive end of block signals also supplied by said source encoder  (d) a decision circuit, provided for controlling the reading of the memory as a function of the output signal of said block counting circuit  (C) length coding means, themselves comprising  (e) a coding circuit, provided for delivering the coding words for the lengths of said information blocks. 3. Coding system according to claim 2, characterized in that  (A) the decision circuit is a comparator of the number of blocks whose length is determined to a prerecorded number  (B) the coding circuit is a systematic linear binary coder. 4. Coding system according to claim 3, characterized in that the bit counting circuit is a 10 bit counter, and in that the prerecorded number is equal to 4. 5. Coding system according to claim 4, characterized in that the systematic linear binary coder is a C coder (52.40), with code words of 40 bits maximum and 12 bits of parity. 6. Coding system according to one of claims 1 to 5, characterized in that the stage for selective protection of information blocks comprises  (A) means for classifying bits according to their sensitivity to transmission errors  (B) means of selective coding according to said classification  (C) means for shortening the code words resulting from said selective coding. 7. Coding system according to claim 6, characterized in that  (A) the means for classifying bits according to their sensitivity to transmission errors comprise  (a) a memory, designed to receive, in a first memory area, the variable length coded signals from the source encoder and, in a second memory area, for addressing said first memory area, the rank said coded signals, and delivering said coded signals in a modified order according to said addressing  (B) the means of selective coding according to said classification include  (b) a so-called Blokh-Zyablov coder  (C) the means for shortening the selective coding words comprise means for deleting bits. 8. Coding system according to claim 7, characterized in that, when the length L of the block considered is less than or equal to the coding capacity K of said selective protection stage, the multiplexing stage comprises  (A) means for multiplexing the output signals of said block length coding stage and said selective block protection stage  (B) means for regulating the rate of the output signals of said multiplexing means and in that, when said length L is greater than K, said multiplexing means are provided to also ensure the multiplexing of said L-K non-coded bits. 9. Coding system according to claim 8, characterized in that the Blokh-Zyablov coder has four levels of selective protection and comprises a matrix memory with four lines and n / 4 columns, n being an integer close to the average length. information blocks from the source encoder. 10. Coding system according to one of claims 8 and 9, characterized in that the rate control means comprise a buffer memory intended to deliver on the one hand rate control signals sent back to the channel encoder and on the other hand, the output signals from said coding system. 11. Coding system according to one of claims 8 to 10, characterized in that said flow regulation means and the flow regulation circuit of the variable length coding chain are grouped into a single flow regulation subset .