FR2642252A1 - Circuit interconnection unit, especially of the crossbar type, process for employing a circuit interconnection unit and uses of a circuit interconnection unit - Google Patents

Abstract

The field of the invention is that of circuit interconnection devices, especially devices of the crossbar type used more specifically in parallel-processing electronic machines. An essential objective of the invention is to provide a circuit interconnection unit allowing relatively short times for configuring the latter. This objective is achieved with the aid of a unit 1 for interconnecting circuits 1001, 1002, 1003 of the type comprising a plurality of transmitter 2e and/or receiver 2r communication channels which cross at channel connection points P and which effect the connections between the said circuits linked to at least one channel, a plurality of means 11, 12 switching and monitoring the state of the connection points, which unit is characterised in that the control of the means 11, 12 for switching and monitoring the state of the said connection points P is shared between the circuits 1001, 1002, 1003 which access the said connection points P via a channel 2e, the means 11, 12 for switching and monitoring the state of a connection point P being at least linked to the circuits for accessing the said connection points via at least the said channel.

Description

 "Interconnection unit between circuits, including the crossbar type, a method of implementation of a circuit interconnection unit, and uses a circuit interconnection unit.

 The invention relates to an inter-circuit interconnection unit of the type comprising a plurality of transmitting and / or receiving communication channels crossing at channel connection points and making connections between said circuits connected to at least one channel, an plurality of switching means and control of the state of the connection points.

 The field of the invention is more specifically that of crossbars, which are frequently used in multiprocessor structures, to interconnect them to each other or to memory resources, and more traditionally in telecommunication central offices. Crossbars, in general, can be defined as square mesh grid circuit interconnection networks.

 Interconnection networks linking several processors together or connecting processors and memories, in the case of parallel processing machines, have been the subject of much work. A known traditional solution is based on the principle of bus communication. However this solution offers only limited communication rates because the different circuits must share the same channel to communicate.

Other solutions have been proposed that use different principles of known interconnection networks, among them the structures of the crossbar type. The crossbar makes it possible to obtain a simultaneous point-to-point connection between many circuits
In general, crossbars are used in multiprocessor systems, said processors sharing a common memory resource (high torque system) or in multiprocessor systems only (weak coupling). In these crossbars, composed of a plurality of communication channels crossing at a connection point and physically connecting at least two circuits of the processor, memory or other type, the connection is in a known manner performed by a switch that the it is represented by an AND logic gate 11.The state of the connection at the connection point and therefore the state of the switch or not is commonly determined by the state of a logic latch 12 connected to the logic gate. AND 11 and associated with each intersection of channels or connection point as visible in Figure 1. Of course the AND gate can be realized in a conventional manner using other types of doors.

 The configuration of the interconnection circuit consists in assigning to each of the logical latches 12 associated with the connection points a specific connection state (whether or not it passes) and consequently a reconfiguration of the interconnection circuit consists in modifying all or part of the initial state of said logic latches associated with the connection points of the interconnection circuit.

 The crossbar structure has the advantage of being extensible, in particular it can be made from a plurality of crossbar components Ci as shown in FIG. 2.

 Several types of crossbar structure are known. According to FIG. 3, a first solution consists of a plurality of vertical transmitter channels, with unidirectional communication, connecting circuits 15 via horizontal emitter channels with unidirectional communication as well.

The use of the crossbar in general requires its configuration or reconfiguration that is to say the establishment of a specific state of the different flip-flops 12 associated with the connection point of the crossbar. In this simplest design of the crossbar as shown in Figure 3, the reconfiguration thereof is done in a serial manner. A reconfiguration circuit 14 outside the crossbar successively addresses all the flip-flops associated with the connection point of the crossbar via a set of decoders 13, so as to position said flip-flops connections in the desired state.

 A second crossbars solution, according to FIG. 4, consists of a plurality of vertical parallel transmitter-receiver channels connected to circuits 15 and crossing pairs of horizontally communicating horizontal connection channels. Again, the management and control of the intersections of channels is performed by a control processor 14 outside the crossbar and processing the information received sequentially.

 A particular constraint of the use of such known crossbars devices concerns in particular their configuration delays, this delay being decisive for the efficient use of parallel processing machines built around such structures. In particular, a major drawback of known crossbars operating with a reconfiguration device such as those described above lies in the fact that the total reconfiguration delay of the crossbar is important compared to the cycle time scale of a processor connected to it. last, or compared to serial transmission delays.

 For current systems based on crossbars, it is recommended to carry out static reconfigurations (at the beginning of the operation) or semidynamics at the reconfiguration points determined by the algorithm used (JG HARP, "Phase 2 of the reconfigurable transputer project'l, in "esprit'87, achievements on impact'l, North Irland, 1987). Estimatively, we can estimate the global reconfiguration time of a 100 x 100 (100 entries per 100 outputs) crossbar to about one millisecond, which would correspond to a reconfiguration delay of a flip-flop in the order of 10 This estimated time of reconfiguration of the crossbar prevents any dynamic reconfiguration thereof, that is to say with very short time intervals between two global reconfigurations.

 Another disadvantage of known crossbars lies in the fact that the processor circuits 15 are necessarily connected by a connection to the management and control processor of the intersections 14 as visible in FIG. 4, which monopolizes an output line of each of said processor circuits 15 .

Another disadvantage of known crossbars lies in the fact that their reconfiguration time is not compatible with the effective implementation of "SIMA" methods (Simple Instruction
Multiple Data), or fine-grained "MIND" (Multiple Instruction, Multiple Data) methods, corresponding to a large division of operations between the processors, for any application size. Also, the global reconfiguration performance of the channels is not better than the reconfiguration performance of the paths in static interconnection networks, such as the hypercube whose path reconfiguration times are of the order of 200. micro-seconds for an equivalent complexity (E. CHOW et al., Hyperswitch, network form hypercube computer, international symposium on computer architecture,
Hawaii, May 1988).

 Another disadvantage of known crossbars lies in the fact that their reconfiguration delay increases with the size of the crossbar (expressed in number of processor circuits or memories connected thereto) because the addressing of the connection points by the processor External connection control is sequential, which leads to using crossbar hierarchies rather than a uniform interconnection mechanism. This hierarchy of crossbars is translated into a cluster structure of the processor circuits, memories or other connected to the crossbar.

 Within a lower-level cluster, it is possible to divide the processors into logical clusters at a given time, without diminishing the virtual connectivity in the logical cluster or the physical cluster. On the other hand, the virtual "full connectivity", that is to say the possibility of simultaneous point-to-point communication of any processor or memory circuit with any other circuit, is not realized for the structure considered globally.

 The object of the invention is to overcome these various disadvantages of the state of the art.

 More specifically, a first object of the invention is to provide an interconnection unit between circuits allowing overall reconfiguration times thereof relatively low, of the order of a few microseconds with "CMOS" technologies for example , regardless of the size of it.

Furthermore, the interconnection unit according to the invention must allow the grouping of processors in logical clusters on demand in particular, for the multicasting of information within the structure and the division of all the processors into sub-assemblies. related.

 This objective is achieved by means of an interconnection unit between circuits, of the type comprising a plurality of transmitting and / or receiving communication channels crossing at channel connection points and making connections between said circuits connected to each other. at least one channel, a plurality of switching and control means of the state of the connection points, characterized in that the control of the switching means and the control of the state of said connection points is distributed between the circuits accessing said connection points-by a channel, the switching means and control of the state of a connection point being at least connected to the circuit accessing said connection point by at least said channel.

 Due to the fact that the processors directly control the change of state of the connection point or points to which they have access, the use of a control circuit of the connection points of the interconnection unit becomes accessory. This connection state change control is performed dynamically directly by the circuit or circuits accessing the connection points.

 Another object of the invention is to provide distributed connection management logic between the connection points, which provides advantages especially in terms of fault resistance.

 This objective is achieved by means of an interconnection unit between circuits, characterized in that the means for switching and checking the state of a connection point consist of at least one memory storage means. state of said connection point, said storage means being informed by a specific intersection management unit of said connection point.

 Another essential objective of the invention is to allow the logical organization of the interconnection structure by assigning logical addresses to the connection points of the structure, this assignment being done by transmission of messages on the channels accessing the points of access. connection.

This objective is achieved by means of an interconnection unit in which at least one logical address is assigned to each connection point in view of a connection request to said connection point, a unit characterized in that the unit Intersection management includes at least
means for storing the logical address assigned to said connection point,
a comparator means of at least two logical addresses,
means for memorizing a connection request.

 Yet another object of the invention is to no longer use an external circuit for the control of collisions but to perform collision detection at the internal structure of the interconnection unit.

 This objective is achieved by means of a circuit interconnection unit, characterized in that it comprises, at each connection point, storage means with at least two states for storing the different states of a priority mark. access to said connection points, said at least two state storage means, distributed at the connection points of a transmitter or receiver channel, being connected by a specific track for the propagation of a priority mark between said circuits of storage.

 Another object of the invention is to provide a method for implementing an interconnection unit between circuits of the type of that described above, which uses the flexibility of the structure of the unit in particular to position the state of the points of connection by message transmission on the communication channels.

This objective is achieved by using a method of implementing an interconnection unit between circuits, characterized in that to initialize the interconnection unit
each transmission channel transmits the logical address of each connection point placed on said transmitter channel,
- successively memorizing said logical address corresponding to each of said connection points of said transmitter channels in said means for storing the logical address,
to establish a connection between at least two circuits, one of the circuits being transmitter, the other receiver
transmitting on the emitter channel associated with the sending circuit requesting the connection, a message containing at least the logical address of the connection point corresponding to the connection request,
the connection request is noted by comparing the actual logical address of the connection point with the requested logical address when one of the following three conditions is fulfilled
i) if the requested logical address is identical to the actual logical address,
ii) if the requested logical address has a value meaning "any connection point on the sending channel",
iii) if the requested logical address and the logical-effective address are identical after masking the binary values corresponding to the two addresses by the same variable bitmask,
storing the connection request found in said means for storing a connection request.

 Yet another object of the invention is to provide a collision management method in the interconnection unit, the collision management being effected by the structure of the interconnect unit.

This objective as well as others which will appear later is achieved by means of a method of implementing an interconnection unit between circuits, unit comprising in each connection point of at least one receiving channel a means of for storing a priority mark, said storage means comprising a state machine, said states describing the position of the priority mark and being at least in the order
- state 1: "no mark",
- state 2: "connection request",
- state 3: "active mark",
- state 4: "suspended mark",
- state 5: "mark abandonment",
characterized in that
At initialization, the automaton of a storage means is set in state 3 and the automaton of the other memory means in state 1,
the automaton of a storage means switches to state 3 from state 1, if said memory means receives a mark forcing signal, in state 2 if said memory means receives a signal connection request and no mark forcing signal, and remains in state 1 in other cases,
the automaton of a storage means passes to the state 3, from the state 2, if said memory means receives a mark transfer signal, and remains in the state 2 in the opposite case,
the automaton of a storage means goes into state 5 from state 3, if said memory means receives a signal meaning "no ordinary message in progress" and that the receiver channel is not requisitioned, in state 4 if said storage means receives a signal meaning "no ordinary message in progress" and the receiving channel is requisitioned, and remains in state 3 in other cases,
the automaton of a storage means goes to state 5 from state 4 if and only if the receiver channel is not requisitioned,
the automaton of a storage means enters the state 3 from the state 5 if said storage means receives a connection request signal and a mark transfer signal, and enters the state 1 on the other hand.

Other features and advantages of the invention will appear on reading the following description of a preferred embodiment of the invention, given by way of non-limiting example and illustrated in the accompanying drawings in which:
FIG. 1 represents switching means of a connection of a known crossbar,
FIG. 2 represents a crossbar made using a matrix of components,
FIG. 3 represents a known crossbar with centralized reconfiguration,
FIG. 4 represents a known crossbar with parallel transmit and receive channels, centralized reconfiguration,
FIG. 5 represents a crossbar according to the invention,
FIG. 6 represents an intersection management unit according to the invention,
FIG. 7 represents the priority management mechanism according to the invention,
FIG. 8 represents a diagram of the operation of a PLC for the management of the access priority mark at the connection point according to the invention, and
FIG. 9 represents a block diagram of a 3 × 3 crossbar according to the invention.

 The distributed control crossbar interconnection unit according to the invention consists of a plurality of transmitting and / or receiving communication channels crossing at connection points and interconnecting a plurality of transmitter and / or receiver circuits placed on the channels, the transmitter circuits directly controlling the state of the connections of the channels. Each channel may consist of a plurality of distinct unidirectional lines depending on whether the transmission of the messages on the channel is in series or in parallel. In addition, the channels may include data transfer lines and control lines. Different types of structures of the crossbar according to the invention can be provided, which have already been mentioned in the description of the prior art. A first possibility consists of a square mesh grid consisting of vertical transmitting channels and horizontal receiving channels. crossing at points of connection inside the crossbar, each circuit connected to the crossbar transmitting respectively on a transmitter channel and receiving the information on a receiving channel. The transmitter parts of the circuits are connected to a dimension of the crossbar corresponding to the base of the transmitting channels, while the receiver parts of the circuits are connected to another dimension of the crossbar corresponding to the arrival of the receiver channels, as can be seen in FIG. transmitter channel associated with the transmitting part of a circuit crosses the receiving channel associated with the receiving part of said circuit at a connection point preferably located on the diagonal of the gate, the rank i of the transmitting part of the circuit according to a first dimension the crossbar being identical to the rank j of the receiving part of said circuit according to the other dimension of the crossbar.

 According to FIG. 4, another possibility of crossbar structure consists of a square mesh grid consisting of vertical transmitting and receiving channels communicating in an opposite direction, associated in pairs with respective circuits (transmitters and / or receivers, preferably emitter). and receiver), said respectively receiving receiving channels crossing pairs of horizontal channels and communicating in opposite directions. In this structure the circuits are placed on a single dimension of the crossbar or at the points of interconnection.

 The invention is not limited to these two types of crossbar, subsequently we will describe the invention mainly according to the first crossbar structure mentioned.

According to FIG. 5, the crossbar 1 comprises emitter 2 and / or receiver 2r communicating channels interconnecting circuits 1001, 1002, 1003, connected thereto, a plurality of section management units 10 placed at connection points P of transmitter channels 2e and receiver 2r, said intersection management units 10 being respectively connected to the emitter channel 2e substantially at the connection point P of the channel and communicating with a circuit via said channel
The aim of the intersection management unit 10 is to control the logical connection of a second transmitter channel with a receiver channel 2r, said logical connection between two channels being in a known manner provided by an AND logic gate 11 and a logic flip-flop. 12. In the usual implementations, the AND gate is made using "NAND" and "NOR" gates, and the AND gate 11 with at least two inputs is connected. at the output to the receiver channel 2r, its two inputs being connected to the second transmitting channel crossing said receiver channel 2r, the other at the output of the logic latch 12, so that according to the state of the logic latch 12, the AND logic gate 11 establishes a connection or not between the two transmitter channels 2e and receiver 2r intersecting as has already been mentioned previously.

 The intersection management circuit 10 is connected to the logic latch 12 so as to be able to control the state of said flip-flop. your crossbar 1 configuration is effected by broadcasting a configuration message from a circuit 100i, via its associated transmitter channel 2ei, simultaneously to the intersection management units 10 placed at the connection points P belonging to said transmitting channel. According to another variant, this message can pass through a specific track and auxiliary to the transmitter channel 2ei connecting the transmitter circuit 100i with the corresponding intersection management circuits 10 (not shown).

 The intersection management unit 10 comprises at least in the preferred embodiment of the invention, a series-parallel converter 13, a mask register 14, a comparator 15, an address memory register 16 and a sequencer 17 as shown in FIG. 6. The logic latch 12 is preferably connected to the intersection management circuit 10 by at least one output of the sequencer 17, the sequencer 17 being able to initialize or change the state of said flip-flop 12 by sending of an appropriate signal (initialization by the line RESET, and loading by the line w). The converter 13, the mask register 14, the comparator 15, the address memory register 16 and the sequencer 17 are connected logically so as to be able to communicate with each other.

 Before any configuration of the crossbar 1, its initialization is carried out in order to assign a logical address to each connection point. This initialization is carried out by transmitting on each 2nd transmitter channel of the crossbar, a message containing the logical address of each connection point P placed on the transmitter channel, the logical addresses assigned to said connection points P being memorized successively in the address memory registers 16 respectively intersection management units 10.

A specific logic address creation signal 210 informs each intersection management unit 10 placed on a 2nd emitter channel, this signal being placed on initialization in the sequencer of the first intersection management unit. close to the corresponding transmitter circuit, by a global control signal of the interconnection unit or by a local mechanism managed by a transmitter circuit. This specific signal 210 is intended to enable the intersection management unit 10 to store the logical address broadcast on the second transmitter channel in its memory register 16 of logical address. The logical address of the intersection can be loaded sequentially during the initialization phase of the crossbar, the end of loading of a logical address of an intersection triggering the start of address loading of the next intersection, either within the same channel , either for the whole crossbar or a crossbar component. The logical addresses or numbers of each connection point belonging to an emitter channel for example may be loaded by the processor circuit connected to the emitter channel. The numbers, corresponding to an address, assigned to the connection points placed on a receiver channel 2r are not necessarily the same, so as to allow different "views" of them from the second transmitter channels. to carry out the multicasting of information and the logical organization of the crossbar, according to the needs of the different circuits connected to it. The logical numbers or addresses of the connection points can be fully loaded at the time of initialization in their entire expression, or include an "address base" part loaded at the time of initialization of the crossbar, and a part "displacement in the crossbar" (or in general in the transmitter channel), fixed during the manufacture of the component supporting the crossbar. In this case, the part "base of address" can be diffused to all the intersections of the crossbar. The existence of different address databases is only used in a multicomponent version of the crossbar. In the opposite case, the logical addresses can be predefined in the form of physical addresses set during the manufacture of the component. The address memory register 16 is then a read-only memory ("ROM") register. This solution reduces the area of the substrate necessary to store the logical addresses of the connection point, and can also reduce the initialization time of the crossbar, but does not allow to have different views of the receiver channels for each transmitter circuit. It also has drawbacks for the management of the fault resistance of the interconnection circuit because a user circuit of a crossbar channel must know the numbers of the connection points associated with the failed channels, which does not is not the case If the addresses of the connection points are purely logical.

 In order to establish a connection request between at least one circuit 100i and a circuit 10Q1, a message containing at least the logical address of the connection point which is placed on the transmitter channel 2ei associated with this circuit is transmitted from the circuit 100i on the transmitter channel 2ei. the receiver channel 2rj associated with the circuit 100j. Transmission of the message can be done either in parallel or in series on the transmitter channel depending on the type of transmission on the crossbar channels as already indicated above. Preferably, for a serial transmission, the message consists mainly of an address part containing at least the logical address of the requested connection. The broadcast connection request message on the transmitter channel 2ei informs in parallel each converter 13 of the 2ndi transmitter channel. According to the embodiment of the invention, the converter 13 makes it possible to decode the information coming in series on the transmitter channel to the other channel elements connected to it, and respecting a serial transmission protocol characterized for example by the presence of specific bits placed at the beginning and end of the word.

 The logical connection request address obtained is compared to the logical address previously assigned to the connection point and stored in the address memory register 16 by the comparator of at least two logical addresses 15. If the result of the comparison shows the equality of the logical addresses compared, the sequencer 17 informs the logic latch 12, which establishes the effective connection between the transmitter channel and the receiver channel considered, the state of said sequencer 17 storing the existence of a connection request.

 Preferably, the connection request message may furthermore contain a mask value composed of a sequence of bits, this mask value making it possible to perform multicasting from a transmitter circuit.

More particularly, depending on the value of the mask included in the connection request message, it is possible to address a set of receiver channels as follows
a logic AND is performed beforehand between each binary element constituting the logical address stored in the memory register 16 of the intersection and each bit of the value of the mask by a corresponding rank, the result of this operation being stored in the mask register 14,
the comparison operation is carried out, via the comparator 15, between the value of the mask register 14 and the value of the requested logical address contained in the converter 13. If the result of this comparison, as previously, states the equality of the two values, the sequencer 17 stores a connection request. Next, depending on the mask value and the requested logical address, contained in the connection request message, it is possible to establish a connection by all or part of the connection points placed on a sender channel for broadcasting information to all or part of the receiver circuits associated with the corresponding receiver channels. If the sending channels are logically seen as organized into a binary tree, a suitable bit masking device in the requested channel number makes it possible to address only a set of subtrees of this binary tree, for multicast purposes. A specific value of the requested logical address, meaning "any connection point of the channel" can be substituted for a logical address in the connection request message to perform a multicast. The same result can be obtained by hiding all the bits of 'address.

 The crossbar 1 according to the invention comprises an arbitration mechanism for the detection of collisions and the management of the priority of access to the connection points of the crossbar. This arbitration mechanism is preferentially distributed at the connection points of the crossbar and can arise from different types of collision management methods.

A first method is to propagate from an intersection located on the far left of a crossbar receiver channel and positioned in a connection request state, control information to the intersections to the right of the first (or vice versa) on a line of the same receiver channel
If one of these intersections receives this control information and is set in the connection request state, it detects a possible collision and reports to its corresponding transmitter circuit an error. However, this method has the disadvantage of allocating a priority of the circuits per rank of transmitter channel and is not generally satisfactory in a parallel environment.

 A second method is to propagate, from an intersection positioned in the connection request state, control information to the right and to the left on the same line of the receiver channel. Any intersection of this line receiving this control information signals an error to the corresponding transmitter circuit. If two sending circuits simultaneously attempt to access the same receive channel, they receive an error message and will be in deadlock. A distributed solution to avoid this deadlock is the random wait. Another solution is to use a centralized management of collisions by an auxiliary control processor. A major disadvantage of this method is that it leads to a high rate of non-use of the transmitter and receiver channels.

 A third method consists in placing at least one crossbar at each receiving channel a distributed arbitration protocol, which protocol can be implemented at the component level. At a given time, a priority is assigned to one of the intersections of a receiver channel, this priority being reflected in the existence of a priority mark. The processor circuit associated with the corresponding transmitter channel obtains this access. When it stops using the receiver channel, the priority mark is propagated to the nearest intersection in the propagation direction of the mark that requests access to the receiving channel. If no such intersections exist, the priority mark is propagated to the immediately following intersection in the direction of propagation of the priority mark. When there is a request for access to the receiving channel by an emitting channel , the allocation time of the mark can be limited to a defined duration, which amounts to defining a maximum length of the messages.

 According to FIG. 7, the priority management module consists mainly of a storage element 110, connection tracks 100, 160 to 170, and logic gates 130 and 140 placed on the connection tracks. Said storage means 110 are placed at each connection point of a receiver channel, said storage means 110 of said receiver channel being connected by the specific line 100 closed so that the mark circulating on the line 100 and arriving at the end crossbar 1 propagation by this direction, continues its path to the left end of the crossbar by the return of the line 100, then again spreads to the right on the line 100.

 In this preferred embodiment of the invention, the storage means consists mainly of a finite state machine (of the sequencer type). The information stored in the storage means 110 are stored in the form of states of this automaton, the states of the automaton describing the presence, the absence or the transfer of a token of priority or mark.

More specifically, the different states of the automaton correspond to the following states
- state 1: "no mark",
- state 2: "connection request",
- state 3: "active mark",
- state 4: "suspended mark",
- state 5: "abandonment of the mark".

 The transition from one state to the other state of the automaton is done on reception of a clock signal, according to the current state and the input signals of the automaton. In order to fully describe the priority management module, we will explain the list of states of the PLC, the origin of the input signals from it, the destination of the output signals of the latter, and its equations of transition.

According to FIG. 7, the input signals of the storage element 110 are as follows
the input signal 160 serves to transfer the mark from its propagation track 100 to a storage means 110i satisfying the conditions for entering the state 3 "active mark",
the input signal 161 serves to transfer the mark from the previous module 11 0 # into the next module 110 1 + 1, according to the propagation direction of the mark, when no other means of storing the mark is requesting this brand. The input signal 161 allows a circular connection of all the storage means 110 associated with a receiver channel. This input signal 161 forces the automaton of the module 110i + 1 into the state 3 "active mark". When the module 100i is the rightmost module on the receiver channel, the input 161 allows the activation of the 100o module located on the left.

the output signal 165 corresponding to the input 165 of the corresponding intersection management unit 10 informs said unit for establishing the connection
the input signal 164 indicates to the storage means 110i that an ordinary message is being transmitted, or on the contrary that it is not the case. This input signal is connected to the specific track 210 determining the type of message sent to the crossbar (message / configuration) from a column management module 20 which will be described later,
the input signal 168 indicates the existence of an intersection connection request, this input signal being generated by the sequencer 17 of the corresponding intersection management unit 10,
the input signal 169 indicates the existence of a requisition request of the receiving channel associated with the priority management unit considered, said requisition request coming from a line management unit 30 which will be described later,
the input signal 170 indicates a request to reset the storage element 110i.

In the preferred embodiment of the invention, it is a global signal common to any interconnection unit 1 and originating from a control circuit of said unit or of the host machine in which it is placed (signal " RESET "general",
the input signal h corresponds to a clock signal input known per se
The output signals of the storage element 110 are as follows
the output signal 162 makes it possible to stop the propagation of the priority mark signal on the propagation track 100, at the storage means 10 0 which delivers the mark on said propagation track. As a result, this mark performs only one course of the track 100. The value of this output is set to "TRUE" if the state of the storage means 110i is the state 5 "mark abandonment" or if the input signal 168 "connection request" is set to "TRUE",
the output signal 163 makes it possible to transmit the signal representing the mark on the propagation track 100, where it will propagate to the next storage element 110 verifying the conditions for entering the state 3 "active mark".

This output signal 163 is set to "TRUE" If the storage element 110i is in the "mark abort" state,
the output signal 166 is "TRUE" If the state of the storage means 110 1 is the state 5 "mark abort". The value "TRUE" of this output signal is the condition for propagating the signal corresponding to the mark from the propagation track 100 to the output 167 of the storage means 100i, which is connected with the input 161 of the storage means 100i. + l, in the order of propagation of the priority mark signal.

 The other signal propagation means of a priority mark consist of the propagation track 100, which is connected to the input 160 and 161 and to the output 163 of the storage means 110. The signal 167 controlled by the value signal 166 is taken on the track 100 before a gate 140, placed on the track 100, and whose role will be described later. As already mentioned, the track 100 forms a loop so that the value of the signal flowing on the track 100, after the maximum index storage means 110 associated with a receiving channel, is transmitted by the track 100 to the means for memorizing 110 of minimum index. This track 100 is therefore formed of a unidirectional ring, the connection of the inputs on this ring can for example be done by logic gates "OR".

 The connection means 100 and 167 have logic gates 130 and 140 whose functions are as follows. The logic gate 130 performs a logical "AND" of the signal from the track 100 and the signal 166 from the storage means 110i, and delivers the result on the track 167. The logic gate 140 performs a logical AND between the signal 100 and the inverted signal 162 from the storage means 110i. This logic gate 140 delivers the corresponding result in the next portion of the track 100, in the direction of propagation of the priority mark signal. One can of course perform the calculation of the results mentioned above from an equivalent configuration of logic gates "NAND", "NO OR" and "NO" inverters. The object of the logic gate 140 is stopped the signal on the track 100 after a complete course on the ring or when this signal has allowed the transfer of the mark in the current storage means. The role of the logic gate 130 is to allow the propagation of this signal on the track 167 after a complete course of the ring, in order to force the next storage means 110 in the state 3 "active mark".

 We now describe the transition equations of the automaton. According to FIG. 8, the automaton comprises at least five states, from 1 to 5, previously described. In FIG. 8 we have represented a sixth state corresponding to the initial state 0 so as to facilitate the understanding of the sequencing of the states of a storage means 110. In the initial state 0, the value contained in the storage means 110 is arbitrary. Therefore, it is not necessary that there is a physical state of the automaton corresponding to this initial state 0.

The actual sequencing of the states of a storage means 110 starts from the initial state
O (in fact from any state), when said storage means 110 receives the reset signal 170. A storage means 110, belonging to a receiver channel, then enters the active mark state 3, which the storage means 110 being determined in advance, the other storage means 110 of said receiving channel passing into the state 1 "no mark".

 From state 1 "no mark", the automaton goes into state 3 "active mark" as soon as it receives the signal forcing the mark 161. From state 1 "no "mark", the controller goes into state 2 "connection request" as soon as it receives a connection request signal 168 and does not receive a forcing signal of the aforementioned mark 161. In other cases, the automaton remains in the current state 1 "no mark".

 From the state 2 "connection request", the PLC goes into state 3 "active mark" as soon as it receives the signal 160 representing the transfer of the mark. In the opposite case, it remains in the current state 2 "connection request".

 From the state 3 "active mark", the automaton goes into the state 5 "mark abandonment" as soon as it receives the signal 164 with a value meaning "no ordinary message in progress" (that is ie the CONFIGURATION value of this signal), and the channel requisition signal 169 corresponding to the FALSE value.

From state 3 "active mark", the automaton goes into state 4 "suspended mark if signal 164 has the value quoted CONFIGURATION and if channel requisition signal 169 is set to" TRUE " In other cases, the automaton remains in its current state 3 active mark ".

 From state 4 "suspended mark, the PLC goes into state 5" mark abort "If and only if channel requisition signal 169 is set to the value" FALSE ".

 From the state 5 "mark abort", the automaton goes into state 3 "active mark" if the connection request signal 168 is set to "TRUE" and if the mark transfer signal 160 is also set to "TRUE". From state 5 "mark abandonment", the automaton goes into state 1 "no mark" if the previous condition is not fulfilled and if it is in the state 5 "abort of mark "for a certain period of time, which may be represented by a pre-defined number of clock cycles h.This delay condition ensures that the signal 163 of transmission of the mark will be maintained for a sufficient time for the mark to be propagated to another remote memory means 110 verifying the conditions for entering the state 3 "active mark".

It can be considered that there is always such a memorization element of the priority mark verifying these conditions. When the delay conditions and signal condition 168 set to "TRUE" and signal 160 set to "TRUE" are not met, the controller remains in the current state 5 "mark abort".

 When exchanging messages between circuits, it is appropriate to distinguish the ordinary messages addressed from a transmitting circuit to a receiving circuit and not passing through the communication channels of the crossbar, so-called service messages that the circuits connected to the crossbar send to the latter. ci, such as requests for reconfiguration of the crossbar, connection requests issued by the circuits and error messages issued by the crossbar structure.

 This distinction can be made in different ways independently of the structure of the crossbar according to the invention, one of alternating systematically ordinary messages and service messages, the other consisting of place # r a type code messages in the header of each message.

This last solution has the disadvantage of modifying the usual message formats used by most processors. As a preferred solution we describe the first solution.

 In this case, the ordinary messages have a format similar to the service messages, the detection of the type of message being carried out by a column control unit 20, respectively connected to each transmitting channel of the crossbar, which receives each message sent from a circuit connected to its corresponding column, the analysis and returns on a specific line 210 a signal representative of the type of message addressed in particular to the intersection management units 10 of the channel, as can be seen in FIGS. 6 and 9. Column control unit 20 comprises a serial parallel converter adapted to the mode of transmission of the crossbar channels, a message length counter and a sequencer managing at least two states namely "MESSAGE" or "CONFIGURATION" .The specific line 210 links the intersection management units 10 placed at the connection point of an emitter channel to the associated column management unit 20 audit channel to inform them of the type of message they receive.

 Moreover, all the service messages exchanged in the crossbar structure must generally be acknowledged. In the preferred embodiment of the invention, a message acknowledgment management unit 40 is placed north of each transmitting channel 2e, the interconnection unit 1 being represented so that its sending channels are seen as tracks. North-South, as shown in Figure 9.

More specifically, the message acknowledgment management unit 40 comprises a serial-parallel converter and a sequencer for decoding the message transiting on the transmitter channel to which it is connected. Acknowledgment management unit 40 is indicated by one of its inputs by line 210 for determining the type of messages (MESSAGES /
CONFIGURATION). To acknowledge the message from a transmitter circuit and passing through a corresponding transmitter channel, the acknowledgment management unit 40 associated with said transmitter channel returns an acknowledgment information to the circuit that sent the message. This acknowledgment signal is transmitted by a specific vertical track (not shown). At the intersection of the column with the diagonal North
West - South East of the crossbar, the signal is transmitted to the receiving track of this intersection. In the case where the crossbar is multicomponent, only the components located on the diagonal of the multicomponent crossbar switch the signal to the receiving track. Several solutions are possible to ensure this property. One of them is to distinguish two types of components, one with switching on the diagonal, the other without switching.

Another is to make a global command of this switching, the signal providing this command being fixed on the card.

 In the preferred embodiment of the invention, the crossbar 1 comprises a plurality of line management units 30, said units 30 being preferably distributed to the west of each receiving channel 2r, each unit 30 consisting of at least one channel requisition flip-flop. The line management unit 30 transmits, via the receiving channel requisition specific line 169, a requisition state of said channel, contained in the line management unit 30, to the various storage means 110 of the state of operation. a priority mark associated with said receiving channel, so that when the current transmission on a receiving channel is completed, there can be no further message transmissions before the acknowledgment. Only intersections on the main diagonal of the crossbar are not blocked by this signal.

As has been indicated in the description of the state of the art, current crossbars frequently use transmitter and receiver channels placed in the same dimension, these channels being connected as needed by specific channels placed on the other dimension of the crossbar. This implies having a transmitter channel and a receiver channel per line and column in the case where the channels are monodirectional. This solution has the advantage that the connection of two processor circuits can be carried out in any horizontal channel. increases fault tolerance. -
The message transmitted on an emitter channel passes through at least two intersections, this may imply that the logical intersection address contained in the service message described above comprises at least two parts, one containing the logical address of the first intersection on the transmitter channel, the other containing the logical address of the second intersection on the connecting channel.

This therefore implies that there is an arbitration mechanism (priority mark management) on the sending and connecting channels. When the sender channel has acquired priority over the first intersection, it must request priority over the second intersection. This is likely to create a waiting time for the transmitter channel as well as for the connection channel. To avoid this phenomenon, the actual message (ordinary message) is transmitted to the first intersection as soon as priority is given to this intersection. The connection channel is not necessarily available at this time, said message is stored in a suitable storage means placed at this intersection (not shown). The sender channel becomes available again and the management unit of said intersection requests priority over the connection channel. As soon as this priority is obtained, the message is transmitted by the second intersection to the destination circuit. To increase the. As a result of the crossbar flow, it is possible to place also message storing means at the intersection between the connecting channel and the receiving channel. This organization maximizes the flow rate of the crossbar according to the invention.

 We will describe later, various uses of the crossbar according to the invention.

 DISTRIBUTED MANAGEMENT OF A VIRTUAL MEMORY.

A preferred use of the distributed reconfiguration crossbar according to the invention concerns the distributed management of a so-called "object-oriented" virtual memory. The global management of a virtual memory, in a parallel machine, is generally considered in the context of a strongly coupled machine (with shared memory) having caches and a primary memory. However, the problem also arises in the case of a weakly coupled machine, where the processors communicate by message. Large data, for example of the relationship type (CODD,
EF, "A Relational Model of Data for Larges Shared
Data Banks ", Communications of ACM, # 13, 6, June 1970), can be distributed among several processors.

using this data. In an object-oriented approach, these relationships are sets of objects in which each object is represented by an identifier, which is an invariant logical address.

The identifiers are exchanged between processors, and must be able to be transformed into conventional logical addresses or physical addresses by any processor. In such a system, a physical object address can be seen as a couple <processor number> <local address to a processor circuit>.

This representation is necessary to know which processor to request the data referenced by the identifier.

 In the case of an identifier-type logical address, the processor number of the corresponding data can not be directly determined from a field of the logical address. Indeed, the identifier must be invariant even if the value of the referenced object changes, while the placement of this object between the processors can be determined by this value.

 The known solution for defining an invariant logical address consists in carrying out two logical addressing "stages" as described in European Patent No. 88 401819.3. The object has a first level of logical addressing, which we call the physical identifier, and which is a classic logical address except that it contains an object number in a page and not a move in that page. This solution makes it possible not to change the physical identifier in case of compaction of the page, which simplifies the problem said of the management of the holes or the "garbage collection". In a multiprocessor environment, the physical identifier is composed of the <processor number> <packet number (optional)> <page number> <object number> fields. Since the physical identifier is of fixed size, it can be updated in place, and its logical address is invariant. The logical identifier is therefore the logical address of the physical identifier. In the solution presented in the aforementioned European patent application, the logical identifier is composed of the fields <logical packet number> <logical page number> <logical object number>. As a result it contains no information to determine the processor where the data is.

 The transformation of a logical identifier into a physical identifier, and a physical identifier into a physical address, is performed through decoding tables following a solution related to the general mechanism for decoding logical addresses. These tables include at least one physical identifier and an address, both normally on at least 32 bits, per object. Also it is not possible to replicate them on all the processors, firstly for reasons of update cost, and secondly because the volume of the tables could greatly exceed the volume of the referenced data. It is therefore necessary to distribute the tables between the processors. The physical identifiers necessarily necessary to calculate the processor number, the corresponding tables can be placed on the same processors as the data they reference. on the other hand, the tables making it possible to decode the two logical ientifiants can be placed only in a way independent of the localization of the data. The most natural solution is to place them between the hash processes on the identifier.

When a relation of R tuples (or more generally objects) resulting from relational operations (CODD, EF, article cited above) is distributed between p processors, it is generally represented by R identifiers or n-tuples of identifiers, also distributed among these processors (a n-tuple of identifiers results from several operations associating n source relations). To perform other operations on this relationship or read its tuples, you must transform the identifiers into physical addresses. For this purpose, in the method according to the invention, each processor has its R / p tuples in p 'packets and transmits them to the processors managing the decoding tables of the logical identifiers. These p 'processors return the corresponding physical identifier packets. In a general way p L77 p 'and it is convenient that p = p'. It will be assumed later that the processors processing the data are numbered from A + 1 to A + p, those performing the decoding of B + 1 to
B + p. In order to avoid access conflicts and centralized management, the sending of the packets is synchronized, each processor of index A + p first addressing a packet to the processor of index B + p and then B + p + 1, and thus in a circular manner (after having transmitted a packet to the processor B + p a continuous processor possibly by the processor B + 1); Links or paths between processors must be reconfigured after each step, whose duration is (k *
R * F / p2) + S, where F is the uniformity factor of the hash (ratio between the average and maximum size of a packet), k the transmission delay of a packet and
S the synchronization delay.

 In practice the size of a packet (ie b = R / p2) depends on p but must be greater than a few units so that F is not too high. We will also take K = 0.3 sec sec. , S = 0.2 sec., P = 16, R = 10,000, F = 1.2. The values of k, S, p, correspond to probable values if the processor is a transputer T800 (Inmos), F can be evaluated by simulations, R is a current value.

In this case the duration of a reconfiguration step is 12 sec + 3.2 + sec = 15.2 + A / Csec.

 So that the reconfiguration delay does not reduce the output of the multiprocessor too much, and represents for example less than 20% of the transfer time, it is necessary that the reconfiguration takes place in about 3 seconds or less, which is obviously very far some 1,000 ss sec of a complete reconfiguration in current crossbar systems according to our estimates, or even some 300 sec sec to which we would end with a partial reconfiguration, limited to a few dozens of intersections.

In the method according to the invention, each calculation processor knows the list of its successive decoding processors. On the other hand, a synchronization is preferably performed in the following manner. A simple or ring bidirectional link is made between the p processors with links available thanks to a suitable configuration of the crossbar. This ring link is maintained for the duration of the operation that uses the cluster of p processors; If the cluster of p processors has a bus specific to this cluster and intended for example to control processors, it is also conceivable to use this bus. This link connects the processor A + 1 with A + 2, A + 2 with A + 3, and so on. When the processor of index A + 1 has completed the current step, it transmits a message to the processor of index A + 2.When the latter has also completed the current step, it transmits the message to the processor
A + 3, and so on. When the processor A + pa receives the message and completes the current step, it begins the next step and returns the message to the processor A + p - 1, which does the same and transmits the message to the processor A + p -2 , And so on. Before starting the transfer of the packet to the decoding processor corresponding to the step considered, each processor of index A + i (i <p) requests the crossbar its connection with the corresponding receiver channels of the decoding processor.

To avoid the risk of collision, one or more input channels are reserved on each decoding processor and are all used by the processor that transmits the identifiers.

 This method corresponds to a use of the distributed reconfiguration crossbar in a "fine grain" SIMD application. However, the crossbar according to the invention can also be used with random access by each processor, in applications "MIMD" fine grain.

 NEURONAL NETWORK.

 Another use of the crossbar according to the invention relates to neural networks.

 In the distributed control crossbar the logic is located at the nodes of the interconnection network, and on the other hand the size of the circuits located at these nodes is very small, allowing the implantation of very many interconnections on a slice. These properties are similar to those generally expected of a network of "neuronal" type processors. On the other hand, in the case where the control is performed by the receiving processors, the crossbar according to the invention as described above corresponds to a neural network where the weights are either 0 or 1.

 In the case of a neural network, each intersection receives messages from a sending processor, and retransmits them to a receiving processor.

The principle of a "neural" type network is that each processor delivers a response that is a function of the sum of the received signals (represented for example by a message containing a number) from each of the transmitter channels, multiplied by the weight associated with the corresponding interconnection. The logic being distributed over the interconnections, these must not retransmit each received signal immediately, but multiply it first by the weight which is associated with them. In order to allow the weighting of the intersection to be adjusted, each intersection also receives messages from the receiving processor informing it of the activity level thereof, and possibly messages broadcast globally to the entire network informing it. the degree of validation of the response. These three types of messages can be transmitted alternately to the intersection, the message value being the activation level of the source processor (or the response), or a modifying factor (for example additive or multiplicative) of this level, previously recorded in a register of the intersection; The signal of each transmitter channel is transmitted simultaneously to all the intersections to which it is connected; Each receiving channel receives a signal from any intersection to which it is connected.

 The mode of operation of the crossbar is here multicasting ("multicasting").

 However, it can only intervene from one transmitter channel at a time. To avoid collisions, two solutions are possible. In the first case, each transmitter channel steers successively on the bus, at least within groups of transmit channels determined statically or dynamically. The reception is therefore parallel, the sequential transmission (the opposite would also be possible).

 A second solution lies in the fact that all the processors emit at the same time,. but the information is not transmitted immediately to the receiving processor. This solution corresponds to the storage of information from the messages at the intersection level, a solution that we have previously described in the context of crossbars with sending and receiving channels in the same dimension, which is the case here. In this second solution, the information is accumulated in the intersection (this amounts to determining a mean level), then multiplied with the weight, finally transmitted to the receiving processor. Operations at the intersection may be more complex than simple aggregation, and include distribution characteristics such as the munimum and maximum activation level during the period. For this transmission, either (i) multiplexing occurs between different intersections of the same receiver, either (ii) these transmit their result each in turn, for example by being activated by the previous intersection of the same receiver, or (iii) the intersections require access to the receiving channel when the level of message to be transmitted exceeds a certain threshold. At this time we will use on the line corresponding to the receiver a distributed arbitration mechanism equivalent to that previously proposed for conventional uses of the crossbar. Access to the receiving channels will be fair for transmission channels with the same transmission frequency, but less often for those requiring less frequent access to these channels. Solution (iii) seems the most interesting, especially in terms of possible communication rates.

 The calculation of the new value of the weight is carried out using an arithmetic and logic unit placed at each connection point, which can be composed for example of an adder and a shift register, one the activation levels are then stored in a counter. Given the sequential nature of the transmission or reception, the operations performed by each intersection do not need to be performed quickly, and sequential circuits are sufficient. As a result of the evaluations that will be presented below, the size of the intersection in 0.5 micron technology should be in the order of 600 * 800 square microns, and the number of elementary processors should be approximately the same as in a conventional use of the crossbar.

 Given their low complexity, these processors may eventually reside on the same slot as the intersection management units. It will then be possible to interconnect about 1,000 processors on a two-size unit of the size of a slice, with one million interconnections operating in parallel.

 It can be noted that neural networks are often simulated on architectures with a lower degree of parallelism. The fast reconfiguration crossbar of the type of the invention lends itself very well to the execution of the operations of a neuronal network comprising an n times higher number of neurons, provided that each intersection has n memory words at the same time. the position of the state latch 12, and that each elementary processor (or neuron) can maintain its activation level in a memory of n words (the size of the word in bits being the logarithm of the number of states). In practice by multiplying by 4 the surface of the intersection, it is possible to treat a virtual network comprising approximately 750 times more basic-processors than the physical network. The process switching on this network can be done in a synchronous way (on executes the operations of a "virtual plane" of the network, then of another, in successive time slots), or asynchronous, a physical intersection supporting a new logical intersection (or a processor supporting a new process) when certain conditions are met. The first solution allows in particular to treat several "neural" problems in parallel on the same physical network. The problems of logical interconnection between "planes" of the virtual network (how a process located in one plane can communicate with a process or an intersection located in another plane) are outside the object of the present invention.

 MATRIX PROCESSORS.

 In the use of the crossbar according to the invention described above, the main processors are formal neurons placed for example south of the interconnection matrix. However, there is one element of computation at each intersection, and it is possible to consider that there is therefore a second type of elementary processor placed at the intersections.

In fact, the principle of a distributed control interconnection matrix also makes it possible to create an interconnection network, for example a square grid, with processors placed at the intersections of the grid. This application is particularly interesting for interconnecting a large number of elementary processors each provided with a local memory, and integrated at the same level.

 In this case, the bottleneck caused by centralized management of a known interconnection network is all the greater, as the number of processors on the network increases in N2 as a function of the number of rows and columns of the network. . On the other hand, the fine-grained "MIMD" operation of the network necessitates very fast reconfigurations. The operation is a priori "MIMD" insofar as each processor has a significant memory and can execute a program or function different from other processors, it is a priori fine-grained to the extent that the available space for memory The local area is nevertheless limited to 1 / p2 of the area of the unit and, on the other hand, the high number of processors allows a large division of operations.

The interest of associating logic with memory has been recognized for many years, and gave birth to particular ASIC (Application Specific Integrated Circuits) circuits with memory. In many works the memory is divided into many memory spaces accessible in parallel, for example using a crossbar (Miracki et al., Design of a 64 Processor by 128 Memory
Crossbar Switching Network ", IEEE Int.
Computer Design, Rye Brook, NY, Oct. 1988). It is known that the development of wafer-level integration technologies makes it possible to place a number of these memory spaces and their associated logic in a single component. or the same slice, and one of the possible solutions for the interconnection of different processors is to place them at the nodes of a square interconnect matrix (or crossbar). In the context of conventional crossbars designs, this interconnection matrix is managed by a specific circuit that routes and arbitrates centrally. This centralized circuit appears all the more natural in this case that there are many possible paths between two processors, regardless of how the matrix is made.

However, the reconfiguration times are then limited by the input-output and processing capacity of this circuit. This is all the more unfavorable in the case of "MIMD" operation with many very short messages, or "SIMD" operating periods with very frequent global reconfigurations.

The solution of a distributed control of the interconnect matrix by the processors is first made possible by the observation that it is possible to limit the number of paths taken by the messages between any two processors. either two processors Pij and Pi'j ', where i and i' are line indices, j and j 'column indices in each crossbar, the two simplest paths of
Pij to Pi'j 'are the "horizontal first" path, where the signal first propagates on a West-East channel to the intersection corresponding to the processor
Pij ', then on a North-South channel until the processor
Pi'j ', the other path being the "vertical first" path defined symmetrically. The distributed control of the interconnection matrix must allow the direct realization of these two paths, which makes it possible always to have an escape route used effectively in the event of an intersection failure. If the probability of connection between a processor Pij and a processor Pi'j 'is equal regardless of i, j, i', j ', the exclusive use of these two paths appears sufficient to ensure a uniform distribution of the use different intersections and channels. The same is true within rectangular partitions of the interconnect matrix, if the probability of interconnection is uniform within each of these partitions.

Other paths can be used in degraded operation by passing messages through intermediate processors, which in turn handle the transmission to the final processor or another intermediate processor. However, this requires more complex protocols to guarantee the establishment of the path (of the type for example of those used in the hypercubes), and consumes the calculation time of the intermediate processors, so it can not be normal operation.

 In the case of establishing one of the previous simple paths, the processor placed at one of the nodes of the matrix first chooses to transmit the message first on a line transmitter channel or a column emitter channel. It then verifies that the sender channel is free, this access to the channel can be done according to one of the known bus or network arbitration protocols. In the solution according to the invention, it positions a channel request and waits for the arrival of an access token to the transmitter channel, transmitted on a specific track according to the collision management mechanism described above. it then transmits on this channel a service message including a connection request, and mainly formed of a physical address or logical line and a column address. In the case of a "vertical first" path, the line address is first used to determine the line where the message will be switched to a horizontal "sink" channel The arrival of the service message on the intersection between the vertical transmitter channel and the horizontal receiver channel determines the eventual recording of the service message in a storage means placed at this intersection, and the request of the receiving channel A first acknowledgment of the request by the intersection can be addressed then the transmitter processor to ensure the proper operation of the intersection.L allocation of the receiver channel can be performed according to different protocols, the preferred embodiment of the protocol according to the invention based on the reception by the intersection of a token When the access to the receiving channel is obtained, the intersection making the connection of the transmitter and receiver channel transmits the message of the receiver channel. ervice (or only the column address, in the case of the "vertical first" path) to the receiving processor. If this processor is free, an interconnect flip-flop is positioned and connects the processor or its memory with the receiver channel. A final acknowledgment signal of the service message is then transmitted to the sending processor, via the intersection which connects the transmitter and receiver channels. In the opposite case, an intermediate acknowledgment signal may possibly be transmitted at the transmitting intersection. to express the proper functioning of the receiving intersection. Acknowledgment signals can either use the normal receiver channels of the transmitting processors or borrow reserved tracks for message acknowledgment. In the case of distributed processors in the crossbar, surface and complexity considerations lead to choosing this second solution as a preferential solution. Note that protocols without acknowledgment (sending "datagrams") or sending error messages are also possible. . The remarks are also valid for ordinary messages.

As we have presented so far, this protocol has a significant disadvantage, it indeed leads to leave the idle transmitter channel between the transmission of the service message by the sender processor, and obtaining the corresponding receiver channel. It is therefore satisfactory only with a sufficiently low utilization rate of the interconnection network, leading to acceptable waiting rates. This drawback is not encountered in the version with a transmitter channel processor, where a channel transmitter is never requested by another processor
One solution consists in admitting the successive transmission of several service messages intended for several intersections by the different processors of the same sender channel. Each sending processor then returns the token after the transmission of the service message. If more than one service message is sent to the same intersection, it will return a negative acknowledgment for all but the first message. The service message must contain the calling processor number, which is stored in the intersection. When an intersection receives the acknowledgment of the destination processor, it must request access to the sender channel and the acknowledgment channel to allow the requesting processor to transmit the useful message to the destination processor.

 If we want to prevent the receiving channel from waiting for the availability of the sending channel, the best solution is however to store the useful message in the intersection. We have already presented this solution in the general case of crossbars with receiver and transmitter channels in the same dimension, which is the case here. If the size of the message is limited here to 16 bytes, and if the slice has 32 * 32 processors, the area needed to keep the messages in the intersections is about 4 * 128 * 100 * 65 * 1.024 to 2, or about 212 mm2 in 0.5 micron technology. In a preferred solution, the message is indeed stored in a register & shift whose size is of the order of 50 x 65 ss 2 per bit. The number of registers necessary to keep the useful messages is 4 per intersection if takes into account the different possible paths. Based on a 70 * 70 mm2 slice, this represents about 4% of the slice area and therefore remains very acceptable. With this solution, the utilization rate of the sending and receiving channels can approach 100%, including the service messages and the chip propagation time.

 In some cases, it may be desirable to transmit large amounts of data without having to go through the previous protocol each time. In this case, one of the transmitter channels (respectively receiver) concerned must be put on hold until the corresponding receiving channel (or transmitter) is available, and then after final acknowledgment of the connection request the two channels are requisitioned until the end of the transmission. Due to the existence of several paths to communicate between two processors, this requisition mechanism can be authorized only on certain types of paths, either at the level of the physical execution of this protocol by the intersections, or by a specification adequate processors themselves.

 Finally, it may be desirable to dynamically partition the circuit into independent rectangles so as to increase the bit rate of the transmitting and receiving channels. For this purpose, the propagation on the transmitter and receiver channels must be able to be stopped at each intersection by appropriate logic gates. In this case there may be several priority tokens generated on the same channel. Partitioning and removal of this partitioning are performed by service messages addressed to the intersection concerned. In the partitioned operation, the total message flow can be greatly increased, but in the simplest solution there is no communication between the partitions. However, if each processor has several transmitter and receiver channels in line and in column, it is possible to consider that they correspond to several superimposed communication "planes" and to perform independent partitioning in the different planes. In this case with at least one unpartitioned plan, the partitions can communicate with each other. A second solution is to have a plane in which the communications are carried out only with the immediate neighbors, which also solves the problem of communications between neighboring partitions, but not between distant partitions.

 As the partitioning must be known by all the processors of the row or column, it is desirable that it be performed by a single processor for each transmitter and / or receiver channel, this processor having to obtain the corresponding row or column beforehand. and report the partitioning to processors in the row or column. Each processor must be able to communicate with the processor of the row or column performing the partitioning. This can be achieved by using a special channel for reconfiguration messages, or by using a non-shared communication plan according to the previous solution. In any case, the partitioning still remains distributed.

 To avoid that reconfiguration is impossible in the event of an intersection failure, a track may be reserved on each row and / or column for resetting the partitioning flip-flops on the entire line or column.

 From the moment the processors are at the connection points, it is possible to partition each transmitter and receiver channel by AND logic gates. Under these conditions, each partition can transmit data concurrently to other partitions, which increases the flow of the crossbar. Of course, the management of the collisions must be done inside one of each of the partitions, which implies that the track 100 of propagation of the priority mark forms a ring inside each partition by means of doors. appropriate logic.

PRESENTATION OF THE BASIC CIRCUITS AND
SURFACE EVALUATIONS.

 We now present each basic circuit to give an approximate evaluation of its surface. The dimensions are evaluated at A, corresponding to the half-channel width of the transistor. In HCMOS3 technology (1.3 microns), ss = 0 # 65% X, in the HCMOS4 technology (0.5 microns) being sampled,> = 0.25 / k. We will then give an overall assessment of the dimensions of the crossbar.

 CONVERTER.

The parallel serial converter is a classic circuit in computers. In the preferred embodiment of the invention, it respects the transputer transmission protocol (INMOS, "Transputer Reference Manual", Prentice-Hall, New York,
USA, 1988). The transmission is done by messages formed of one or more words of n bits (in the transputer n = 8), n being a constant for a given crossbar.

Each word is preceded by a bit at 1, followed by a bit at 0. To acknowledge a word, the receiver (one of the converters receiving this word) sends back to the transmitter a bit to 1. This protocol presents the the advantage of being easy enough to implement by hardware, and it ensures that in case of transmitter blocked in transmission, the transmission will stop at the onset of the failure.

 In the preferred embodiment this converter is placed at each node of the crossbar, as well as at the bottom and at the top of each column. It consists of a shift register of n + 2 bits, the shift occurring at each clock tick when the register contains at least one bit at 1. It is also possible to manage it with a at least three state machine, which goes into the state "ACTIVE11 on receipt of a first bit, remains in this state until the leftmost bit of the register is at 1 (in the case of a shift from right to left), then goes into the "RECOPIE" state if the bit received during this cycle is at 0, then goes into the "INACTIVE" state if the bit subsequently received is zero. "ACTIVE" state this sequencer shifts the data by one bit at each cycle, in the "RECOPIA" state it transfers it to a register of several bits, in the next state it erases the ns 1 bits to the right. sequencer can be common to a column.

The converter can be made using n + 2 flip-flops D. Each flip-flop can be viewed as consisting of two one-bit cells, having approximately 50 * 65 (static memory). We use the approximate dimensions found in technology
HCMOS3, the D flip-flop therefore has about 100 * 65 to 2 The D flip-flops of a converter are not necessarily placed linearly. For an 8-bit word, the total size of the converter can therefore be limited to about 200 * 260> 2 (about 50 * 62 microns in HCMOS4).

 The size of the converter word, in bits, must be at least equal to the number of lines of the complete crossbar, possibly formed by several smaller crossbars. If the interconnection network realized by crossbars can reach 1000 lines per 1000 columns, the word size must be at least 10 bits. Since it is also desirable to take into account one-byte word transmission protocols, which transmit lo bits per byte, the desirable size of the shift register is 20 bits.

 ADDRESS LOGIOUE AND MASOUE REGISTERS.

 These registers are made in static memory of about 50 * 65 ss 2 per cell. For a crossbar not exceeding 4096 lines, the number of bits needed for each of these registers is 12.

 Its surface can therefore be about 600 * 65> 2.

 In the case where there is an address register and a mask register, the corresponding total area is 600 * 130> 2 (150 * 33 microns).

 UNIT FOR MANAGING AN INTERSECTION.

As shown in FIG. 6, the intersection management circuit (not including the horizontal and vertical tracks) is essentially composed of a converter, a mask and an address register, which should be the elements the most expensive in terms of surface. The sequencer is mainly composed of a few D flip-flops, the comparator of a few gates per bit. The priority management module is also mainly composed of a few D flip-flops. The total area of the intersection should therefore be less than 600 * 600> 2.
COLUMN MANAGEMENT UNIT.

This circuit consists of the following elements
a sequential-parallel converter. This converter receives the length word of each message. If this length is expressed in bytes, we will accept by convention that the message actually transmitted includes an even number of bytes (the logical and physical length may differ). The length word may then comprise two bytes, among which a certain number of bits encode the type of message (message to be transmitted or service message for the crossbar) and possibly an instruction for the crossbar.

 The size of the converter is of the order of 500 * 260> 2.

 a length counter in which is stored the length word of any message whose word of length is greater than 2 bytes).

The size of this counter is of the order of 600 * 130 X 2
a sequencer managing at least two states
MESSAGE or CONFIGURATION. This sequencer can be constituted using sequences of flip-flops D. In this case its size has no practical impact on the dimensions of the crossbar.

 The dimensions of the column management unit are therefore of the order of 600 * 600 A 2 or less.

 VERTICAL TRACKS.

The number of vertical tracks helps to determine the spacing between the columns. Apart from possibly power supplies, the vertical tracks are preferably seven in number
- transmission of the serial signal of a transmitter,
- MESSAGE / CONFIGURATION signal,
- return of the acknowledgment of messages to the corresponding reception track.

(in the processor-memory interconnections, this track is also used to return the data to the processors),
- request signal accepted or refused by the intersection, possibly on two tracks; to account for transmission delays and the fact that the signal may come from several intersections on the same receiver channel, it is desirable to encode this signal on two bits, for example 110111 = accepted and "10. =" refused ".

- free response track signal (this signal comes from the receiving channel management circuit, as long as it is not set, the acknowledgment of the service message or its bytes can not intervene)
- column activation signal; when not positioned, the column is disabled.

 In total, up to 7 signals. Although some of them may possibly be multiplexed, it is reasonable to provide 7 tracks.

With a spacing of 7 Å between tracks, the interval used by the vertical tracks is 49 A, which does not change the order of magnitude of the horizontal pitch. By cons this situation is very unfavorable to the realization of a crossbar in several components, according to the principle of Figure 2. We will see below that it is possible to achieve a crossbar according to the invention, large, by integration at the level of the slice, with a good manufacturing efficiency.

 HORIZONTAL TRACKS.

 As will appear in the following paragraphs, the number of horizontal runways should also be 7, ie 5 for priority mark management, one for track requisition and one for message transmission (excluding runways). power, clock and control common to the entire crossbar).

The space required for the tracks in the vertical pitch is therefore also in the order of 50
NOT HORIZONTAL AND VERTICAL.

 It follows from the preceding evaluations that the horizontal and vertical pitch (interval between the middle of two rows or of two columns) is of the order of 650> at the most. This result will be used to estimate the size of a crossbar according to the invention.

 OTHER MISCELLANEOUS CHARACTERISTICS.

 TIME OF ACOUTING A SERVICE MESSAGE.

 After a delay corresponding at most to the transmission time of a message of maximum size, the acknowledgment signal and the acknowledgment byte are transmitted on the receiving channel of the same index as the transmitting channel. With a maximum message size of 256 bytes (plus two bytes of length and type) and a transmission rate of 100 megabits per second, the maximum acknowledgment time is of the order of 2.6 microseconds. With a bitrate of 20 Megabits per second it would be 13 microseconds. It is obviously necessary that this delay does not generate an error signal in the processor.

 Optionally, the flip-flops are reset after a certain time.

The proposed mechanism is as follows. The storage takes place in a first flip-flop. During a reset signal of the flip-flop, the value is transmitted to a second flip-flop, according to an approach comparable to that of the flip-flops D. The value of the set of two flip-flops is a "LOGICAL OR" of the values of each of the two flip-flops. The delay between two reset tops must be greater than the maximum acknowledgment time.

 Another important delay is the latency between messages, in the case where the same processor requests to send a new data message, and for which no other is requesting the line.

The latency time is then at least equal to the circular propagation time of the mark. This is of the order of: L = 2 nt, where n is the number of transmitter channels, and t the delay of a gate. Let for n = 100 and t = 0.5 ns, L = 100 ns; for n = 1,000 and t = 0.5 ns, L = 1 microsecond. This latency is not perceptible if it is less than the transmission time of a service message, for example at 100 Mhz and for an 18-bit message, 180 ns. In the case of large crossbars and high transmission frequencies, this phenomenon may lead to privileging the transmission of sufficiently long messages (a few tens of words).

 PRIORITY MANAGEMENT.

 Figure 7 shows the mechanism of propagation of the priority mark in a "ring" version. In a "bidirectional linear" version, where the direction of propagation varies when the mark signal arrives at the end of the line, the propagation is done along two unidirectional lines (for electrical reasons, at least in electronic technology). The propagation logic is present on both tracks, while in the ring version the track "to the left" is only used for signal transmission. There is at least one additional track for transmitting control information on the direction of transmission. This mechanism thus uses 6 tracks at least instead of 5.

 A complementary aspect of this arbitration mechanism results from the existence of the requisition circuits on the left of each track, intended for the management and the acknowledgment of the service messages. So that the user can give a processor the ability to broadcast a message in priority, regardless of the position of the mark, it is sufficient to give this processor the ability to set to "true" the requisite flip-flops of the corresponding tracks.

Normally these flip-flops are positioned only in the reception tracks of the same index as the transmission tracks where a -service message has been sent. It is also possible to position these latches on any track that is the subject of a request for transmission by a processor "absolutely priori tary". An absolutely priority processor "is characterized by a #signal to" true "on a vertical track associated with its column, and positioned by an external control processor.This positioning can be done either by the management of a specific pin associated with each column, or preferably by the serial transmission of a column number along the bottom line of the crossbar, equivalent to the request for access to a line.A specific track allows to delete all the "absolute priorities" You can also delete some of them sequentially using the same mechanism as for creating them, but with a different type of message code.The existence of the "absolute priority" mechanism allows a processor to perform non-interference broadcast or multicasts of the relative priority management mechanism - after a certain period of time no other processor can transmit In the preferred solution, the allocation of an absolute priority to a processor is done by a transmitter channel placed along the East-West dimension, and comprising intersection management units 50.These units are similar to units 10 apart from their disposal
East-West and the existence of a specific O-delivery trail to remove absolute priorities. It is also necessary that the transmission of the busy signal no longer take place at this time.

 ALLOCATION BETWEEN GROUPS OF LINES.

 In a number of cases, neighboring receiver tracks (lines) correspond to the same processor. When a processor requests access to one of these lines and it is busy, it is desirable that an appropriate mechanism allow the allocation of another line of the same processor. A solution in this case is that the transmitter successively requests the different lines of the group.

EXISTENCE OF A MANAGEMENT MECHANISM
CENTRAL.

 The preceding mechanisms in no way exclude the existence of a centralized control mechanism for logic latches, the use of this mechanism being optional. The realization of this mechanism can be based on the existence of line and column decoders, and a logical latch positioning signal, common to all the crossbar.

 CROSSBARS PROCESSORS MEMORY.

 The preferential solution that we presented previously applies directly to the processor-processor crossbars. In the case of memory processor crossbars it is necessary to distinguish the address tracks and the data tracks. These return to the processor that emits the address (they change direction at the intersection that manages access to the -path). Each transmitter and receiver is connected to the crossbar by at least two tracks (a transmit track, a receive track).

GLOBAL EVALUATIONS OF SURFACE AND
COMPLEXITY.

 In 0.5 micron technology (= 0.25 microns, the horizontal and vertical steps in absolute values are about 150 microns.) From the point of view of the available surface, a 1 cm2 crossbar component, made of HCMOS4, will be able to therefore have about 100 inputs and 100 outputs.

 A less favorable element in the crossbar according to the invention is the number of pins. If the crossbar is to be expandable on several components, the number of horizontal pins is 7 * r, the number of vertical pins is 7 * e, where e and r are the numbers of transmit and receive channels respectively.

In addition, there are a small number of power supply pins and centralized control signals.

If the number of rows and columns is limited by the number of pins or pads, a case of a given size will have 7 times fewer entries and 7 times fewer outputs than a conventional crossbar, and 49 times less intersection. For example, a 260-pin component, which represents a large box, will have at most 10 inputs and 10 outputs. A crossbar made with this component will occupy a large area, and especially given the propagation time between boxes (delays of the input and output amplifiers, external capacities), it will be more difficult to obtain propagation delays. end to end of a line that are satisfactory, at least with current electronic technologies. The bit rates are therefore likely to be lower and the message acknowledgment times longer. Finally a 200 by 200 crossbar would require 400 boxes, and would consume 400 watts on the basis of one watt per cm2 (which is a weak hypothesis). These features are not compatible for satisfactory use.

 Another solution is to perform the crossbar on a single housing, by integration at the level of the wafer, this crossbar according to the invention sty lent well, in terms of manufacturing yields.

In this case it is sufficient to use one pin per transmitter channel and one pin per receiver channel, plus the power and control pins. This solution obviously poses unusual problems of realization of the housings. But these problems are likely to become more classic with the development of integration at the level of the slice. For a 256-by-256 crossbar that can connect 64 4-link processors, or fewer with higher future link numbers and external link management, the total number of connectors exceeds 1,000.

This can be easier to achieve with optical technologies than electric technologies.

It can be noted that circuits with several thousand connectors exist on high performance machines, but at the card and not the box.

 On the other hand a circuit having this number of rows and columns can be realized with a single component, even with a surface of 1 cm 2 or a side of 1.5 cm (2.25 cm 2). The use of several micro-connected components in the same housing is possible but does not reduce the limitations due to the size of the pads. It appears however that a second solution is the realization of the circuit by integration at the scale of the wafer, for which the crossbar according to the invention is particularly well suited.

FAULT TOLERANCE AND YIELDS
MANUFACTURING.

 Unlike the conventional crossbar, the crossbar according to the invention can operate sustainably and with unchanged efficiency (no routing problem) with lines, columns or intersections failed. The condition is that these failures have been detected during manufacture. In the case of a broken intersection, the lines and columns to be deleted are on the one hand the line and the current column of the intersection, on the other hand the line that cuts the deleted column on the diagonal of the component (or the complete crossbar in the case of a multicomponent crossbar), finally the column that cuts the deleted line on the diagonal. As a result, each broken intersection leads to the deletion of two rows and two columns. The deletion of a row or column is done by hardware, by not connecting this line or column to the pins or by not connecting them to the processors. Faults should not occur in the control lines and columns of the crossbar (bottom and top row, left and right columns).

 Dynamic fault tolerance is also possible, but it results in a decrease in performance, since it is performed by a re-routing of messages, which must be managed by a dialogue between the processors managing the corresponding columns and a control processor . The use of this possibility is therefore not generally optimum.

 For a certain intersection failure rate per cm2, the proportion of unavailable rows and columns increases with the area, or the side of the slice. For example, a manufacturing technique leading on average to two failures per cm2, a component of 1 cm2 (theoretical size 100 * 100) will be used at 96% of its inputs and outputs, a slice having a useful part of 4 cm2 (theoretical size 200 * 200) to 92 8, and will therefore manage about 184 entries and exits, a slice of 9 cm2 (theoretical size 300 * 300) will be used at 82%, and will manage 264 entries and exits. A square slice of 100 cm2 (Thematic size 1.000 * 1.000) would be used at 60 8, in other words it will achieve a crossbar of 600 * 600.

 However with higher yields per cm2, it will be possible to get closer to the theoretical size. If the spacing between the pads is 0.2 mm and if they are arranged edge edge, the maximum possible size for a crossbar of this size is in practice of the order of 500 by 500. In practice the Usual size of the slices allows to write a square of 7 cm * 7 cm. Note that the difficulty of this type of circuit resides in the number of connectors, the effect of this phenomenon is reduced if the fault detection occurs before packaging. Indeed it remains possible to have the same number of pins for the input and output channels, only the number of tracks and columns usable in the circuit being changed.

  Finally, by combining optical I / O that may not all be on the same line or using several lines of pins with pins placed on the same lines, such a crossbar must actually be able to reach a size of 1,000 by 1,000 with slice sizes similar to those that currently exist. Multi-component or multi-slice implementations are also possible.

 Of course, the invention is not limited to the embodiment described, for which one could consider using optoelectronic circuits for example.

Claims (15)

CLAIMS.  1) Interconnection unit (1) between circuits (1001, 1002, 1003), of the type comprising a plurality of emitter (2e) and / or receiver (2r) communication channels intersecting at connection points (P) of channels and making connections between said circuits connected to at least one channel, a plurality of switching and control means (11, 12) of the state of the connection points, characterized in that the control of the switching means and control (11, 12) of the state of said connection points (P) is distributed between the circuits (1001, 1002, 1003) accessing said connection points (P) through a channel (2e), the switching means and control (11, 12) of the state of a connection point (P) being at least connected to the circuit accessing said connection point by at least said channel.  2) interconnection unit between circuits, according to claim 1, characterized in that the switching means and control (11, 12) of the state of a connection point consist of at least one storage means (12) of the state of said connection point (P), said storage means (12) being connected to an intersection management unit (10) specific to the connection point (P).  3) circuit interconnection unit according to claims 1 or 2, wherein at least one logical address is assigned to each connection point for a connection request to said connection point, a unit characterized in that the an intersection management unit (10) comprises at least:  means for storing (16) the logical address assigned to said connection point,  a comparator means (15) of at least two logical addresses,  means for storing (17) a connection request.  4) interconnection unit between circuits, according to claim 3, characterized in that it comprises at each connection point (P) a storage means (110) at least two states for storing different states of a access priority mark at said connection points, said at least two state storage means (110), distributed at the connection points (P) of a transmitter or receiver channel, being connected by a specific track (100) to propagating a priority mark between said memory circuits (110).  5) interconnection unit between circuits, according to claim 4, characterized in that said storage means (110) to at least two states consists of a state machine finite.  6) a circuit interconnection unit according to any one of claims 1 to 5, wherein the at least one transmitter channel is represented by north-south tracks, wherein said circuits communicate to the interconnection unit of service messages therefor, characterized in that  each transmitter channel (2e) comprises transmitting channel management means (20) for at least detecting the messages intended for the interconnection unit; specific means for acknowledging (40) service messages from a transmission channel; transmitter circuit, said transmitter channel management means (20) being connected to the south end of said transmitter channel, said specific means of acknowledgment (40) of service messages being connected to the north end of said transmitter channel (2e) ,  each receiver channel (2r) comprises a specific receiver channel management means (30), said receiver channel management means being connected to said priority mark management circuits (110), associated with said receiver channel, by a track specific (169) channel requisition.  7) a circuit interconnection unit according to claim 6, characterized in that said transmitter channel management means (20) associated with an emitter channel is connected to said intersection management units (10) placed on said channel, by a specific line (210).  8) a unit interconnection between circuits, according to claim 6, characterized in that said receiving channel management means (30) associated with a receiving channel is connected to said storage means of a priority mark (110) placed on said channel, by a specific line (169).  9) interconnection unit between circuits, according to claim 2, characterized in that at least a portion of the intersection management units (10) comprises means for storing messages passing through the intersection.  10) A method of implementing an interconnection unit between circuits, according to claims 1 and 3, characterized in that  to initialize the interconnect unit:  each of the transmission channels (2e) transmits the logical address of each connection point placed on said transmitter channel,  - successively memorizing said logical address corresponding to each of said connection points of said transmitter channels in said storage means (16) of the logical address,  to establish a connection between at least two circuits, one of the circuits being transmitter, the other receiver ::  transmitting on the emitter channel associated with the sending circuit requesting the connection, a message containing at least the logical address of the connection point corresponding to the connection request,  the connection request is noted by comparing the actual logical address of the connection point with the requested logical address when one of the following three conditions is fulfilled  i) if the requested logical address is identical to the actual logical address,  ii) if the requested logical address has a value meaning "any connection point on the sending channel",  iii) if the requested logical address and the actual logical address are identical after masking the binary values corresponding to the two addresses by the same variable bitmask,  - Saving the connection request found in said storage means (17) of a connection request.  11) A method of implementing an interconnection unit between circuits, according to claim 10, characterized in that a connection is established between a transmitter channel and a receiver channel when there is a connection request and a access priority mark attached to said connection point of the sending channel and the receiving channel.  12) A method of implementing an interconnection unit between circuits, according to claim 11, unit comprising in each connection point of at least one receiving channel means for storing (110) a priority mark, said storage means (read) comprising a state machine, said states describing the position of the priority mark and being at least in the order  - state 1: "no mark",  - state 2: "connection request",  - state 3: "active mark",  - state 4: "suspended mark",  - state 5: "mark abandonment",  characterized in that  At initialization, the automaton of a storage means (110) is set in the state 3 and the automaton of the other storage means (110) in the state 1,  the automaton of a storage means (110) goes to the state 3, from the state 1, if the said storage means (110) receives a mark forcing signal (161), in the state 2 if said storage means (110) receives a connection request signal (168) and no mark forcing signal (161), and remains in state 1 in the other cases,  - The controller of a storage means (110) goes to state 3, from the state 2 ;; if said storage means (110) receives a mark transfer signal (160), and remains in state 2 otherwise;  the automaton of a storage means (110) goes into state 5 from state 3, if said storage means (110) receives a signal meaning "no ordinary message in progress" (164) and that the receiving channel is not requisitioned, in state 4 if said storage means receives a signal meaning "no ordinary message in progress" (164) and the receiving channel is requisitioned, and remains in the state 3 in other cases,  the automaton of a storage means (110) goes to state 5 from state 4 if and only if the receiver channel is not requisitioned,  the controller of a storage means (110) switches to state 3 from state 5 if said storage means (110) receives a connection request signal (168) and a transfer signal of mark (160), and goes to state 1 otherwise.  13) Use of a circuit interconnection unit (1) according to claim 1, for the distributed management of a virtual memory in which the stored data consist of objects whose addresses are logical identifiers invariant to the modifications of value of said objects, the decoding of the logical identifiers into physical address being performed by a hierarchy of tables, the circuits being composed of data processing processors and address decoding processors, characterized in that ::  the decoding tables of said logical identifiers are distributed by hashing on the identifier between a plurality of decoding processors connected to said interconnection unit,  the decoding of the set of identifiers being organized in steps, during each of which a data processing processor is connected to a single address decoding processor,  at the end of a step, each data processing processor, knowing the address of the decoding processor to be connected to the next step, requests the connection with the latter in parallel with the requests of the others processors.  14) Use of a circuit interconnection unit (1) according to claim 1, of the type comprising parallel transmit and receive channels in the North-South direction and pairs of connection channels crossing said transmitting and receiving channels, for a neural network, characterized in that at each connection point of said interconnection unit is provided at least one arithmetic and logic unit and means for storing messages.  15) Use of a circuit interconnection unit (1) according to claim 1, of the type comprising parallel transmit and receive channels in the North-South direction and connecting channels crossing said transmitter and receiver channels for a matrix. memory processor element, characterized in that said circuits are placed at the connection points of said interconnection unit.