EP0774705B1 - Comparator with hysteresis for use in a voltage regulating circuit - Google Patents

Description

The invention relates to a hysteresis comparator circuit for Use as a comparison stage and control signal generator of an electrical Voltage control circuit with a voltage supplying the voltage to be regulated Voltage source, and a control circuit with such Comparator circuit.

There are electrical circuits for which a potential is provided must be above the potential of the supply voltage source lies. An example are circuits with NMOS transistors that are on the side of high supply voltage potential of your circuit are located and their gate electrode when they are turned on to be, a gate potential must be supplied, which is above the high supply voltage potential. Examples are CMOS circuits. To provide such a high gate potential Booster circuits used. For AC circuits you use bootstrap circuits. For DC applications one uses charge pumps or voltage pump circuits.

Such voltage pump circuits have a charging voltage capacitor on, which is about twice the value of the supply voltage source is charged with the help of the AC voltage a pump oscillator, usually in the form of a rectangular pulse train provided. This leads to electromagnetic radiation (EMR), which is particularly annoying in DC voltage applications can be. Measures are therefore required to achieve such EMR to encounter.

One can reduce the EMR by lowering the frequency the pump pulse sequence and / or by deliberately reducing the Raised slope of the pump pulses. Main disadvantage of this However, measures are that they only reduce the problem with the EMR, don't eliminate however.

DE 37 23 579 C1 describes a series voltage regulator with a comparator circuit known, which contains a difference level, which a Load stage is connected upstream, and which is a current mirror circuit is connected downstream. In this known longitudinal voltage regulator Comparator circuit for comparing output voltage and Input voltage of the controller, to one on the longitudinal controller branch Turn off the control transistor when the input voltage of the regulator drops below a nominal regulator output voltage in order to thereby caused by voltage drops on the input side Mitigate malfunctions.

Electronics, Sept. 16, 1976, pages 42 and 44 is a voltage pump circuit known in which the pump voltage to a predetermined Value is adjusted, depending on the output signal of a comparator a pump oscillator is switched on and off.

The object of the present invention is therefore a circuit arrangement to make available with such pump circuits completely eliminates the problem of EMR.

The basic idea for solving this task is as follows:
When the gate of said NMOS transistor is charged to the required pump voltage, the pumping process is ended, so that from then on the pumping frequency causing EMR no longer occurs. Since a MOS transistor has a very high gate input resistance, the pump voltage can be maintained for a relatively long time. In order not to counteract this, it is necessary to make the regulation of the pump voltage essentially loss-free, so that the capacitor holding the pump voltage is not burdened by the control circuit, that is to say, to discharge, which leads to the start of a new pumping process with the recurrence of EMR Episode.

The realization of this idea happens with a comparator circuit, that for the practically powerless recording of one Used a differential level compared to the voltage value one end of the load transistor and the other end a negative feedback stage and preferably between the differential stage and negative feedback stage uses a current mirror stage. The control electrode of a first one Load transistor, which is a transistor with high input impedance, e.g. is a MOS transistor, the one to be compared Voltage supplied. The control electrode of a second load transistor becomes a Reference voltage supplied, due to which this load transistor has a constant Represents load impedance. The second load transistor is a third load transistor connected in parallel depending on the output signal of the Comparator conducts or blocks, so that the impedance of the second load transistor a further load impedance depending on the output signal of the comparator is connected in parallel or not.

A differential stage in the basic circuit is known per se see. US-A 3,938,055 or JP-A 58 202 613.

Use of such a comparator circuit in context with a voltage control circuit is specified in dependent claim 3. According to claim 15, the comparator circuit according to the invention is at a control circuit can be used.

Further developments of the comparator circuit according to the invention are in the Claims 2 and 4 to 15 indicated.

Fig. 1

ein elektrisches Schaltbild, teilweise in Blockdarstellung, einer erfindungsgemäßen Pumpspannungsregelungsschaltung;

Fig. 2

ein Schaltbild einer hysteresebehafteten Komparatorschaltung, die bei der Pumpspannungsregelungsschaltung der Figur 1 verwendbar ist; und

Fig. 3

Spannungsverläufe, die bei der Komparatorschaltung nach Figur 2 auftreten

The invention will now be explained in more detail by means of embodiments. In the accompanying drawings:

Fig. 1

an electrical circuit diagram, partially in block diagram, of a pump voltage control circuit according to the invention;

Fig. 2

a circuit diagram of a hysteresis comparator circuit which can be used in the pump voltage control circuit of Figure 1; and

Fig. 3

Voltage curves that occur in the comparator circuit according to FIG. 2

Figure 1 shows a circuit diagram of a pump voltage control circuit with a supply voltage connection VA to which the high potential VS is supplied to a supply voltage source. Between the supply voltage connection VA and a first input E1 one Comparator COM is a series connection of two diodes D1 and D2. The anode of D1 with VA and the cathode of D2 connected to E1. A second input E2 of the comparator COM is with a parallel connection of two reference resistors RREF1 and RREF2 connected. These are, after all, ground potential connected while at the other end they are connected to E2, RREF1 direct and RREF2 via a first switch S1. A circuit node K between the two diodes D1 and D2 is on one side of a pump capacitor CP connected, the other side to an output of an oscillator OSC is connected, which when switching on a second switch S2 a pump pulse sequence with a pump frequency supplies. Is located between the diode D2 and the first input E1 a parallel connection of a load capacitor CL and a Load resistance RL, which is the input capacitance and the input resistance the load to be fed with the pump voltage, in the case of called NMOS transistor whose gate capacitance or gate input resistance, represent.

If the switch S2 is closed, the pump pulse sequence causes in itself a known way of charging the pump capacitor CP to a Pump voltage VP, which is about twice the supply voltage VS is. If the desired pump voltage is reached, the Switch S2 opened to end the pumping process, the discharges Pump voltage across the load resistor RL. Is the pump voltage VP falls below a predetermined threshold, is by Closing, i.e. switching switch S2 to on, means a new pumping process began.

When a pumping process can be ended and when a new one Pumping process is required, using the comparator COM determined, of which occurs at a comparator output A. Output signal it depends on whether this output signal is the switch S2 switches conductive or non-conductive. To regarding the pump voltage VP to achieve two-point control is the comparator with hysteresis behavior educated. For this purpose, the two reference resistors are RREF1 and RREF2 are provided, of which depending on the position of switch S1 only the reference resistor RREF1 or the parallel connection from the two reference resistors RREF1 and RREF2 takes effect. Since the input resistance RL of the NMOS transistor is very high, the time intervals between the times, to which a pumping process by closing switch S2 will be very large if the input resistance of the Input E1 of the comparator COM is also very large. Between there is no pump voltage operation at these long intervals, the pump oscillator can thus be switched off, so that between no EMR occurs during these long time intervals.

An embodiment of an inventive hysteresis Comparator, which loads the pump voltage source as little as possible shown in Figure 2 and includes the dashed part of the in Figure 1 circuit shown.

The hysteresis comparator COM according to FIG. 2 comprises a cascade connection between one supplying the positive supply voltage VS. Supply voltage connection VA and the negative pole of the Supply voltage source forming ground connection GND a differential stage D, a load impedance stage located on the high potential side of D. L, a negative feedback stage located on the low potential side of D. G and between D and G a current mirror stage S.

The differential stage D has a first differential stage transistor QP1, a second differential stage transistor QP2 and a first current source I1 on. QP1 and QP2 are each as a bipolar PNP multi-collector transistor trained with two collectors. The basic connections of QP1 and QP2 are connected to GND together via the first current source I1. One of the two collectors of each of the two differential stage transistors QP1 and QP2 is with the common base connection connected.

The current mirror stage S has a current mirror circuit with a Current mirror diode QN1 in the form of a bipolar connected as a diode NPN transistor and a current mirror transistor QN2 in the form of a bipolar NPN transistor. In the usual way for current mirrors the basic connections of QN1 and QN2 connected to each other.

The negative feedback stage G has a first negative feedback resistor R1 and a second negative feedback resistor R2.

The load impedance stage L has a first load transistor MN1 in Form of an N-channel MOS transistor, a second load transistor MP1 in the form of a P-channel MOS transistor and a third load transistor MP2 in the form of a P-channel MOS transistor. In addition, the Load impedance stage L a reference voltage source V1, which between the Gate of MP1 and VS is switched, and a second current source I2, which is connected between the gate of MP2 and VS.

MN1, QP1, QN1 and R1 form a first series connection, while MP1, QP2, QN2 and R2 form a second series connection. R1 and R2 form negative feedback impedances for QP1 and QP2. MN1 forms a load impedance for QP1. The load transistors connected in parallel MP1 and MP2 together form a load impedance for QP2.

A circuit node SK is located between QP2 and QN2 the base of a bipolar NPN switching transistor QN3 is connected. Its emitter is connected to GND while its collector both with the gate of MP2 and with the second current source I2 connected is. A common connection point between the power source I2, gate of MP2 and collector of QN3 forms the comparator output A.

The load impedance formed by the first load transistor MN1 is of pump voltage VP present at the first comparator input E1. The through the parallel connection of the two load transistors MP1 and MP2 formed load impedance at the emitter of QP2 depends on Potential at the comparator output. MP1 is using the reference voltage source V1 permanently in a certain state of conduct held, so permanently has a constant predetermined impedance on, also referred to below as the first reference load impedance becomes. The third load transistor MP2 is depending on the one at the comparator output A occurring potential switched conductive or non-conductive. Its impedance, hereinafter also referred to as the second reference load impedance, depends on the potential at comparator output A. Is MP2 switched non-conductive, the effective load impedance at the emitter of QP2 practically formed only by the constant impedance of MP1. If MP2 is switched on, the effective one at the emitter of QP2 Load impedance through the parallel connection of the first and second reference load impedance educated. Depending on the potential at the comparator output A therefore, a lower or a higher load impedance acts on the emitter of QP2.

Between the supply voltage terminal VA and the gate of MN1 is a protection diode D3 to protect the gate-source path by MN1 against overvoltages that come across the supply voltage connection VA could be supplied.

In Figure 1, the impedance of the conductive load transistor MP2 is through RREF2 is shown while the impedance of the permanently conductive Load transistor MP1 is represented by RREF1. The switch S1 in Figure 1 is by the load transistor MP2 operated as a switch indicated.

With the help of Figure 3, the mode of operation of the in Figure 2 considered comparator circuit. This will start with assumed an operating state in which the pump voltage VP is below the desired voltage value, as is initially the case when the power supply is switched on. This Time period is identified in Figure 3 with T1.

In order to achieve an increase in the pump voltage VP, the pump pulse sequence must can reach the pump capacitor CP in Figure 1.

A potential value must therefore be available at comparator output A, which controls the switch S2 in Figure 1 in the conductive state, thus controls the oscillator in the on state.

The impedance of the load transistor MN1 depends on the current one Voltage value of the pump voltage at comparator input E1 VP from. This pump voltage determines the value of the gate-source voltage VGS from MN1. Assuming VP is big enough to to drive the load transistor MN1 into the conductive state at all, the lower the impedance, the greater the load impedance formed by MN1 Pump voltage VP is and the lower, the higher the pump voltage VP is. The load impedance formed by MN1 therefore sets Measure for the respective existing value of the pump voltage VP. Da the pump voltage VP is applied to the gate of a MOS transistor the instantaneous or actual value is recorded and evaluated the pump voltage VP practically without power. The pump voltage source, namely the pump capacitor CP, is by this type Actual value acquisition is therefore practically not loaded and unloaded.

The impedance value representing the respective actual value of the pump voltage of MN1 is compared to the reference impedance, as ever after switching state of the third load transistor MP2 by the load impedance of MP1 alone or the parallel connection of the load impedances is formed by MP1 and MP2. Since the pump voltage VP after Turning on the supply voltage increases, which is formed by MN1 Load impedance thus decreases accordingly, that at the emitter effective load impedance of QP2 must be correspondingly lower than that Impedance of MN1, which is present as long as the pump voltage VP has not yet reached the desired voltage value or setpoint. The comparator circuit therefore behaves in the phase in which the Pump voltage VP is still below the desired value, asymmetrical, since the two differential stage transistors QP1 and QP2 Difference level D different load impedances are offered. Since the load impedance effective at the emitter of QP2 is lower than the load impedance acting on the emitter of QP1 flows through QP2 more electricity than through QP1. The one on the SK circuit node from the collector The current supplied by QP2 is therefore higher than that via the current mirror stage S current supplied to the circuit node SK from the collector of QP1. In addition, the voltage drop across the negative feedback resistor R2 greater than the voltage drop across the negative feedback resistor R1, which leads to an increase in the potential at the circuit node SK. These two phenomena cause the switching transistor QN3 to turn on is so that a low potential occurs at its collector, which leads to the conduction of the third load transistor MP2. At the emitter of QP2 thus becomes the parallel connection from the first one formed by MP1 Reference load impedance and the second one formed by the conductive MP2 Reference load impedance effective.

Since the pump voltage VP is too low at the collector of QN3 and so that there is a low potential at the comparator output A is entire control circuit so that at low potential at Comparator output A a pump pulse train on the pump capacitor CP is given.

At some point during its rise, the pump voltage VP becomes like this large that the value of the impedance from MN1 to that impedance value has dropped from the parallel connection of the first and second reference load impedance results. At that moment the Comparator circuit symmetrical behavior. If minor further increase in the pump voltage value this symmetrical behavior is lost again, the comparator output A goes into the other of the two possible states: The comparator output A takes high potential. This is because the one that is effective on the emitter of QP1 Load impedance value has become lower than that at the emitter of QP2 effective load impedance value and accordingly that of QP1 current flowing has become higher than the current flowing through QP2. The current balance at the circuit node SK is reversed accordingly and because of the decreased current through QP2 the voltage drop is across the negative feedback resistor R2 and thus that Potential dropped at circuit node SK. As a result, locks the switching transistor QN3. On the one hand, this leads to the already mentioned high potential value at the comparator output A and on the other hand to Block the third load transistor MP2. From this point on, Emitter of QP2 only the constant first formed by MP1 Reference load impedance effective.

Due to the transition of the potential at the comparator output A to The further loading of the pump capacitor becomes a high potential value CP in Figure 1 prevented with pump pulses.

This state is reached at the end of time period T1 in FIG. 3. While No pump pulses occur in the subsequent time period T2 on, the pump voltage VP remains during a first section T2a of the period T2 practically constant and the potential is at the comparator output A, designated VSA in FIG. 3, is high Value.

Since MOS transistors do not have an infinitely high gate-source input resistance and possibly due to other influences there may be a gradual discharge of the pump capacitor CP and thus a gradual drop in the pump voltage value come. With the pump voltage becomes the gate of a MOS transistor is controlled and the actual value measurement of the pump voltage is adjusted accordingly the comparator circuit according to the invention by applying the Gates of a MOS transistor with the pump voltage is performed the period of time during which the T1 reached at the end of the period Pump voltage value has dropped significantly, usually very long. However, in order to be able to use FIG. 3 to show what happens when the Pump voltage value after reaching the setpoint by a predetermined Amount has dropped, is in the second subsection T2b in Figure 3 assumes that the pump voltage value drops rapidly. This leads to a corresponding increase in those formed by MN1 Load impedance. If this matches the first reference load impedance formed by MP1 has risen and only slightly more increases, the comparator circuit tilts back into the one initially considered State in which the potential at the comparator output A is low Potential value. This state is at the end of the period T2 reaches and leads to the pump capacitor CP now again pump impulses are applied. During a period of time in Figure 3 is designated T3, the pump voltage value increases due to this application of CP with pump pulses again until on End of the period T3 at which the value of that formed by MN1 Load impedance back to the value of that of MP1 and the conductive MP2 commonly formed reference load impedance has dropped into the State of high potential at comparator output A, which leads to Blocking the application of CP leads to further pump pulses. This state persists during the period T4 in FIG. 3.

1 and the comparator circuit according to FIG. 2 containing pump voltage control circuit thus effects a two-point control between a high pump voltage threshold and a low pump voltage threshold, which in Figure 3 with VPH or VPL are designated. The one leading to this two-point control Hysteresis is caused by the controllable switching on and off of the Impedance formed by MP2 to or from that formed by MP1 permanent, constant load impedance.

Previously, the comparator circuit according to Figure 2 was part considered a pump voltage control circuit. This comparator circuit but can also be used advantageously for other purposes. It is suitable for any application in which an input variable compared to a hysterical reference variable with practically no performance shall be. Because the gate with the size to be measured of a MOS transistor, such becomes practical powerless measurement of those of interest or to be monitored Size possible.

In the comparator circuit according to the invention, not only one practically powerless measurement of the monitored or regulated Achieve voltage value but you can use it for the control process easily program the determining threshold through the Selection of the voltage value of the reference voltage source V1. At a Comparator circuit of this type designed as an integrated circuit you could provide several reference voltage sources that you ever according to the threshold value required in the special case by programming could make selectable.

I_{D MN1}

= I_{D MP1}

V_{DS MN1} - V_{DS MP1}

= V_DS

V_{th MN1}

= V_{th MP1} = V_th

V_{GS MN1}

= a*V1

V_{GS MP1}

= V1

βMN1

V1 - V_th - V_DS * 0,5

βMP1

a * V1 - V_th - V_DS * 0,5

The use of multi-collector transistors for QP1 and QP2, in each of which a collector is connected to the base, leads to a high transconductance or steepness due to the resulting non-linear diode behavior of each of the two differential transistors QP1 and QP2 at their emitters, so that by means of the difference stage D very small voltage differences can be determined, and thus very small differences in the load impedances that act on the emitter of QP1 or on the emitter of QP2. Therefore, with the same drain currents, the drain-source voltage of the first load transistor MN1 must be equal to the drain-source voltage of the second load transistor MP1 in order to achieve balanced conditions at the current mirror stage S. The gate-source voltage of MP1 is given by the reference voltage V1 of the reference voltage source. In simplified equations for unsaturated CMOS transistors, the threshold potential required to reach the high potential at the comparator output A can be calculated as a multiplier factor a of the reference voltage V1, with the assumptions listed below.

I _{D MN1}

= I _{D MP1}

V _{DS MN1} - V _{DS MP1}

= V _DS

V _{th MN1}

= V _{th MP1} = V _th

V _{GS MN1}

= a * V1

V _{GS MP1}

= V1

βMN1

V1 - V _th - V _DS * 0.5

βMP1

a * V1 - V _th - V _DS * 0.5

I_{D MN1}, I_{D MP1}

= Drainstrom von MN1 bzw. MP1

V_{DS MN1}, V_{DS MP1}

= Drain-Source-Spannung von MN1 bzw. MP1

V_{th MN1}, V_{th MP1}

= Schwellenspannung von MN1 bzw. MP1

V_{GS MN1}, V_{GS MP1}

= Gate-Source-Spannung von MN1 bzw. MP1

V1

= Referenzspannung der Referenzspannungsquelle

β

= Transkonduktanz (Steilheit) eines MOS-Transistors

β_MN1, β_MP1

= Transkonduktanz von MN1 bzw. MP1

W

= Kanalbreite

L

= Kanallänge

In the above formulas:

I _{D MN1} , I _{D MP1}

= Drain current of MN1 or MP1

V _{DS MN1} , V _{DS MP1}

= Drain-source voltage of MN1 or MP1

V _{th MN1} , V _{th MP1}

= Threshold voltage of MN1 or MP1

V _{GS MN1} , V _{GS MP1}

= Gate-source voltage of MN1 or MP1

V1

= Reference voltage of the reference voltage source

β

= Transconductance (slope) of a MOS transistor

β _MN1 , β _MP1

= Transconductance of MN1 or MP1

W

= Channel width

L

= Channel length

The ratio of the transconductances must be used to determine the threshold value of MN1 and MP1 can be set using the respective W / L ratio. The threshold value can therefore be dependent on the channel widths and the channel lengths of the two CMOS transistors MN1 and MP1 can be selected.

A hysteresis can be achieved by parallel to the second Load transistor MP1, the third load transistor MP2 is switched, the Channel type is also opposite to that of MN1 and where it is is a transistor with a P-channel. The amount of hysteresis can also be selected by selecting the length and width of the channel become.

In the context of the invention, it is not necessary to use the transistors Comparator circuit all with the channel type or conductivity type too choose as indicated in Figure 2. You need one instead of one positive pump voltage, which is assumed in Figure 2, a negative pump voltage, you can use the comparator circuit shown in Figure 2 reverse in that you put the load transistors on the ground side (GND) and chooses opposite channel type, where one for the transistors of the differential stage D and the current mirror stage S selects corresponding transistors of opposite conductivity type.

Claims (17)

1. A hysteresis comparator circuit for ascertaining in virtually power-free manner a voltage value to be used for a comparison, comprising a differential stage (D) that is part of a cascade circuit (L, D, S, G) having on one side of the differential stage (D) a load stage (L) with load transistors (MN1, MP1) and having on the other side of the differential stage (D) a negative feedback stage (G), with the control electrode of a first load transistor (MN1), which is a transistor with high input impedance, having the voltage applied thereto that is to be used for the comparison, and the control electrode of a second load transistor (MP1) having a reference voltage applied thereto on the basis of which this second load transistor (MP1) forms a constant load impedance, and with the second load transistor (MP1) having a third load transistor (MP2) connected in parallel thereto that is in the conducting or blocking state depending on an output signal of the comparator circuit, so that in accordance with the output signal of the comparator circuit, the impedance of the second load transistor (MP1) has an additional load impedance connected in parallel thereto or no such connection is made.
2. The comparator circuit of claim 1,
   wherein a current mirror stage (S) is connected between differential stage (D) and negative feedback stage (G).
3. A hysteresis comparator circuit for use as a comparator stage and actuating signal generator of an electric voltage regulating circuit having a voltage source (CP) which delivers the voltage to be regulated and whose output voltage (VP) is variable by means of an actuating signal delivered by an output of the comparator circuit, said comparator circuit

   a) comprising a comparator input (EI) adapted to have the output voltage (VP) of the voltage source (CP) applied thereto and a comparator output (A) delivering the actuating signal;

   b) being fed by a supply voltage source having a first supply voltage pole (VS) and a second supply voltage pole (GND);
   wherein

   c) the differential stage (D) has a first differential stage transistor (QP1) and a second differential stage transistor (QP2) each having a control electrode, a first main path electrode and a second main path electrode,

   c1) the control electrodes thereof being coupled jointly to the second supply voltage pole (GND),

   c2) the first main path electrodes thereof being connected via a first load impedance and a second load impedance, respectively, to the first supply voltage pole (VS) each, and

   c3) the second main path electrodes thereof being each coupled via a negative feedback impedance to the second supply voltage pole (GND);

   wherein

   d) the first load impedance is produced by the first load transistor (MN1) which has a control electrode coupled to the comparator input (E1) such that the first load impedance is dependent on the output voltage (VP) of voltage source (CP),
   wherein

   e) a reference voltage source (VR) is connected between a control electrode of the second load transistor (MP1) and the first supply voltage pole (VS), said reference voltage source (VR) controlling the second load transistor (MP1) to the conducting state such that it has a predetermined first reference load impedance, and wherein

   f) the third load transistor (MP2) is adapted to be switched to the conducting or blocking state under the control of the actuating signal at comparator output (A), such that the third load transistor (MP2) is switched to the blocking state in case of an actuating signal occurring at comparator output (A) when the increasing output voltage (VP) of voltage source (CP) reaches an upper threshold value (VPH), and is switched to the conducting state in case of an actuating signal occurring at comparator output (A) when the decreasing output voltage (VP) of voltage source (CP) reaches a lower threshold value (VPL), thereby forming a predetermined second reference load impedance.
4. The comparator circuit of any of claims 1 to 3,
   wherein said first load transistor (MN1) is a MOS transistor.
5. The comparator circuit of any of claims 1 to 4,
   wherein the three load transistors (MN1, MP1, MP2) are each constituted by a MOS transistor whose gate electrodes form the control electrodes thereof.
6. The comparator circuit of claim 5,
   wherein the first load transistor (MN1) on the one hand and the second (MP1) and third load transistors (MP2) on the other hand are of different channel type.
7. The comparator circuit of claim 5 or 6,
   wherein the gate electrode of the third load transistor (MP2) is coupled to the comparator output (A).
8. The comparator circuit of any of claims 1 to 7,
   wherein the two differential stage transistors (QP1, QP2) are constituted by a bipolar transistor each.
9. The comparator circuit of claim 8,
   wherein the two differential stage transistors (QP1, QP2) are each connected on the emitter side to the associated load impedance and on the collector side to the associated negative feedback impedance (R1, R2).
10. The comparator circuit of claim 8 or 9,
    wherein a current mirror circuit (S) is disposed between the differential stage transistors (QP1, QP2) and the negative feedback impedances (R1, R2), said current mirror circuit (S) having a current mirror diode (QN1) connected between the first differential stage transistor (QP1) and the negative feedback impedance (R1) thereof and having a current mirror transistor (QN2) connected between the second differential stage transistor (QP2) and the negative feedback impedance (R2) thereof.
11. The comparator circuit of any of claims 8 to 10,
    wherein the two differential stage transistors (QP1, QP2) are each constituted by a multicollector transistor, a first one of said collectors being coupled to the respectively associated negative feedback impedance (R1, R2) and a second one of said collectors being coupled to the base of the respective differential stage transistor (QP1, QP2).
12. The comparator circuit of any of claims 3 to 11,
    wherein the control electrodes of the two differential stage transistors (QP1, QP2) are commonly connected via a first current source (I1) to the second supply voltage pole (GND).
13. The comparator circuit of any of claims 3 to 12,
    wherein the comparator output (A) is coupled to a connecting point (SK) between one differential stage transistor (QP2) and the associated negative feedback impedance (R2), and in case of interposition of a current mirror circuit (S), between this differential stage transistor (QP2) and the associated current mirror element (QN2).
14. The comparator circuit of claim 13,
    wherein a switching transistor (QN3) is connected between the connecting point (SK) and the comparator output (A), said switching transistor (QN3) having its control electrode connected to the connecting point, its main path connected between the control electrode of the third load transistor (MP2) and the second supply voltage pole (GND) and its main path electrode, which is connected to the control electrode of the third load transistor (MP2), to the comparator output.
15. The comparator circuit of claim 14,
    wherein the switching transistor (QN3) is constituted by a bipolar transistor having a conductivity type opposite to the conductivity type of the bipolar differential stage transistors (QP1, QP2) and having one of its main path electrodes connected on the one hand to the control electrode of the third load transistor (MP2) and on the other hand via a second current source (I2) to the first supply voltage pole (VS).
16. An electric regulating circuit comprising a comparator circuit according to any of claims 1 to 15.
17. A regulating circuit according to claim 16, for regulating a pumping voltage of a voltage pumping circuit that is higher than the supply voltage value of the first supply voltage pole (VS), to a predetermined pumping voltage value, wherein:

    a) the voltage pumping circuit comprises a pumping voltage accumulator (CP) adapted to have applied on its input side a charging alternating current voltage (OSC) via a controllable pumping circuit switch means (S2), with the accumulated pumping voltage increasing when the pumping circuit switch means (S2) is controlled to its conducting state, and decreasing in accordance with a specific discharging time constant when the pumping circuit switch means (S2) is not controlled to its conducting state; and

    b) a switching control input of the pumping circuit switch means (S2) is coupled to the comparator output (A) and an output of the pumping voltage accumulator (CP) delivering the pumping voltage (VP) is coupled to the comparator input (E1).

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