EP0667061A1 - Systeme asservi en phase - Google Patents

Systeme asservi en phase

Info

Publication number
EP0667061A1
EP0667061A1 EP94925338A EP94925338A EP0667061A1 EP 0667061 A1 EP0667061 A1 EP 0667061A1 EP 94925338 A EP94925338 A EP 94925338A EP 94925338 A EP94925338 A EP 94925338A EP 0667061 A1 EP0667061 A1 EP 0667061A1
Authority
EP
European Patent Office
Prior art keywords
frequency
pll
pll circuit
divider
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94925338A
Other languages
German (de)
English (en)
Inventor
Jens Hansen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HuC Elektronik GmbH
Original Assignee
HuC Elektronik GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HuC Elektronik GmbH filed Critical HuC Elektronik GmbH
Publication of EP0667061A1 publication Critical patent/EP0667061A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
    • H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
    • H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
    • H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

Definitions

  • the invention relates to a PLL system of the type specified in the preamble of claim 1.
  • variable frequency for the mixer stage of the tuner changes the divider ratio of a PLL circuit whose fixed reference frequency is quartz-stabilized.
  • the frequency stabilized by a quartz is lower than the output frequency of the PLL circuit, which thus forms an integral multiple of the reference frequency.
  • the control loop contained in the PLL circuit oscillates, which in each case can last for a few milliseconds. During this time, it is not possible to specifically receive the signal from a particular transmitter.
  • the invention has for its object the possibility in a PLL system of the type mentioned to create, the frequency of which should be set to different transmission frequencies without a substantial time delay, in order to change, in particular, the set frequency of an FM receiver without the user noticing.
  • the invention includes, in particular, the knowledge that in two PLL circuits connected in series, the frequency divider effect is also cascaded, so that the first system acted upon by the quartz-stabilized reference frequency operates in a lower frequency range, while the second system operates at a higher frequency.
  • the higher-frequency system has a short settling time, while the lower-frequency system requires a longer settling time when the divider ratio changes, ie when the frequency changes. Since the higher-frequency system is connected downstream of the low-frequency one, short-term changes in the reception frequency can be made while maintaining the oscillation frequency of the low-frequency circuit and changing the divider frequency of the higher-frequency circuit without a noticeable disturbance in the program presentation (when changing to a transmitter with matching program information or switching back to the short-term one station received first).
  • the lower-frequency system stays steady, while the higher-frequency system always settles in again at short notice.
  • the division ratio of the second frequency divider to the essentially undelayed tuning to a frequency adjacent to the previously received frequency can be changed in particular by such an integer value that produces a frequency jump in the grid of the FM transmitter frequencies. In this way, a change between different predefined transmission frequencies can also take place in a predefined time grid (for example, scanning).
  • the division ratio of the frequency divider of the first PLL circuit is preferably greater than that of the frequency divider of the second PLL circuit, so that the transient range after a frequency change is kept relatively small and the transient process of the relevant PLL circuit is additionally accelerated. It is furthermore advantageous if the division ratio of the frequency divider of the first PLL circuit is essentially a thousand, preferably 1024 (as a corresponding power of two). In an advantageous application, the division ratio in the second PLL circuit is then essentially sixteen.
  • the control loop is not influenced by transition processes when the division ratio changes, but instead provides when the switch is closed again after completing the adjustment processes on the divider, it will be activated in a very short time.
  • two integration elements with different time constants are provided in at least one PLL circuit, the output signals of which can be alternately connected to the voltage-dependent oscillator by switching, control means being provided for the switch in such a way that To change the divider ratio of the frequency divider, the output of the integration element with the small time constant is first connected to the downstream voltage-dependent oscillator. First of all, a rapid settling of the control circuit in relation to the new frequency value is achieved.
  • the regulating voltage that arises (control voltage for the voltage-dependent oscillator) is still subject to disturbances (ripples).
  • the second integration element provided in parallel which was meanwhile still connected on the input side to the output of the phase comparison stage, has also almost reached its final state (corresponding to the steady state), this is - if necessary additionally - connected to the input terminal of the voltage-dependent oscillator, so that an operation free of interference amplitudes quickly sets in.
  • a switch between the output of the integration element and the voltage-dependent oscillator in at least one of the PLL circuits is provided for temporarily interrupting this connection and holding means for holding the input signal of the voltage-dependent oscillator during the change in the divider ratio of the frequency divider of the other PLL circuit and the subsequent transient process.
  • the voltage-controlled oscillator can be isolated from the rest of the circuit for the time of the frequency change, so that the transition and compensation processes associated with the change in the divider frequency of the frequency divider or the changeover of the reference frequency at the input of the PLL circuit do not interfere with the output signal.
  • the reference or control potential for the oscillator is obtained from the sample-and-hold circuit which is then in the "hold state". After the switchover has been completed, this circuit then returns to "sample mode" in order to be prepared for the next frequency change.
  • storage means can be provided for the control variable to be used in each case.
  • the control variable from a previous period of time at which the PLL system was set earlier to the frequency to be set after the frequency change will be recorded. In this way, the transient process will "self-learning" adapt to the current conditions.
  • Storage means are preferably digital storage or analog storage means for electrical voltages in the form of capacitances that take up variable charges.
  • selection means for the control variable in coordination with a selection variable for the control of a frequency divider of the associated PLL circuit are also favorable.
  • Another advantageous embodiment of the invention provides that the output signals of a plurality of first PLL circuits provided for different frequency values can alternatively be connected to the input of the second PLL circuit.
  • the two low-frequency (first) PLL circuits can alternately oscillate to the next frequency to be selected, while the other is active for controlling the second PLL.
  • FIG. 1 shows a block diagram of a first exemplary embodiment of the invention in use with an FM receiver
  • FIG. 2 shows a first time diagram for the exemplary embodiment according to FIG. 1
  • FIG. 3 shows a second time diagram for the same exemplary embodiment
  • FIG. 4 shows a block diagram of a further exemplary embodiment of the invention
  • FIG. 4a shows a detail of one of the exemplary embodiment according to FIG. 4,
  • FIG. 5 shows a first time diagram for the exemplary embodiment according to FIGS. 4 and 4a
  • Figure 6 shows a second timing diagram for the same exemplary embodiment
  • Figure 7 shows a third embodiment of the invention.
  • the PLL system shown in FIG. 1 is used to generate the mixing frequency for the mixing stage of the schematically illustrated FM receiver.
  • the FM receiver consists of a preliminary stage 1, to which the signal from an antenna 2 is fed.
  • the output signal of the preamplifier reaches a mixer 3, the output signal of which forms the intermediate frequency which is processed in the subsequent IF section 4.
  • the output signal of the IF part 4 is in turn fed to a demodulator 5, the de-odulator output signal being amplified in an NF stage 6 and presented to the user.
  • the difference frequency between the signal to be received and the IF frequency is fed to the mixer 3 as the mixing frequency, so that the mixing frequency M f determines the reception frequency.
  • the mixed frequency In order to ensure stable reception conditions, the mixed frequency must have a high stability, otherwise interference and reception distortion would result.
  • the PLL system which is described below, is used for this purpose.
  • the circuit shown here has two stages and consists of a first PLL circuit 7 and a second PLL circuit 8.
  • the two PLL circuits 7 and 8 are connected in series, the PLL circuit Circuit 7 operates in a lower frequency range and the PLL circuit 8 receives the output signal of the PLL circuit 7 at the input and generates the mixed frequency Mf as the output signal.
  • the reference frequency for the first PLL circuit 7 is approximately 6 kHz.
  • the reference frequency f re f is generated by a - not shown - quartz-stabilized oscillator, the higher-lying oscillation frequency of which is divided accordingly.
  • the reference frequency forms the input frequency for a phase comparison stage 71, at the second input of which the output signal of the first PLL circuit 7, which is divided down via a frequency divider 72, is compared with the reference frequency.
  • the output signal of the Pahsen comparator 71 is fed to an integration stage, which consists of a resistor R ⁇ and a capacitor C j .
  • the output signal of the integration stage is supplied as a voltage value to a VCO 73, which oscillates at a frequency that is around the factor n of the span voltage dividing circuit 72 is increased compared to the reference frequency.
  • the factor n is adjustable and determines the tuning frequency of the receiver.
  • the first PLL circuit 71 can be constructed from relatively inexpensive components for a frequency range of the output frequency around 6 MHz, the (changeable) frequency divider 72 in particular not forming a high-speed component needs.
  • the settling time of the PLL circuit 7 in the event of a frequency change by changing the reduction ratio of the frequency divider 72 is approximately 6 ms, so that no frequency change would be audible to the user. This behavior corresponds to that of known FM receivers.
  • the PLL circuit 7 is followed by a further PLL circuit 8, which operates in a higher frequency range.
  • the input frequency of approx. 6 MHz is increased by a fixed factor 16, so that the output frequency corresponds to approx. 100 MHz and is therefore in the VHF radio range, taking the IF frequency into account.
  • the function of a phase comparator 81 of the frequency divider 82 and of the voltage-dependent oscillator 83 corresponds to that of the corresponding components in the PLL circuit 7, the design only having to take into account the higher frequency range.
  • the frequency divider 82 is fixed and can therefore be obtained inexpensively despite the mode of operation in a higher frequency range.
  • the divider ratio is - as mentioned - fixed 16.
  • phase comparator 81 is followed by an integration element with respect to the voltage-dependent oscillator 83, which consists of the resistor R 3 on the capacitor C 3 .
  • a sample and hold circuit 84 which is controlled by a control signal S and a changeover switch 85, which is activated by a control signal S 2 , are switched into the signal path upstream of the voltage-dependent oscillator.
  • the two PLL circuits 7 and 8 could also be used in the cascaded embodiment in the receivers for tuning purposes without further customary use.
  • the settling time would always be noticeable, as is shown in FIG. 2 for a change in frequency from the frequency f ⁇ ⁇ to the frequency f for the PLL circuit 1 with 6 ms.
  • control signals required for this which are also shown in FIGS. 2 and 3, are emitted by a control module 9, which is indicated schematically in FIG.
  • the control signal S ⁇ _ (between times t and t) is activated for the time of the transient process of the first PLL circuit 8, as a result of which the sample and Hold circuit 84 responds and holds the current charging voltage of the capacitor C 3 of the corresponding timing element.
  • the transient response of the first PLL system 7 is not noticeable to the voltage-dependent oscillator 83, so that the mixing frequency Mf and thus the reception frequency is kept constant.
  • the remaining overshoot process can be reduced even further by additional circuit measures, as will now be described. This is to be done with reference to FIG. 3, where the frequency transition from the frequencies f 21 to f 2 of the second PLL system 8 is shown enlarged in time. Since the changeover switch S 2 in FIG. 1 is activated for a short period of time up to the time t 3 during the transient process of the second PLL system, that is to say after the time t according to FIG. 2, the input of the voltage-dependent oscillator 83 is switched over from the integration element R 3 / C 3 to a further integration element R 2 / C 2 , which is also connected on the input side to the output of the phase comparison circuit 81.
  • the above-mentioned circuit can effectively shorten the settling time of a PLL system, so that switching between PLL elements connected in parallel, which each have high-quality modules to cover the entire frequency range, must have rich, can be dispensed with.
  • switching between PLL elements connected in parallel, which each have high-quality modules to cover the entire frequency range, must have rich, can be dispensed with.
  • only a quartz-stabilized oscillator is required.
  • the frequency divider 82 in the second PLL circuit can also be changed in its divider ratio, so that the settling processes can generally be shortened without a sample-and-hold circuit 84.
  • the application of such a measure depends on the frequency ranges in which the output frequency of the PLL circuit is to be changed.
  • a device for the short-term detection of signal trains which are emitted by transmitters whose program is not currently being presented to the user, so that, for example, the reception quality of further transmitters as possible alternate transmitters during the current program can be monitored.
  • the time control device 9 For a jump back and forth to a transmitter of a different frequency, the time control device 9 must be activated for each frequency change, while at the time shown t ⁇ is set to a division ratio n which corresponds to the new frequency. The return occurs to the original frequency value.
  • a 100 kHz grid can be generated in a simple manner.
  • the steps 998 to 1002 of the first frequency divider multiplying these steps with 6.25 kHz and 16 results in the output frequencies 99.8 99.9 100.0 100.1 100.2 MHz.
  • a corresponding result is evidently always obtained when the product of the stabilized input frequency with the division ratio of the second PLL circuit is equal to the raster frequency, namely 100 kHz.
  • a corresponding result can now also be achieved if, when the jump distance of the first frequency divider is graded according to any integer, the product of the input frequency and division ratio of the second PLL circuit is divided by this jump distance.
  • FIG. 4 The block diagram of a further exemplary embodiment of the invention shown in FIG. 4 shows how the settling process of a PLL during the transition from one frequency to the next can be accelerated by specifying a fixed or previously determined offset voltage.
  • the stored offset voltage is added to the output voltage of the phase comparison stage and can preferably have been determined or updated during an earlier tuning process.
  • a variant of the first PLL circuit of the previous embodiment is shown. However, it can also be used as a second PLL in accordance with the respective frequency relationships.
  • the measures reproduced in this exemplary embodiment can, however, also be applied to a single-stage PLL circuit for any type of application where a fast frequency change of the PLL circuit with a short settling time is important.
  • the reference frequency f re f is fed to a phase comparator 101, the output signal of which is fed to a subsequent amplifier 104 via a low-pass filter formed from a series resistor 102 and a transverse capacitance 103, which amplifier is used to improve the signal-to-noise ratio - related to the subsequent sample-and-hold circuit 105 - provides.
  • the sample-and-hold circuit is activated briefly in time coordination with a frequency change for the period of the switching operations of the frequency dividers to be carried out (and described below) in order to avoid undefined transition processes.
  • the output signal of the downstream impedance converter 106 reaches a summing stage 107, the output signal of which in turn forms the input signal for the subsequent voltage-controlled oscillator 108.
  • the voltage controlled oscillator 107 in turn provides the desired phase controlled output frequency. For this purpose, this is fed as usual to the second input of the phase comparator 101 via a frequency divider 109.
  • a control circuit 110 which, on the one hand, emits different control signals n in succession to the frequency divider stage 109, which cause the frequency dividers to reduce the input frequency by a factor of n in each case.
  • a Timer III activates the sap-and-hold circuit 105 so that the subsequent possible detuning of the phase comparator 101 initially does not affect the VCO circuit.
  • the timer circuit is designed in such a way that the compensation processes occurring during frequency switching are kept away from the VCO.
  • the switchover process to a new frequency transmits an offset signal from a memory 116, which corresponds to the optimal - or a corresponding approximately optimal - value associated with this frequency.
  • the divider value n is transmitted to the memory 116 by the control circuit 110, which divider value n (for the sake of simplicity) forms an address in order to read out the associated offset value stored at the relevant address from the memory 116.
  • the read-out signal is emitted by the timing element 111 via a corresponding input of the memory.
  • the PLL-SW system swings to the new frequency in a very short time without overshoots of the output frequency occurring.
  • the reading out of the memory 116 is not activated, it is addressed via the inverter 115 by the output signal of the (also not activated) timer 112 for reading in, likewise at the memory location which is assigned to the current value of the divider ratio n.
  • the transition to the new frequency is carried out via an analog-digital converter 114 a digital data value corresponding to the current control voltage of the VCO 118 is written into the memory 116 and continuously updated, so that the next current frequency and memory location change the last current offset value remains in the addressed memory location and is available as an initial offset, when this frequency is selected again.
  • FIG. 4a shows a variant of a detail of the exemplary embodiment according to FIG. 4, a block being shown in broken lines between the sample-and-hold circuit 105 and the VCO circuit 108, which block practically summarizes the components 106 , 107 and 113 of Figure 4.
  • This block contains a controllable voltage divider, which optionally adds various current components of a positive bias voltage + U to the input signal supplied via the resistor R j or derives corresponding current components to ground, so that - with a corresponding (for example binary in two powers) gradation of the resistance values R 1; L j - ⁇ s
  • R 311 zw * R i2 ⁇ is R 32 - a variety of different (initial) offset values can be selected.
  • the respective resistance is activated by the respectively assigned switches S 1 to S 32 controlled by the control circuit 110 again in association with the selected division ratio of the frequency divider 109.
  • two first PLL circuits of low frequency 201 and 202 are provided, which are alternatively used to guide the downstream second PLL circuit.
  • Their internal frequency divider factors are set in time before the changeover (still in "idle mode") by the control circuit 203 to the value required for the output frequency required later.
  • the divisor value of the still activated PLL remains unchanged.
  • the switchover takes place by means of the switch 206 after the PLL that has settled to the value of the following guide frequency has stabilized, so that the subsequent (high-frequency) PLL can settle immediately and in a very short time with a fixed division ratio.
  • the PLLs 201 and 202 are operated with input frequencies increased by factors NL and N 2 , respectively, which are reduced by the frequency dividers 204 and 205 connected downstream by the PLLs by a corresponding frequency reduction be compensated. That way you can cheaper PLL circuits operating at higher frequencies are used, which also show (in absolute terms) faster transient response. This measure can also be used for the corresponding exemplary embodiments described above.
  • the downstream second PLL circuit works with the usual assemblies: phase comparison circuit 207, low-pass filter 208, 209, VCO 210 and frequency divider 211 of 1:16 at an input frequency of approximately 6 MHz and an output frequency of approximately 100 MHz. This is fed to mixer stage 212 of an FM receiver.
  • the circuit shown enables rapid frequency changes which make it possible to query certain reception criteria of other transmitters, while the signal of the station currently being received is not audibly impaired by the user, since the necessary transient processes of the receive PLL circuit are essential are shortened. In this way, the switchover to a possible alternative transmitter can be prepared in good time in the event of a serious reception disturbance of the currently received transmitter and the switchover can be initiated immediately.
  • the embodiment of the invention is not limited to the preferred exemplary embodiment specified above. Rather, a number of variants are conceivable which make use of the solution shown, even in the case of fundamentally different types.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

L'invention concerne un système asservi en phase, servant notamment à produire la fréquence de battement pour les étages de changement de fréquence d'un récepteur M.F. Un second circuit asservi en phase, ayant un signal de référence ou de sortie d'une seconde fréquence plus élevée, est intercalé à la suite d'un premier circuit asservi en phase ayant un signal de référence ou de sortie d'une fréquence plus basse, le signal de sortie du premier circuit asservi en phase étant acheminé sous forme de signal d'entrée au second circuit asservi en phase. Le rapport du signal de sortie du premier circuit asservi en phase à son signal de référence est déterminé par un premier diviseur de fréquence qui produit un signal de comparaison pour le circuit de comparaison de phases du premier circuit asservi en phase, à partir de ce signal de sortie. La fréquence du premier circuit asservi en phase est réduite d'une valeur correspondant au rapport déterminé par le premier diviseur de fréquence. Le rapport du signal de sortie du second circuit asservi en phase au signal de référence est déterminé par un second diviseur de fréquence qui produit un signal de comparaison pour le circuit de comparaison de phases du second circuit asservi en phase, à partir de ce signal de sortie. La fréquence du second circuit asservi en phase est réduite d'une valeur correspondant au rapport déterminé par le second diviseur de fréquence.
EP94925338A 1993-08-27 1994-08-29 Systeme asservi en phase Withdrawn EP0667061A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4329353A DE4329353A1 (de) 1993-08-27 1993-08-27 PLL-System
DE4329353 1993-08-27
PCT/DE1994/001007 WO1995006359A1 (fr) 1993-08-27 1994-08-29 Systeme asservi en phase

Publications (1)

Publication Number Publication Date
EP0667061A1 true EP0667061A1 (fr) 1995-08-16

Family

ID=6496475

Family Applications (1)

Application Number Title Priority Date Filing Date
EP94925338A Withdrawn EP0667061A1 (fr) 1993-08-27 1994-08-29 Systeme asservi en phase

Country Status (3)

Country Link
EP (1) EP0667061A1 (fr)
DE (1) DE4329353A1 (fr)
WO (1) WO1995006359A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19523433C2 (de) * 1995-06-28 1998-04-23 Telefunken Microelectron Schaltungsanordnung zur Frequenzumsetzung
DE19734656A1 (de) * 1997-08-11 1999-02-18 Alsthom Cge Alcatel Schaltungsanordnung zur Einstellung einer Systemfrequenz
DE19913110C1 (de) 1999-03-23 2000-11-16 Siemens Ag Frequenzsynthesizer
DE19959714C2 (de) * 1999-12-10 2001-11-29 Siemens Ag Taktsignal-Erzeuger-Umsetzer-Einrichtung

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4205272A (en) * 1977-04-13 1980-05-27 Trio Kabushiki Kaisha Phase-locked loop circuit for use in synthesizer tuner and synthesizer tuner incorporating same
FR2412981A1 (fr) * 1977-12-23 1979-07-20 Adret Electronique Synthetiseur de frequence a boucles multiples d'asservissement de phase, agence de facon a eviter toute discontinuite de frequence ou d'amplitude dans une large gamme de variation de frequence
FR2483704A1 (fr) * 1980-06-03 1981-12-04 Thomson Csf Dispositif de prepositionnement de frequence pour synthetiseur indirect de frequence et synthetiseur comportant un tel dispositif
JPS573438A (en) * 1980-06-06 1982-01-08 Fujitsu General Ltd Synthesizer type channel selector
EP0454917B1 (fr) * 1990-05-02 1994-08-17 Hewlett-Packard Limited Synthétiseur de fréquences
US5144254A (en) * 1991-09-30 1992-09-01 Wilke William G Dual synthesizer including programmable counters which are controlled by means of calculated input controls

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9506359A1 *

Also Published As

Publication number Publication date
WO1995006359A1 (fr) 1995-03-02
DE4329353A1 (de) 1995-03-02

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