EP0640261A1

EP0640261A1 - Data transmission delaying circuit using time-multiplexed latch enable signals

Info

Publication number: EP0640261A1
Application number: EP92913469A
Authority: EP
Inventors: Thomas Ebzery
Original assignee: VLSI Technology Inc
Current assignee: Philips Semiconductors Inc
Priority date: 1992-05-14
Filing date: 1992-05-14
Publication date: 1995-03-01
Also published as: WO1993023937A1; EP0640261A4

Abstract

A digital signal phase adjustment circuit adjusts the phase of a data signal in relation to a first local clock signal having a frequency of f. Also provided is a second local clock signal with a frequency of Nf, where N is a positive integer greater than 1. An N-bit shift register (120), clocked by the second local clock signal, generates N phase signals that are enabled in rotating sequential order during non-overlapping time intervals. One of the N phase signals is selected by a multiplexer (130) and used as the enable control signal for a data sampling circuit that is clocked by the second local clock signal. The data sampling circuit samples and outputs the data signal only when the selected phase signal is enabled, thereby outputting the data signal with a selected phase relative to the first clock signal.

Description

DATA TRANSMISSION DELAYING CIRCUIT USING TIME-MULTIPLEXED LATCH ENABLE SIGNALS

The present invention relates generally to digital phase delay circuits and particularly to methods and apparatus for adjusting the phase of a stream of data signals arriving at a destination circuit so as to synchronize the data stream with a local clock and/or to compensate for phase shifts caused by transmission of the data between circuits or systems.

BACKGROUND OF THE INVENTION

In many cases, streams of data are transmitted from a source to a destination over a path in which the delays to which the bit streams are subjected cannot be accurately controlled. Variable delays are introduced not only by differing lengths of the signal paths, but also by variations in the signal drivers and in the impedance of the signal paths. In order for the receiver at the destination to accurately recover the data, the individual data bits must be sampled by a clock at the receiver. This clock can have the same frequency as the transmitter, but the transmitter and receiver will not necessarily have the same phase, further exacerbating the problem of correctly receiving the data.

Some prior art phase adjustment circuits, such as the one shown in U.S. Patent 4,700,347, multiplex several delayed versions of the input data signal. The object of the present invention is to provide a phase shift or delay circuit with as few components as possible and which has high accuracy in terms of the amount by which an incoming data signal is phase shifted. SUMMARY OF THE INVENTION

In summary, the present invention is a phase adjustment circuit that adjusts the phase of a data signal in relation to a first local clock signal having a frequency of f . Also provided is a second local clock signal having a frequency of Nf , where N is a positive integer greater than 1. An N-bit shift register, clocked by the second local clock signal, generates N phase signals that are enabled in rotating sequential order during non-overlapping time intervals. One of the N phase signals is selected by a multiplexer and used as the enable control signal for a data sampling circuit that is clocked by the second local clock signal. The data sampling circuit samples and outputs the data signal only when the selected phase signal is enabled, thereby outputting the data signal with a selected phase relative to the first clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:

Figure 1 is a block diagram of a phase adjustment circuit in accordance with the present invention.

Figure 2 is a logic circuit diagram of a preferred embodiment of the present invention.

Figure 3 is a timing diagram representing operation of the logic circuit shown in Figure 2.

Figure 4 is a block diagram of a phase adjustment circuit used for sampling a multiplicity of data input signals. DESCRIPTION OF THE PREFERRED EMBODIMENT

Figure 1 shows a phase adjustment circuit 100 that samples a data signal on line 102 with a specified phase shift from the nominal phase of a clock signal CLK, and outputs the sampled signal on Data Out line 104. The phase adjustment circuit 100 receives from a clock generator 106 (which may be internal or external to the circuit 100) a clock signal CLKN having a frequency Nf which is N times the frequency f at which the Data In signal is to be sampled. A counter 110 is used as a divide-by-N circuit to generate a second clock signal CLK with frequency f from the high frequency clock signal CLKN.

Before normal operation of the phase adjustment circuit 100 can begin, a Reset signal on line 112 is generated by the Reset Signal Generator 114. The Reset signal coordinates the operation of the phase adjustment circuits components.

An N-bit shift register 120 is preloaded by the Reset signal with a data pattern of "00...01" so that only the last bit of the register is set to a value of "1". The shift register 120 is clocked by the high frequency clock signal CLKN, and generates N "phase signals" on N parallel output lines qO to qN-1. At any given time, only one of the N phase signals is enabled while the others are disabled. This one "1" bit in the register 120 is shifted by one position each cycle of the CLKN signal, and after reaching the last bit position in the shift register is it recycled back to the first bit position to begin the cycle again. The N phase signals are thus enabled in rotating sequential order during non-overlapping time intervals of duration 1/Nf. Each phase signal on lines qO to qN-1 represents a particular 1/N phase of the CLK clock signal and has a duty cycle of 1/N (i.e., each phase signal is ON for just one of each N cycles of the CLKN signal).

A phase select value on line 122, provided by an external system, user, or circuitry not part of this invention, is stored in register 124. The phase select value is an integer between 0 and N-1 that identifies the time (or phase) at which the Data In signal on line 102 is to be sampled with respect to the CLK signal. The phase select value stored in register 124 can be reloaded at the rising edge of clock CLK, but will typically be changed infrequently.

Multiplexer 130 uses the stored phase selection value, received from register 124, to select one of the N phase selection signals produced by the shift register 120. That is, the multiplexer 130 selects one of the N lines qO to qN-1 and transmits the signals on the selected phase signal line to enable line 132. The phase select value determines which of the N lines becomes the multiplexer's output. For example, if the phase select value is equal to "3", then the signal on line q3 from the N-bit shift register 120 will be passed through as the output of the multiplexer 130. The output of multiplexer 130 becomes the input enable signal for flip-flop 140.

Flip-flop 140 samples the Data In line 102 at the rising edge of the CLKN signal only when the enable signal on line 132 is high (equal to " 1 ") . Since the enable signal on line 132 is high during only one of every N cycles of the CLKN signal, the Data In signal is sampled at the frequency f of the CLK signal, but with a phase relative to the CLK signal determined by the phase select signal. The resultant Data Output signal has a fundamental frequency of 1/f, but is phase shifted from the CLK signal by the selected phase. This output relationship is better viewed in the timing diagram of Figure 3, as discussed below.

Figure 2 shows a logic circuit diagram of the preferred embodiment of the phase delay circuit 100. A 3-bit Counter 110 is used as a divide-by-8 frequency divider for generating the CLK clock signal. The multiplexer 130 comprises a decoder 200, eight AND gates 201-208 and an OR gate 209.

Shift register 120 in the preferred embodiment has eight flip-flops 210-217 with the last flip-flop's output connected to the shift register's serial input. The lines carrying the outputs of the shift register, herein called phase signals, are labelled qO to q7. Note that the choice of eight as the length of the shift register 120 should not be construed as a limitation on the present invention, as any whole number greater than 1 would suffice. At any one time, only one of the eight flip-flops 210-217 stores a "1", and all the others store a value of "0". Since the shift register 120 is clocked by the CLKN signal at a rate of Nf, the phase signals on lines qO to q7 are enabled in rotating sequential order during non-overlapping time intervals of duration 1/Nf.

The three-bit phase selection value stored in register 124 is decoded into eight binary signals by a decoder 200 in the multiplexer 130. In accordance with the stored phase selection value, the decoder 200 outputs a "1" on just one of the decoders eight output lines zO to z7, and outputs a "0" on all the others. As a result, seven of the AND gates 201-108 are disabled and only one is enabled. For example, if the phase selection value is equal to "011 " (i.e., "3" in base 10), the decoder 200 will output a "1" on line z3, enabling only AND gate 204. The one enabled AND gate and OR gate 209 pass the corresponding phase signal onto the data sampling enable line 132. The overall operation of the multiplexer 130 is to select the phase signal on just one of the shift register output lines qO to q7 and to output that selected phase signal as the input enable signal for flip-flop 140.

Flip-flop 140 samples the Data In line 102 at the rising edge of the CLKN signal only when the enable signal on line 132 is high (equal to "1 "). Referring to the timing diagram in Figure 3, if the phase selected value is "3", then the phase signal on line q3 becomes the input enable signal, and therefore the Data In signal is sampled at the rising edge of the CLKN signal occurring near the end of each pulse of the q3 phase signal. Note that the q3 phase signal is slightly delayed by its passage through the multiplexer 130, and therefore the enable line 132 is still high (equal to "1") when the next CLKN clock cycle begins.

The Reset signal is provided to coordinate the CLK signal with the phase signals. Referring to the timing diagram of Figure 3 and the logic circuit shown in Figure 2, it can be seen that the negative-logic Reset signal sets phase signal on line q7 and resets all the other phase signals on lines qO to q6. The Reset signal also loads a value of "011 " into the three-bit counter 110. The first rising edge of CLKN after expiration of the Reset signal causes the counter 110 to count to a value of "100", causing its output signal, CLK, to go high. The same rising edge of the CLKN signal also causes the shift register 120 to shift its contents one position, enabling the phase signal on line qO and disabling the other phase signals. Thus, the Reset signal acts to set the states of the CLK signal and the phase signals from the shift register 120 to a predefined starting state. As a result, the phase selection value stored in register 124 defines a data sampling time relative to the rising edge of the CLK signal as follows:

Data Sample Time = tax + (Phase Selection Value + 1)/8f

where tc_LK is the time associated with the rising edge of the CLK signal. Clearly, by connecting the decoder outputs differently (i.e., zO to AND gate 208, z1 to AND gate 201, z2 to AND gate 202, and so on) the "+1" could be eliminated from the above timing equation.

It should be noted that by using the phase signals on lines qO to q7 as input enable signals, and not using a selected one of these phase signals as the clock for sampling the input data, the phase delay circuit 100 has high accuracy in terms of the amount by which an incoming data signal is phase shifted. The exact point at which the data is sampled is defined by the rising edge of the circuit's master clock signal, CLKN, which by definition is periodic and used to define the timing of the circuit's operation. This is true regardless of the phase selected. Furthermore, in applications in which several data input signals are sampled at different points of an integrated circuit (see Figure 4), the same set of phase signals can be used over the entire integrated circuit without sacrificing the accuracy of the sampling phase shift. The timing of the rising edge of the selected phase signal, which may be affected by the length of its transmission path, is not critical because it does not control when the input signals are sampled. It is only the overlap of the selected phase signal with the rising edge of the CLKN signal that determines the point at which the input signals are sampled, and therefore the precise time (within the selected 1/Nf time slot) at which the input signals are sampled is controlled by the CLKN signal alone. While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. Apparatus for adjusting, in relation to a first local clock signal having a frequency of f, the relative phase of a data signal, comprising: clock means for generating a second local clock signal with a frequency of Nf, where N is a positive integer greater than 1; an N-bit shift register clocked by said second local clock signal, said N-bit shift register generating N phase signals that are enabled in rotating sequential order during non-overlapping time intervals of duration 1/Nf; a multiplexer having N input ports coupled to said N-bit shift register to receive said N phase signals and having an output port that outputs a selected one of said N phase signals; and a data sampling circuit clocked by said second local clock signal, wherein said data sampling circuit samples and outputs said data signal only when said selected one of said N phase signals is enabled, wherein said data signal is output by said data sampling circuit with a selected phase, relative to said first clock signal.

2. The apparatus of claim 1 , including phase selection means, coupled to said multiplexer, for selecting the one of said N phase signals to be output by said multiplexer.

3. The apparatus of claim 1, wherein said data sampling circuit is a latch that samples said data signal at a predefined transition of said second local clock signal only when said selected one of said N phase signals is enabled.

4. The apparatus of claim 1 , said clock means including a divider circuit for generating said first local clock signal.

5. A method of adjusting a digital signal's phase in relation to a first local clock signal having a frequency of f, the steps of the method comprising: receiving a second local clock signal with a frequency of Nf; generating N phase signals that are enabled in rotating sequential order during non-overlapping time intervals of duration 1/Nf, each of said N phase signals having a predefined phase relative to said first clock signal; where N is a positive integer greater than 1; selecting one of said N phase signals; and sampling said data signal, upon a predefined transition in said second local clock signal, only when said selected one of said N phase signals is enabled, and outputting said data signal's sampled value; whereby said data signal is sampled with a selected phase, relative to said first clock signal.

6. The method of claim 5, wherein said generating step includes enabling successive ones of said N phase signals at each occurrence of said predefined transition in said second local clock signal.