JP2774380B2 - Data transmission delay circuit using time multiplexed latch enable signal - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to digital phase delay circuits, and more particularly to synchronizing a data stream with a local clock and / or phase shift due to transmission of data between circuits or systems. A method and apparatus for adjusting the phase of a stream of data signals arriving at a destination circuit to correct for phase shifts.

BACKGROUND AND OBJECTS OF THE INVENTION In many cases, a stream of data is transmitted from a source to a destination over a path where the bit stream cannot accurately control the delay of interest.
Variable delay is introduced not only by differences in signal path length, but also by variations in signal drive and signal path impedance. In order for the destination receiver to accurately recover the data, the individual data bits are
Must be sampled by a clock at the receiver. This clock can have the same frequency as the transmitter, but the transmitter and receiver do not need to have the same phase, further exacerbating the problem of receiving data accurately.

Prior art phase adjustment circuits, such as those shown in U.S. Pat. No. 4,700,347 (Japanese Patent Application Laid-Open No. 62-23647), multiplex multiple delayed versions of an input data signal. An object of the present invention is to provide an input data signal (incoming d).
It is an object of the present invention to provide a phase shift or delay circuit which has a high accuracy with respect to the amount by which the ata signal is phase shifted and has as few components as possible.

SUMMARY OF THE INVENTION In summary, the present invention is a phase adjustment circuit that adjusts the phase of a data signal for a first local clock signal having a frequency of f. Further, the present invention also provides a second local clock signal having a frequency of Nf, wherein N is a positive integer greater than one. The N-bit shift register, clocked by the second local clock signal, has a non-overlapping time interval (non-overlapping).
rotation intervals during time intervals) (r
Generate an N-phase signal that is enabled in otating sequential order. One of the N phase signals is selected by a multiplexer and is used as an enable control signal for a data sampling circuit clocked by a second local clock signal. The data sampling circuit samples and outputs the data signal only when the selected phase signal is enabled, thereby outputting a data signal having the selected phase with respect to the first clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS Further objects and features of the present invention will be more readily understood from the embodiments and claims described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a phase adjustment circuit according to the present invention.

FIG. 2 is a logic circuit diagram of the preferred embodiment of the present invention.

FIG. 3 is a timing chart showing an operation of the logic circuit shown in FIG.

FIG. 4 is a block diagram of a phase adjustment circuit used to sample the multiplicity of the data input signal.

Embodiment FIG. 1 shows a standard phase (nominal phas) of a clock signal CLK.
FIG. 3 shows a phase adjustment circuit 100 that samples the data signal on line 102 with the specified phase shift from e) and outputs the sampled signal on Data Out line 104. FIG. The phase adjustment circuit 100 outputs a clock signal CLKN having a frequency Nf that is N times the frequency f at which the Data In signal is sampled (which may be internal or external to the circuit 100). From reception from clock generator 106. The counter 110 starts the normal operation of the phase adjustment circuit 100 used as a divide-by-N circuit for generating the second clock signal CLK having the frequency f from the high frequency clock signal CLKN. Next, a reset signal (Reset signal) on line 112 is generated by a reset signal generator (Reset Signal Generator) 114. The reset signal coordinates the operation of the phase adjustment circuit components.

The N-bit shift register 120 is preloaded with a reset signal having a data pattern of "00 ... 01" so that only the last bit of the register is set to a value of "1". The shift register 120 is clocked by the high frequency clock signal CLKN and has N "phase signals".
On the N parallel output lines q0 to qN-1. At any given time, only one of the N phase signals is enabled (enabled) and the other phase signals are disabled. This one "1" bit in register 120 is shifted by one position in each cycle of the CLKN signal, and after reaching the last bit position in the shift register, the first bit is used to restart the cycle. To the bit position of N phase signals are therefore possible (enable) in rotational sequential order during a non-overlapping time interval of duration 1 / Nf.
To be. Each phase signal on lines q0-qN-1 represents a particular 1 / N phase of the CLK clock signal and has a 1 / N duty cycle (ie, each phase signal
ON for exactly one of each N cycles of the CLKN signal).

Circuits supplied by external systems, users, or circuits not part of this invention
The phase selection value on 122 is stored in register 124. The phase selection value is determined by the data in (Data In) signal on line 102 being CL
Time (or phase) sampled for K signal
Is an integer between 0 and N-1 that identifies Register 12
The phase selection value stored in 4 can be reloaded on the rising edge of clock CLK, but is typically changed infrequently.

The multiplexer 130 selects one of the N phase selection signals generated by the shift register 120,
The stored phase selection value received from the register 124 is used. That is, the multiplexer 130 includes N lines q0 to qN
-1 and transmits the signal on the selected phase signal line to the enable line 132. The phase selection value is
Determine which of the N lines will be the output of the multiplexer. For example, if the phase selection value is equal to "3", the signal on line q3 from N-bit shift register 120 is passed as the output of multiplexer 130.
The output of multiplexer 130 is the input enable signal for flip-flop 140.

Flip-flop 140 samples Data In line 102 on the rising edge of the CLKN signal only when the enable signal on line 130 is high (equal to "1"). Since the enable signal on line 132 is high during only one of every N cycles of the CLKN signal, the Data In signal is
Sampled at the frequency f of the signal, but with a phase with respect to the CLK signal determined by the phase select signal. The resulting Data Output signal has a fundamental frequency of 1 / f but is phase shifted from the CLK signal by the selected phase. This output relationship will become more apparent in the timing diagram of FIG. 3 described below.

FIG. 2 is a logic circuit diagram of the preferred embodiment of the phase delay circuit 100. 3-bit Counter 110
Is an eight-divided frequency divider (d
ivide-by-8 frequency divider).
The multiplexer 130 includes a decoder 200, eight ANDs (AN
D) Gates 201 to 208 and an OR (OR) gate 209 are provided.

The shift register 120 of the preferred embodiment has eight flip-flops 210-217 with the output of the last flip-flop connected to the serial input of the shift register.
The lines that carry the output of the shift register, referred to herein as phase signals, are labeled and labeled q0-q7. It should be noted that the choice of 8 as the length of the shift register 120 should not be construed as a limitation in the present invention, but that any natural number of one or more is sufficient. At any one time, only one of the eight flip-flops 210-217 stores a "1" and all other flip-flops store a value of "0". Shift register
Since 120 is clocked by the CLKN signal at a rate of Nf, the phase signals on lines q0-q7 have a duration of 1 / Nf
Are enabled (enabled) on a rotational sequential order during the non-overlapping time interval.

The 3-bit phase selection value stored in the register 124 is decoded by the decoder 200 of the multiplexer 130 into eight binary signals. The stored phase selection value allows the decoder
200 outputs "1" to only one of the eight output lines z0-z7 of the decoder and outputs "0" to all other output lines. As a result, seven of the AND gates 201-208 are disabled (disabled) and only one is enabled (enabled).
To be. For example, if the phase selection value is “011” (ie, 10
If it is equal to the base "3"), the decoder 200
"1" is output to enable only the AND gate 204. One enabled AND and OR gate 209 passes the corresponding phase signal on the data sampling enable line 132. The overall operation of the multiplexer 130 is to select a phase signal on exactly one of the shift register output lines q0-q7 and predominantly use the selected phase signal as an input enable signal to the flip-flop 140.

Flip-flop 140 samples Data In line 102 on the rising edge of the CLKN signal only when the enable signal on line 132 is high (equal to "1"). Referring to the timing diagram of FIG. 3, if the phase selection value is "3", the phase signal on line q3 will be the input enable signal, and thus the Data In signal will be the signal of the q3 phase signal. CLKN occurring near the end of each pulse
Sampled on the rising edge of the signal. It should be noted that the q3 phase signal is somewhat delayed by its passage through multiplexer 130, so that enable line 132 is still high (equal to "1") when the next CLKN clock cycle begins.

A reset signal is provided to match the CLK signal to the phase signal. Referring to the timing diagram of FIG. 3 and the logic circuit shown in FIG. 2, the negative logic reset signal (nega
tive-logic Reset signal) sets the phase signal on line q7 and resets the other phase signals on lines q0-q6. The reset signal also loads the 3-bit counter 110 with a value of “011”. The first rising edge of CLKN after the expiration of the Reset signal causes the counter 110 to count a value of "100" and cause its output signal, CLK, to go high. The same edge of the CLKN signal causes the shift register 120 to shift its content by one position,
Enable (enable) the phase signal on q0 and disable (disable) the other phase signals. Hence,
Reset signal is CLK signal and shift register
It acts to set the state of the phase signal from 120 to a predetermined disclosure state. As a result, the phase select value stored in register 124 defines the data sampling time with respect to the rising edge of the CLK signal as follows: data sample time = t _CLK + (phase select value + 1) / 8f where: t _CLK is the time associated with the rising edge of the CLK signal. Obviously, by connecting the decoder output differently (ie, z0 for AND gate 208, z1 for AND gate 201, z2 for AND gate 202, etc.), +1 can be eliminated from the above timing relationship.

By using the phase signals on the lines q0 to q7 as input enable signals, and not using selected ones of these phase signals as clock signals for sampling input data, the phase delay circuit 100
It should be noted that the incoming data signal has a high degree of accuracy with respect to the amount of phase shift. The exact point at which data is sampled is defined by the rising edge of the circuit's master clock signal, CLKN, which is by definition periodic and used to define the timing of circuit operation. This is true regardless of the phase selected. Further, in applications where multiple data input signals are sampled at different points in the integrated circuit (see FIG. 4), the same set of phase signals is used throughout the integrated circuit without sacrificing sampling phase shift accuracy. be able to. The timing of the rising edge of the selected phase signal, which can be affected by the length of its transmission path, is not critical because it does not control when the input signal is sampled Because.
Only the overlap of the selected phase signal with the rising edge of the CLKN signal determines the point at which the input signal is sampled, and therefore, the exact time at which the input signal is sampled (within the selected 1 / Nf time slot). Time is controlled only by the CLKN signal.

Although the invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as a limitation of the invention. Various modifications will occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Continuation of front page (58) Fields investigated (Int.Cl. ⁶ , DB name) H04L 7/02 H03K 5/135

Claims (6)

(57) [Claims] An apparatus for adjusting a relative phase of a data signal in relation to a first local clock signal having a frequency of f, wherein N is a positive integer greater than one; Clock means for generating a second local clock signal having a frequency of Nf; clocked by said second local clock signal and enabled in a rotational sequential order during a non-overlapping time interval of duration 1 / Nf. An N-bit shift register for generating an N-phase signal; an N-input port coupled to the N-bit shift register for receiving the N-phase signal; and an output for outputting a selected one of the N-phase signals. A multiplexer having a port; and a data sampling circuit clocked by the second local clock signal; Road, the N said data signal and output sampling vital only when a selected one of the phase signal is enabled, the data signal with respect to said first clock signal,
Apparatus characterized by being output by the data sampling circuit at a selected phase. 2. Apparatus according to claim 1, including phase selection means coupled to said multiplexer for selecting one of said N phase signals to be output by said multiplexer. 3. The data sampling circuit is a latch that samples the data signal at a predetermined transition of the second local clock signal only when the selected one of the N phase signals is enabled. The device according to claim 1, characterized in that: 4. The apparatus according to claim 1, wherein said clock means includes a frequency divider for generating said first local clock signal. 5. A method for adjusting a phase of a digital signal with respect to a first local clock signal having a frequency of f, comprising: receiving a second local clock signal having a frequency of Nf; The local clock signal is a positive integer where N is a positive integer greater than 1 each having a predetermined phase with respect to the first clock signal and a non-overlapping time interval of duration 1 / Nf. To generate a select signal that is enabled during one of the non-overlapping time intervals of duration 1 / Nf, each of which is transmitted on a separate corresponding signal line. Selecting the N-phase signals in combination; and sampling the data signal only when the selected one of the N-phase signals is enabled; Comprising the step of outputting a sampled value of items, said data signal, with respect to said first clock signal,
A method characterized by being sampled at a selected phase. 6. The converting step includes enabling, on each occurrence of a predetermined transition of the first local clock signal, a next one of the N phase signals of a next one of the separate signal lines. The method of claim 5, wherein: