EP0092211B1 - Electronic time-programme commutating device - Google Patents

Abstract

PCT No. PCT/EP83/00107 Sec. 371 Date Dec. 20, 1983 Sec. 102(e) Date Dec. 20, 1983 PCT Filed Apr. 18, 1983 PCT Pub. No. WO83/03688 PCT Pub. Date Oct. 27, 1983.A time-programming apparatus comprises a central processor which includes at least one recording/readout working memory having addressable registers, computing means with at least one logic circuit connected to the working memory for processing output signals therefrom, and at least one program memory with associated program counter connected to the logic circuit for the generation and distribution of function signals for the central processor. The apparatus further comprises a luminous digital display connected to the processor and divided into subregions with respective display fields for alphanumeric display, input means including manually actuatable keys and switches assigned to the display fields, and output means for selective actuation of a load to be operated, the input and output means being connected to the central processor and all including the luminous display, with a wall provided therefor, being contained in a common housing. Power means in the housing supplies electric power to the central processor, the input means being so connected to the processor as to define hierarchical functioning and including first and second function-selection means and a further selection means.

Description

The present invention relates to an electronic time program switching device according to the preamble of claim 1.

The requirements for a time program switching device, previously mainly time switches with electromechanical drive and mechanical switching devices, such as radially displaceable switching segments, pluggable switching fingers, or the like, have recently become increasingly high. So now and in the future there will probably be more demands that at least several time switch programs, i.e. with differences in different days of the week and also for several switching channels with partially different time switching programs should be as easy and error-free to set.

Electronic time switches with more complicated and multi-time and channel programs have recently come onto the market (US-A-4 004 085); in these it has been shown that incorrect entries are possible in several ways and then problems in correcting them occur because, for. B. whole sections of the switching program deleted and the relevant switching data must be entered again and each from the front. So with the well-known electronic timer «GRÄSSLIN digi 127», because a numeric keypad is provided for the input of the switching time data, it is also possible to use illegal time data, e.g. To enter 26.84 with day of the week «9»; Although this error is indicated by flashing, it still requires the entire time entry to be deleted and re-entered in a fixed, prescribed order, i.e. starting from the beginning.

In addition, in the known time switch, the switching data record cannot be entered and displayed completely, but only a partial section thereof, e.g. with a single day of the week, either an ON switching time or an OFF switching time; Combinations e.g. of several days of the week with the same ON and OFF switching times are neither possible in the display nor can they be checked at the same time. A pattern for a programming sheet is therefore included in the operating instructions.

The invention is therefore based on the object of improving a time or time program switching device according to the preamble of claim 1 and its assemblies, i.e. the display device for the ON and OFF switching times with any number of days of the week and, if necessary, different switching channels - optionally adjustable in any change of the sections of the complete data set - combined with the operating elements and intermediate memories so that they can be controlled and designed so that the individual switching times and secondary data can be configured can be entered in any order and inputs of inadmissible switching time data are excluded from the outset, incorrect or no longer required input data of switching times can be corrected in individual sections and complete data sets with ON and OFF switching times, weekday (s) and secondary data, as desired, for example selected switching channels or choice between ON or OFF switching time, can be clearly read and set or corrected during the entire setting process.

This object is achieved according to the invention in a time switch with the features according to the preamble of claim 1 by connection to the sub-features according to the characterizing part of claim 1. This conveys technical progress that in the entire handling, i.e. the creation, supplementation, partial deletion and correction of an ON and OFF switching time pair, the overview of the entire associated data set including the weekdays and switching channels belonging to this pair, a constant monitoring of all setting measures to a high degree and thus the operation without any special Training and demands on the skill of the operator is possible. The advantages that can be achieved in this way are further promoted by configurations in connection with further special features, in that the functional reliability, which is otherwise only achievable to a limited extent, is even better guaranteed with such a highly developed and versatile time switch.

• Fig. 1:
  • a) die Draufsicht auf den Zeitschalter mit geschlossenem Gehäuse,
  • b) einen Teilschnitt in Längsrichtung,
  • c) die Draufsicht auf das nichtbestückte Gehäuse bzw. dessen Oberteil mit beschrifteter Abdeckmaske auf dem Bedienfeld;
• Fig. 2:
  • a) die Draufsicht auf das nichtbestückte Oberteil ohne Abdeckmaske mit Schnitt-Angaben,
  • b) einen abgesetzten Längsschnitt C-D zur Wiedergabe von Einzelheiten der Schalterhalterung bzw. Tastenführung,
  • c) einen Teilschnitt mit Leiterplatte (vgl. Fig. 1b),
  • d) einen abgesetzten Teilschnitt A-B vor allem zur Darstellung der Führungsrippen für die Tastenstifte,
  • e) die Unteransicht des Gehäuse-Oberteils mit den innen einstückig angeformten Führungsrippen für die Tastenstifte;
• Fig. 3:
  • einen Längsschnitt des aus Gehäuse-Unterteil und darauf aufgesetztem Oberteil zusammengebauten eigentlichen Gehäuses mit dazwischen eingeklemmter Leiterplatte mit angedeuteter Bestückung derselben und Abdeckung des Gehäuse-Unterteils durch ein topfförmiges Abdeckgehäuse mit ausbrechbaren Wandteilen für die Durchführung von Anschlussleitungen;
• Fig. 4: eine Variante der Frontansicht bei anderer Gehäuseform bzw. anderer Taster-/Schalter-Bestükkung
  • a) mit übereinander benachbarten und in der Breite aneinander angepassten Anzeige- und Bedienungsfeldern, sonst jedoch gleicher elektronischer Ausstattung wie im Ausführungsbeispiel der Fig. 1a (Stunden, Minuten, Sekunden, vier Kanäle)
  • b) mit ähnlicher Frontplatten-Gestaltung wie in Fig. 1a, jedoch mit dieser gegenüber abgerüsteter elektronischer Ausgestaltung, d.h. für Zeitanzeige von Stunden und Minuten und im z. B. Sekundentakt blinkenden Doppelpunkten, sowie für maximal zwei Kanäle; bei einkanaliger Ausführung fehlen die gestrichelt markierten Teile;
• Fig. 5:
  • a) einen Querschnitt G-H (vgl. Fig.2a) durch das Gehäuse-Oberteil,
  • b) einen Querschnitt E-F (vgl. Fig.2c) do., mit aufgesetztem topfförmigen Abdeckgehäuse und angedeuteter Bestückung mit der Leiterplatte,
  • c) einen Querschnitt 1-K (vgl. Fig. 2e) do.;
• Fig. 6:
  • a) die Unteransicht des Gehäuse-Unterteils,
  • b) einen Längsschnitt E-F (vgl. Fig. 6c),
  • c) die Draufsicht auf das Gehäuse-Unterteil;
• Fig. 7:
  • a) einen Längsschnitt A-B durch das Gehäuse-Unterteil (vgl. Fig. 6c)
  • b) eine Seitenansicht desselben in Pfeilrichtung N,
  • c) einen Querschnitt I-K,
  • d) d. G-H,
  • e) einen Längsschnitt C-D,
  • f) eine Seitenansicht in Pfeilrichtung O;
• Fig. 8:
  • a) einen Querschnitt J-K durch das topfförmige Abdeckgehäuse (vgl. Fig. 8d),
  • b) einen Längsschnitt A-H (vgl. Fig. 8d),
  • c) einen Querschnitt L-0 do.,
  • d) eine Draufsicht auf das Innere des Abdeckgehäuses;
• Fig. 9:
  • a) eine Unteransicht des Abdeckgehäuses,
  • b) eine Vorderansicht davon;
• Fig. 10:
  • ein stark vereinfachtes Blockschaltbild mit den wichtigsten elektronischen Baugruppen;
• Fig. 11:
  • eine schematische Übersicht über die Aufteilung des Gesamt-Blockschaltbildes mit logischen Verknüpferstufen - hier als UND- bzw. ODER-Glieder für Parallel-Datenverarbeitung - und die Zusammengehörigkeit der Teil-Blockschaltbilder a) bis d):
    • a) die Untergruppe mit den Funktionswahl-Tasten,
    • b) die Untergruppe mit den Stelltasten und dem festformatierten Datensatzspeicher,
    • c) die Untergruppe mit der UND-Verknüpfungs-Gruppe für die Ein- und Ausgänge von Eingangsspeichern der Anzeigeeinrichtung und
    • d) die Untergruppe mit elektronischer Uhr-Baugruppe und arithmetisch logischen Rechner-Einheiten (LE) mit zugehörigen UND-Verknüpfungsgliedern;
• Fig. 12:
  • einen Prinzip-Blockschaltbild-Ausschnitt aus einem Beispiel für logische Seriell-Verknüpfungsstufen mit Schieberegistem bei dem Vergleich von Datensatz-Abschnitten;
• Fig. 13:
  • einen Prinzip-Blockschaltbild-Ausschnitt aus einem dem Beispiel von Fig. 12 entsprechenden Beispiel bei Auswertung der Stelltasten-Codes;
• Fig. 14:
  • ein Prinzip-Blockschaltbild für ein Ausführungsbeispiel mit Bedienfeld-Matrix für Funktionswahl- Schalter und -Tas,ter, sowie Stelltaster und Mikroprozessor mit arithmetisch-logischer RechnerEinheit, Pufferspeichefrn, Eingangs- und Ausgangs-Registem, Schreib-Lese-Arbeits- und Programmspeichenn usw.
• Fig. 15:
  • auszugsweise ein Flussdiagramm des Ausführungsbeispieils der Schaltuhr gemäss Fig.4b mit eingefügten Leuchtziffer-Einrichtungs-Display-Anzeigen für einzelne Betriebszustände mit Anzeige der Schaltzeiten für EIN- und AUSSchaltung und der laufenden Ulmzeit, der gewählten Wochentage und Schaltkamale, sowie der Symbole «∥» und «O» für die EIN- und AUS-Schaltzeiten;
• Fig. 16:
  • Beispiele für Anzeige der Wochentage:
    • a) Einstellung von zwei Tagen
    • b) Ergänzung eiiner bereits worliegenden Einstellung und Reihenfolge der Betätigung der Taster hierfür
    • c) fehlenden Einstellung der EIN-Schalttage
    • d) do. der EIN- und AUS-Schalttage
    • e) Zahl der eingestellten EIN-Schalttage grösser als diejenige der AUS-Schalttage
    • f₁) Positionieren und Quittieren der Schaltkanäle
    • f₂) fehlende Einstellung des zweiten Schaltkanals (nur bei Zeitkanal-Schaltuhr)
• Fig. 17:
  • Blockschaltbild für ein Ausführungsbeispiel der Kompatibilitäts- (Plausibilitäts-)Prüfung der eingegebenen Daten eines kompletten SOLL-Schaltzeiten-Datensatzes vor der Übernahme aus dem festformatierten Datensatzspeicher in den Schreib-/Lese-Arbeitsspeicher.

The embodiments of the invention are the subject of the dependent claims. Exemplary embodiments are described below with reference to the drawing; it represents:

• Fig. 1:
  • a) the top view of the timer with the housing closed,
  • b) a partial section in the longitudinal direction,
  • c) the top view of the unequipped housing or its upper part with a labeled mask on the control panel;
• Fig. 2:
  • a) the top view of the non-equipped upper part without a mask with cut information,
  • b) a stepped longitudinal section CD for reproducing details of the switch holder or button guide,
  • c) a partial section with printed circuit board (see FIG. 1b),
  • d) a stepped partial section AB, above all to show the guide ribs for the key pins,
  • e) the bottom view of the upper housing part with the integrally molded guide ribs for the key pins;
• Fig. 3:
  • a longitudinal section of the actual housing assembled from the lower part of the housing and the upper part placed thereon, with a printed circuit board clamped in between with indicated mounting thereof and covering the lower part of the housing by a pot-shaped cover housing with break-out wall parts for the implementation of connecting lines;
• Fig. 4: a variant of the front view with a different housing shape or different pushbuttons / switches
  • a) with display and operating fields which are adjacent to one another and match the width, but otherwise have the same electronic equipment as in the exemplary embodiment in FIG. 1a (hours, minutes, seconds, four channels)
  • b) with a similar front panel design as in Fig. 1a, but with this compared to disarmed electronic design, ie for time display of hours and minutes and in z. B. Flashing colons every second, and for a maximum of two channels; in the single-channel version, the parts marked with dashed lines are missing;
• Fig. 5:
  • a) a cross section GH (see FIG. 2a) through the upper housing part,
  • b) a cross section EF (see FIG. 2c) do., with a pot-shaped cover housing and indicated mounting of the printed circuit board,
  • c) a cross section 1-K (see Fig. 2e) do .;
• Fig. 6:
  • a) the bottom view of the lower housing part,
  • b) a longitudinal section EF (see FIG. 6c),
  • c) the top view of the lower housing part;
• Fig. 7:
  • a) a longitudinal section AB through the lower housing part (cf. FIG. 6c)
  • b) a side view of the same in the direction of arrow N,
  • c) a cross section IK,
  • d) d. GH,
  • e) a longitudinal section CD,
  • f) a side view in the direction of arrow O;
• Fig. 8:
  • a) a cross section JK through the cup-shaped cover housing (cf. FIG. 8d),
  • b) a longitudinal section AH (see FIG. 8d),
  • c) a cross section L-0 do.,
  • d) a top view of the interior of the cover housing;
• Fig. 9:
  • a) a bottom view of the cover housing,
  • b) a front view thereof;
• Fig. 10:
  • a very simplified block diagram with the most important electronic components;
• Fig. 11:
  • a schematic overview of the division of the overall block diagram with logical logic stages - here as AND and OR elements for parallel data processing - and the correspondence of the partial block diagrams a) to d):
    • a) the subgroup with the function selection buttons,
    • b) the subgroup with the setting keys and the permanently formatted data record memory,
    • c) the subgroup with the AND logic group for the inputs and outputs of input memories of the display device and
    • d) the sub-group with an electronic clock module and arithmetically logical computer units (LE) with associated AND logic elements;
• Fig. 12:
  • a schematic block diagram section of an example of logical serial link levels with shift registers when comparing data record sections;
• Fig. 13:
  • a basic block diagram section from an example corresponding to the example of FIG. 12 when evaluating the setting key codes;
• Fig. 14:
  • a basic block diagram for an embodiment with control panel matrix for function selection switches and buttons, as well as control button and microprocessor with arithmetic-logical computer unit, buffer memory, input and output registers, read-write work and program memory etc.
• Fig. 15:
  • a flow chart of the example of the timer according to Fig. 4b with inserted luminous digit device display for individual operating states with display of the switching times for ON and OFF switching and the current elm time, the selected days of the week and switching times, as well as the symbols «∥» and «O» for the ON and OFF switching times;
• Fig. 16:
  • Examples for displaying the days of the week:
    • a) Setting two days
    • b) Supplementing an already existing setting and sequence of pressing the buttons for this
    • c) Missing setting of the ON switching days
    • d) do. the ON and OFF switching days
    • e) Number of ON switching days set greater than that of OFF switching days
    • f ₁ ) Positioning and acknowledging the switching channels
    • f ₂ ) missing setting of the second switching channel (only with time channel timer)
• Fig. 17:
  • Block diagram for an exemplary embodiment of the compatibility (plausibility) check of the entered data of a complete SET switching times data record before the transfer from the fixed data record memory into the read / write main memory.

In Fig. 1a, the top view - from the front as a front view - is shown on the timer with closed housing 1, from which one can see the division of the front panel 2 into the control panel 3 and the display panel 4. The control panel 3 itself is also divided into subfields 5 to 8 according to the outline of the control elements, the bottom 5 being the function selection main switch 9 “STEL / AUT” and the group of switching channel selection switches 10 to 13 (“S1 to S4”), the upper strip 14 of the keypad 6 “SET” the function selection button 15 (CLOCK), 16 (ON switching time) and 17 (OFF switching time), the middle strip 18 and the lower one Strip 19 the control button «h» 20 (hours), «m» 21 (minutes), «s» 22 (seconds), «d1-7» (weekdays), «S1-4 _" 24 (switching channels) and «Q» 25 (acknowledgment) are assigned, the last-mentioned button belongs to the possible type of single-digit entry in the two cases «d1-7» and «S1-4», in which the weekdays and the switching channels are repeated when the buttons are pressed associated data is shifted by one digit, ie the previously entered value is deleted and the character concerned is only transferred to the assigned buffer to the data that may already be stored there when the "Q" control button is pressed.

With the function selection button «S1-4 _" 26 in the control subfield 7 «Test» (ABFR) - also called «AS1» - the query is initiated, with the button «Check» (ABFR) 27 the actual query of the The complete data record provided is started and the queried section of the data record is deleted with the setting button 28 (Clear) (CLE). When the function _selection button 29 "P _ROGR " or "AUT" is _pressed , automatic operation is interrupted by one of the function _{selection buttons} 15, 16, 17 and 26 restored.

In the display field 4, the complete data record for a switching time pair - in the case of a query - or a part of it when entering for the first time after complete deletion - is displayed, with the switching time image in an upper half 30 for the ON switching time with a first symbol "I" 31 and a lower half 32, mirrored from top to bottom, is divided with a second symbol "0" 33 and each half except the times "h", "m" and "s" with a colon between the dates for " h »and« m », below or above the same bar code 35, 36 at seven adjacent positions corresponding to the days of the week and in the right part 37 of the display field 4 arrows one above the other, for example 38 for the display of the selected switching channels.

The special division of the operating (3) and display fields (4) gives the user a particularly easy and fail-safe setting of the timer data. In the routine selected with the "UHR" function selection button, he can set the built-in electronic clock by pressing the setting buttons 20 to 22 "h", "m" and "s", as well as "d1-7" for the day of the week that applies or press (for automatic pulse sequence) until the relevant section value matches the current time, whereupon he actuates the function selection button 29 "AUT" to transfer the set half data record to the intermediate memory 301 for the current time and release the continuation of the automatic operation of the electronic time program switching device and thus also enables the ongoing automatic adjustment of the built-in electronic clock.

For the purpose of setting the ON and OFF switching times, the user only has one of the function selection buttons «I» 16 and «O» 17 and then in turn - in any order - the setting buttons 20 to 25 for the associated switching times, days of the week and To actuate switching channels, also as long or as often until the desired values are displayed in the individual sections of the data record memory, if this is the case, he only has to press the function selection button 29 «AUT» or «PROGR», whereupon the Complete data record reproduced in display field 4 as associated digits, identifiers and symbols is transferred to the main memory (418) or its associated register and the «AUT» mode is also restored.

Here, however, the condition must be met that all sections of the complete data set, possibly also e.g. B. are entered as «zero» (00) - without pressing the set button 20 to 25 belonging to a section, there is no display at all - i.e. that the record is "complete". With a simplified version of the electronic time switch, this condition can also be limited to a “half data record”, in which case one is displayed alternately for the current time, for ON switching time and for OFF switching time - in a less simplified version, however, then Completeness condition is checked for the entire data set.

In addition to the current overview described, the geometric arrangement of the setting buttons 20 to 25 and the function selection buttons 15 to 17 and 29 also makes operation easier, because the function selection buttons 15 to 17 and 29 in a common line 39, the group of buttons 26 to 28 for the query, correction and deletion in sections, which also includes the total reset by means of the pushbutton 41 “Reset”, in a line 40 at right angles to it and the actual actuating buttons are accommodated in the subfield lying between them.

With the function selection main switch 9 in its "AUT" position, the entirety of all stored complete data records is secured against unauthorized and accidental change by the function selection buttons 15 to 17 and 26 and the setting buttons 20 to 25 being blocked as ineffective. The peculiarities of the electronic circuit are the subject of a separate and independent description of the same.

In Fig. 1b, a partial section in the longitudinal direction, the arrangement of the circuit board 51 is supported by self-aligning by means of clamping between ribs 52, which are integrally formed on the side wall 53 of the upper housing part, and the end faces of the side wall 54 of the lower housing part . The function selection and the setting buttons 55 to 58 are each from a neck, z. B. 53, of rectangular cross-section and a head plate 60 composed of a rubber-like material with additives made conductive and in its entirety by an elastic support surface 61 and integrally and integrally connected to it. When one of these buttons is actuated, the contact surface 61 is pressed onto the circuit board below the neck in question and the ends of conductor tracks applied at this point are thus conductively connected, ie the switch effect is brought about. The necks 55 to 59 are integrally formed by the webs underneath the front plate 2, for. B. 62, 63, and the support surface 61 by the integral integrally molded intermediate webs, for example 64 held at a precisely uniform distance from the front panel 2 self-adjusting.

In addition to the control panel 65, the semiconductor compact component 67 with the display device and associated electronic assemblies is installed directly under the window 68 in the front panel 2 in the display panel 66 and is electrically connected to the conductor tracks of the circuit board 51 by the associated connecting lugs. On the inside of the circuit board 51 are at right angles to it printed circuit boards 69, 70, as indicated, for mechanical stiffening and for mounting larger components, such as capacitors of the power supply part, a battery for power reserve, and the relays.

In Fig. 1c is the top view of the bare upper housing part 1 with holes 81, 82 for its screwing to the lower housing part, with openings for the window 83 belonging to the display device, for function selection and setting buttons, e.g. 84, 85, 86, function selector switch, e.g. 87, 88, and the masks 89, 90, 91 for the subfields 7, 7, 8 (in FIG. 1a).

Fig. 2a shows the bottom view of the upper housing part 101, the integrally molded frame 102 of the window 103 for the display device, not shown, and the holding frame 104 for this, as well as the openings, z. B. 105, for the necks not shown here, for. B. 106 belonging to a push button 107 (in Fig. 2c) and the combined to a latticework 108, namely integrally formed on the underside of the front plate 109 guide ribs, z. B. 110 to 113, on all four sides of the rectangular openings, for. B. 105, and with each other and with these integrally molded stiffening ribs, for. B. 114,115. In addition, you can still see on the inside of the walls, e.g. 116, 117, molded support ribs, e.g. 118, 119, for the circuit board 120 in Fig. 2a, b, c and d. Fig. 2e shows the top view of the completely unpopulated front panel 109 with the openings, z. B. 105 for a button neck, e.g. 106 and for a channel switch 121, as well as for the function selection main switch 122 («STEL / AUT»).

FIG. 3 shows a longitudinal section A-B, supplemented by a longitudinal section through the lower housing part 151 and a phantom longitudinal view of the cover housing 152, through the upper housing part, which is equipped with a compact semiconductor module 153 for the display device and a group 154 of setting buttons. The clamp fastening of the circuit board 155 between ribs, e.g. 156, which are integrally formed on the longitudinal side wall 157, and the lower housing part 151, namely its upper edge. Larger components, such as (again in phantom), relays 159 to 162, electrolytic capacitors 163, 164 and the other parts are arranged on the inside of the circuit boards 158, 159 which are attached at right angles to the underside of the circuit board on the longitudinal edges of the circuit board 155 of the power supply part 165. In this way, even with the new construction with digital electronics, a sufficiently dimensionally stable and space-saving design of the electronic timing device is possible despite its components, which are partially sensitive to changes in geometric dimensions. The phantom view also shows how the pot-shaped cover housing 152 is attached with the aid of clamping claws in the grooves with internal teeth 166, being put over the lower housing part.

4a shows a variant of the front view with a different housing shape, in which the display panels 181 and control panels 182 are arranged one above the other with abutting longitudinal edges (to be understood only conceptually). Otherwise, the explanations for Fig. 1a apply with regard to facilitating operation due to the geometric assignment of display field areas and switches or buttons according to their ranking, especially the increase in the displayed values per button or with a long press of a sequence, and for the days of the week and the channels of the ongoing forwarding each time the button is pressed and transferred to the programming memory only after the acknowledgment button is pressed, in the same way, so that further explanations are unnecessary. The electronic equipment and consequently the equipment of the front panel - apart from the local arrangement - corresponds to that of FIG. 1a.

The front view for an exemplary embodiment electronically disassembled in relation to FIG. 1a or FIG. 4a is shown in FIG. 4b. The numbers of the display 184, 185 of the ON switching time and corresponding to the OFF switching time indicate the hours or minutes, while the colons 186 arranged between them indicate the seconds or other sections of the minutes. The bars 187, 188 above and below the number line «1 ... 7» show the weekday selected by button «d1-7» (189) and permanently saved by pressing the acknowledgment button «Q» (190) , after which the subsequent bar flashes when the «d1-7» button is pressed and jumps one step at a time until the day in question is permanently saved when acknowledged by the «Q» button (190) and indicated by a constant light. The symbols «S», «L», «ix and« 2 »(191) belong to the switching channels, the symbols« I »and« O »(192, 193) show the selected part rate for setting the ON or OFF switching times.

With the «Check» button (194) the saved switching times are queried, with the «Clear» button (195) the polled switching times are deleted, by pressing the «Program» button (196) the (complete) data set is displayed in accordance with the switching time diagram in Display in memory; the button ("Clock picture") (197) is used to set the time that is constantly running in the background, the button "I / O" (198) to choose between "ON" and "OFF" switching times, and to start the Operation of the time switch for setting and automatic mode, switches 199 and 200 of the operating or channel switching optionally to «Set / Program» or «Automatic / independent of this». The parts with a dashed line are missing in the single-channel version of the time program switching device.

The cross sections GH, EF and LO in Fig. 5a, b and c, through the upper housing part 201, the one in Fig. 5b through the slipped cover housing 202 in an almost usual drawing and through the inserted lower housing part 203, 203 'Supplemented in a phantom manner, the various support, mounting and clamping aids in the form of ribs 206, connecting pieces 207, 208, etc., which are integrally formed in the housing front 204 or side walls 205, can be seen, as well as on the underside of the Front plate 209 integrally formed lattice of stiffening 210 and guide ribs 211, 212 and the receptacle 213 for the screw sleeve 214 also integrally molded on the cover housing 202. The printed circuit board 215 together with its side printed circuit boards 216, 217 is between the upper housing part 201 and the housing -Bottom part 203 using the ribs, e.g. 206 and 210 clamped in a correct and spaced manner. One side printed circuit board has a connector plug 219 on the part protruding from the floor.

The lower housing part (151 in Fig. 3) is shown with a bottom view, a longitudinal section E-F and a top view in Fig. 6a, b and c. Of particular note here is the height-offset form, which on the one hand offers a larger space for the power supply in the room part 221, while the elongated room part 222 offers space for connection plug strips, means for connecting the installation and the lower room part 225 for the larger components, such as electrolytic capacitors, batteries and relays is sufficient, on the other hand, the printed circuit board with the plug strip extends through the slot 223 in the intermediate floor 224. The grooves 226, 227 with offset toothed inner surfaces 228 and the integrally molded sleeves 229, 230 for screwing to the upper housing part are arranged on the side walls. The spacer rods 231, 232 for the self-adjustment of the distance and the position of the cover housing are also integrally formed on the underside of the intermediate floor 224.

In Fig. 7a for a longitudinal section AB, Fig. 7c a cross section IK, Fig. 7d for a cross section GH and Fig. 7e for a longitudinal section CD through the lower housing part and Fig. 7b for a side view in the direction of arrow N and Fig. 7f for a side view in the direction of arrow O on the lower housing part, the special features are identified in the same way as in FIG. 6, so that further explanations on this are unnecessary.

8 and 9 show the cover housing (202 in FIG. 5b) in cross sections JK (FIG. 8a), LO (FIG. 8c), in longitudinal section AH (FIG. 8b), in a top view of the interior (FIG. 8d ), repeatedly shown in bottom view (Fig.9a) and front view (Fig. 9b). The screw sleeves (214 in Fig.5b) are designated 241, 242, on the side walls are integrally molded ribs, z. B. 243, 244, for supporting the side walls of the lower housing part (FIGS. 6 and 7) on the lugs (233, 234) attached to the upper edge. Break-out opening areas 247 and 248, 249, 250 are provided in the floor 245 and in the front wall 246 for connecting lines and assembly. Other integral parts are e.g. the fitting parts 251 for the lower housing part.

The circuit-specific features are explained below with reference to FIGS. 10 to 14. 10 shows a greatly simplified block diagram with the most important electronic assemblies. It can be used to store the intermediate memory 301 for the sections 302 to 305 of the current time, which are connected as consecutive counters with the levels 60 (s), 60 (m), 24 (h) and 7 (d), both when the Set the drawn position of the switches 306 from the buffer 307 with a data record read in there to the current time, and also continuously feed the electronic clock module (buffer 301) from the frequency divider pulse source controlled by an oscillator 308, as well as the sections of the buffer Load 307 section by section from the data record memory 310, its sections being set by clock pulses from the clock generator 309 by actuating the setting key switches 311 and with changeover switches 311a set to ON or OFF switching times by means of clock pulses. Depending on the position of the changeover switches 311a, the positions “I” and “O” can be used to store two half-data records in succession from the programming memory and vice versa, depending on the position. The buffer memory 307 can be connected to the input memory 312 of a display device and to the main memory 313 via the line group 314.

In automatic operation, a complete data record is shoveled from the working memory 313 into the intermediate memory 307, while the current time is displayed by the display device. The latter and one of the two half-data sets for ON and OFF switching times are located in sections at the inputs of the arithmetic-logic comparator units 314a, which, in the case of equality, have a signal at their outputs via the AND logic elements 315, which are controlled (not shown in detail) the sections switch the switching devices together with the signal of the channel selection section 316 to ON and OFF operating states.

FIG. 11 shows a schematic overview of the division of the overall block diagram with logical logic levels - here as an AND or OR element for parallel data processing - and the association of the block diagrams 11a to 11d.

11a with the function selection buttons 321 (CLOCK) for the current time, 322 (ON), 323 (OFF) for the ON and OFF switching times, 324 (AS1 ...) for the query channel The area code and 325 (AUT) for taking over the automatic operation of the electronic time switch are located on one side at the clock pulse source T ₁ , T ₂ - which still has to be explained - and are on the output side via the AND gates with the complementary outputs Q the FLIP-FLOP elements 331 to 335 of the other function selection buttons are linked. The result of this is that the FLIP-FLOP element (eg 332) controlled by pressing the button (e.g. 322) is activated by its Q -Output blocks the inputs of all other FLIP-FLOP elements 331, 333, 334 and 335 through the AND elements 326, 328, 329 and 330 which have not been released.

H signals are present on the output lines 336 (UHR), 337 (AUT), 338 («I») and 339 («O») and 340 (AS1 ...) as long as no other function selection key than that of the set FLIP-FLOP element has been actuated. The function selection main switch "AUT / STEL" 341 is located at some point in the circuit, which achieves the same output effect as with the "AUT" function selection button 325 - but blocked. The switching channel setting switches 342 serve to block the control circuit of the switching devices in one of the operating states: remain ON, OFF or INACTIVE, in which they remain set.

The subgroup of FIG. 11b with the setting buttons 351 (weekday "d"), 352 (hour "h"), 353 (minute "m"), 354 (second "s"), 355 (switching channel "S1 ..." ), 356 (query "ABF"), 357 (acknowledgment, ie taking over the weekday or switching channel shift setting "QUI") and 358 (deletion "CLE") is on one side of the clock pulse source via line 359 and is with T ₁ or T ₂ connected - for which an explanation follows - and is located on the output side of an input of AND gates 360 to 367, while the other input (AUT) each at the Q Output (343 in FIG. 11 a) of the FLIP-FLOP element 335 assigned to the function selection button 325 “AUT”. As a result, all setting buttons of this group 351 to 358 are blocked as ineffective in automatic operation. The output signals for «d», «h», «m», «s», «SK» and «ABF» of the AND gates 360 to 365 drive the monostable FLOP gates 368 to 373, of which those 368 to 373 Deliver signals for further links.

The set outputs of the monostable FLOP elements 332 (ON) or (ON) and 333 (OFF) or (AUT) (FIG. 11a) are, as indicated by circles, for example 374, by NAND (or NEG) Gates 375, 376 are linked to the output signals of the FLIP-FLOP gates 368 to 372 so that they indicate output signals via FLIP-FLOP gates 379, 380 whether all of the relevant setting buttons 351 to 355 are actuated; only then is an H signal given both for the "ON" actuation routine and for the "OFF" one and passed on via the AND gate 377 on line 378 for a positive result of the completeness check. These output signals also control a time-delayed monostable FLOP gate, the complementary one, via the OR gate 381 Q -Output signal 382 is on the reset line 383 for the reset inputs. The «ABF» key 356 thus only reloads a data record stored in the working memory into the input memory 312 of the display device and thus interrupts the «AUT» routine if the «AS1 ...» function selection key has been pressed beforehand, ie A signal is present on line 384 and enables the forwarding of the “ABF” signal to line 366 via AND gate 385.

The actual record signals go from the relevant output of one of the AND gates 360 to 364 to the individually assigned buffer memories 387 to 391 of the data record memory 392 and set them to their corresponding values depending on the number of clock pulses entered; the buffer memory sections 387 and 391 are designed as sliding memories, so that after each input which is to be stored, this is entered into the actual register 387 'by a signal at the output of the AND gate 366 belonging to the acknowledgment actuating key «QUI» 357. or 391 '- if necessary in addition to the positions already occupied - must be stored. The data contents of the "Switching time" and "Switching channel" sections are taken from the outputs 393 and 394 of the data record memory 392.

As FIG. 11c shows, the function selection signals “I”, “O”, “AS1 ..”, 401 to 403 are “AUT” 404 and the actuating signal “ABF” 386, with the outputs “SZ” (switching times) 405 and «SK» (switching channels) 406 and OFF switching time 409, 410 of the auxiliary register 412 for the complete data set, and switching channel 411, as well as input 413 of the electronic clock module and input 414, and outputs 415 (ON switching time), 416 (OFF switching time) and 417 (switching channel) of the working memory 418 through a chain 419 of AND gates and the AND gate 429 in the latter together with the completeness signal on line 421 (378 in FIG. 11b) logically combined. The data transports in connection with the working memory 418 are controlled by the central unit 422 including decoders in connection with a program memory 423 and possibly with an external additional read / write memory 424.

11d shows the assemblies of the electronic watch assembly 441 with the time segment stages 442 (day of the week “d”), 443 (hours “h”), 444 (minutes “m”) and 445 (seconds «s») with the clock generator 446, consisting of an oscillator 447 and various divider stages, including for 1 ms-1/2 s, 1/8 s and 1 s clock signal outputs, e.g. B. T ₁ and T ₂ , and (1 s) for the ongoing progression of the electronic clock assembly 441, reproduced. The time segment stages 442 to 445 can also be set from the data record memory (392 in FIG. 11b) via the line 448 and the AND gate 449 when the function signal “UHR” 336 is present on the line 450.

From the clock generators 446, two different clock signals are released alternately via the AND gates 466, 467 by controlling the second inputs from a time-delayed monostable FLOP gate controlled via the line 468 to the outputs T ₁ and T ₂ after a period of time. With this arrangement, the time-delayed switching of the clock signal input takes place with the control buttons from individual pulses to a sequence of faster clock pulses.

The basic block diagram of FIG. 12 as a section shows an example with logical serial logic stages for the comparison of data record sections using shift registers when processing the time comparison of the time and the programmed ON or OFF switching time. The associated data and half data sets are in registers 471 and 472 for the days of the week, 473 and 474 for «h», «m» and «s» for the current time and the stored switching time, and registers 475 and 476 for the switching channels of an intermediate memory 478 loaded from the main memory 477 via the lines 479, 480 and 481. Shift registers 482 to 485 and 486, 487 are assigned to registers 472, 473 of the switching times on the input side and output side and the registers for the switching channels only on the output side. When a clock pulse is applied, the shift registers each switch the input and / or the output of the relevant time segment register to the next one.

The clock pulses are released by multiple linking by means of AND gates between clock signal line 488 via a first AND gate 489 with the AND gates controlled by CARRY and STATUS output signals of comparator stage 490 with a 491 negated on one side and a 492 negated on both sides. If the comparator element 490 determines equality at the next clock pulse and the CARRY and STATUS outputs are high, the AND element 493 is released and a clock pulse is transmitted to the further shift registers 484, 485 and via the counter 494 and the AND element 495 487 is given, so that the comparison for the next section is released. If the comparator stage 490 outputs the STATUS and CARRY signal = 1 (H) in this case as well, then the memory sections for the identically identified switching channels from the registers 475, 476 are switched through to the output 496 via the enabled AND gate further control processes are triggered. In this example, the individual data record sections are not queried in parallel, but in series.

The excerpt from a principle block diagram of FIG. 13 works according to the same principle as in FIG. 12 for an example of the evaluation of the setting key codes. Stored in register 501 z. B. the constants corresponding to the key codes, namely for the subordinate area, namely «QUI» (3), «CLE» (4), «S1-4» (5), «TAG» (6), «SEK» ( 7), «ABF» (6), «STU» (9) and «MIN» (A), in register 502 for an «ABF» subroutine for the «QUI» key, which in turn corresponds to the constants corresponding to the key codes for «TAG» (6) and «S1 .. 4» (5), in a register 503 for the «ABF» subroutine for the CLE key the constants «TAG» (6), «TAGIO» corresponding to the key codes ( 1), «STU» (9), «MIN» (10 = A - hexadecimal code!), «SEK» (7) and «S1 .. 4» (5). Using shift registers 504 to 508, these constants are sequentially read out from the key switch (or switch contacts) matrix (563 in FIG. 14) and in intermediate storage locations “STELF” 509, “TASMRK ₁ ” (510 or “TASMRK ₂ »511 stored key codes compared and, depending on the result of the logic comparator 512, the CARRY and STATUS signals unchanged by AND gates 513, 514 and 515, with one and with two negated inputs, linked to the clock signal and accordingly the registers of Step by step, until equality is determined and then the procedure is switched to a subordinate register, eg 502, 503 etc. The output signals then control via further AND gates 516 and another shift register closes the signal circuits for the subsequent circuit groups.

14 shows the exemplary embodiment with a microprocessor in which the modules arithmetic-logic unit (ALE) 551, buffer group 552, input and output register R 553, output register D 554, working memory 555 including programming memory, Buffer for complete data records, program memory 556 including program counter, return address memory and table memory, operation part decoder 557 and display device including auxiliary modules and clock 558 are integrated. Read lines 559 and address lines 560, 561 of the function selection switches, keys and setting keys combined to form a matrix 563 are connected to the input and output register in such a way that the switch and key codes are constants from the codes of the lines - Divisible areas result, eg the higher-level function keys «CLOCK», «ON», «OFF», «AS1 ..», in the constant range greater than 10 (A), the lower-order control keys «h», «m», «s »,« D1-7 »,« S1 ..4 »,« QUI »,« ABF »and« AS1 .. »in the range less than or equal to 10 (A) and greater than« 2 »and the« AUT »- Buttons are in the area less than or equal to 2. That way a clear query with quite a few steps is possible in all three cases. The output signal of the logic combination or comparator stage 551 controls the relays 562 via intermediate modules 561 and further logic elements.

When the program is being processed, the operating parts of the command words of the program memory are processed in accordance with the steps of the command counter, as it corresponds exactly to the serial logical combination of the exemplary embodiments of FIGS. 12 and 13 that operates purely in hardware.

15, the simple and clear handling of a time or time program switching device according to the exemplary embodiment of FIG. 4b can be explained. After pressing the «Check» button (194) for the first time, an empty display (601) with the number line «1 ... 7» for the days of the week and the symbols «-S», «L ₁ » and «L» for previously set or not set channels, when the button mentioned is pressed again the first switching time image - starting at Monday, but still without its display - 00:00 (602) visible. After a further query of switching times, the "FULL" picture (603) comes at some point, namely when the memory capacity reserved for SL ₁ has been used up. Then press the «Check» button again to select the «SL ₂ » channel. If the operation is repeated again until "FULL" appears, the system automatically switches back to channel "SL ₁ " and the empty display (601) is shown again. After pressing the "I / O" button (198), the ON circuit diagram (604) for the first setting is displayed, here 00:00 for "I".

After the "1/0" button has been pressed for the first time and the "Check" button has continued, if the "h", "m", "d1-7" and "S1-2" buttons have already been pressed, the switching times 605, if necessary consecutively. If this operation has not yet taken place, the ON ("I") and OFF ("O") switching times can be selected according to the preselection using the "1/0" button using the "h", "m", "d1-" buttons. 7 "and" S1-2 "can be entered (606 or 607). In the following, the entered switching time data, ie the respectively displayed and the last pressed button, can be deleted by pressing the" Clear "button (608) and / or use the "CLOCK" button to display (609) or set the current time or, instead, press the "Check" button to call up the relevant switching time image (610) without transferring it to the working memory; if "FULL" is displayed (611), the current time (612) appears on the display.

Fig. 16 shows that the display, change and deletion of the data of the displayed, set days of the week and switching channels takes place in the same simple manner. The days of the week for the ON switching time are in the upper line and for the OFF switching time in the lower one - Consistent with image 605 on the display - reproduced as a series of bars that may light up next to each other, "flashing" hatching and "constant", ie are drawn in solid black. In Fig. 16a at 1) the sequence of the bar images according to the actuation of the button «d1-7», if necessary or partially several times, «Q» acknowledgment and at 2) the switching time data record corresponding to the setting of the days of the week. Excerpt reproduced. 16b shows how the setting according to 1) is extended by pressing the "d1-7" button, again in some cases several times without acknowledgment, and the "Q" button to add Tuesday and Wednesday to the additional days of the week Thursday and Saturday , 3).

In Fig. 16c, top 1), the absence of a setting of ON switching days is indicated, which is eliminated by pressing the «d1-7» key twice according to 2) and pressing the «Q» key. In Fig. 16d, line 1), the blinking of all bars shows that no day of the week has been set at all, which is why according to 2) by pressing the «I / O» setting to ON, i.e. «I» - and pressing the «d1-7» and «Q» buttons and then 3) resetting the «1/0» button - setting to OFF, i.e. «O» - and also pressing buttons «d1-7» and «Q» the data record section for the days of the week must be corrected. 16e - here more ON switching days than OFF switching days in line 1) - can be corrected just as easily by preselecting the OFF switching times “O” using the “I / O” button and pressing the “d1” button -7 »and« Q »for setting the weekdays Monday, Tuesday, Wednesday and Friday and acknowledging them for storage.

Fig. 16f ₁ , line 1) indicates an incomplete entry of the switching channels (only «SL ₁ »), which are supplemented by pressing the «S1-2» and «Q» buttons to that in line 2), as is the consequence of Button images can be recognized. In the event of an incorrect setting according to line 1 of Fig. 16f ₂ to the second switching channel, pressing the «S1-2» key switches to the first switching channel, the symbol flashing, after which pressing the «Q» key saves this correction can.

• d_l (Anzahl) = d_o (Anzahl), SK gleich SK_o die Bedingung erfüllt sein:
• T_p/l kleiner als Tp_/o T_p/0 Ausschaltzeit alles im Datensatzspeicher 621.

17 shows a block diagram for an example of the test for compatibility (plausibility) of the individual data of the complete switching times data set found by the completeness check in the permanently formatted data record memory 621 with the partial areas for the symbol “I” 622, the days of the week “ d »623, the switching time of day in hours« h », minutes« m »and seconds« s »624, of the ON switching time partial data record, as well as the symbol« 0 »625, the days of the week« d »626, the switching -Daytime 627 of the OFF switching time partial data set, with the switching channel or switching channels «SK» 628 associated entered data for possible inconsistency (s). These include, for example, the setting ON switching time equal to OFF switching time same days of the week and same switching channels. So it has to be on condition

• d _l (number) = d _o (number), SK equals SK _o the condition must be met:
• T _{p / l} less than Tp _{/ o} T _{p / 0} switch-off time everything in data record memory 621.

There are further possibilities of contradictions between the data records in the data record memory 621 and one or more switching time data records in the working memory (418) with the associated address counter 629, from which a complete, complete switching time data record (630) is put together for the purpose of checking for compatibility with at least the following half data record 631 for the same day (s) and the same switching channels in the buffer memories 630, 631. These switching time data records necessarily have the same structure or the same composition from partial areas, as described in connection with the programming memory.

The following sub-areas (index "I" means belonging to the switch-on times, index "O" to the switch-off times, index P to the programming memory and index A to the working memory, "T" means switching time of day) must be compared and related to each other put:

• T_p/l g_rö_sser als T_A/O; Tp_/o grösser als T_A/l/AZ+1 unabhängig davon muss aber auch
• T_p/l kleiner als T_A/l des gerade aus dem Arbeitsspeicher ausgelesenen Datensatzes sein. Bei der Prüfung auf diese Bedingungen, die als besondere Beispiele ausgewählt wurden und wobei noch weitere zu berücksichtigen sind, ist zwischen folgenden Fällen zu unterscheiden:

The following cases must then be excluded from forwarding the set data contained in the data programming memory to the job memory:

• T _{p / l} g _r ö _sser than T _{A / O;} Tp _{/ o} greater than T _{A / l / AZ + 1} regardless of this must also
• T _{p / l be} less than T _{A / l} of the data record just read from the main memory. When examining these conditions, which have been selected as special examples and which still have to be considered, a distinction must be made between the following cases:

These conditions are, for the most part, reproduced as a logic diagram in the block diagram of FIG. 17, which, as an exemplary embodiment, also only shows a selection of the possible solutions for the implementation, in that the number of days of the week as a word is first of all in two comparison stages 632, 633 634 to three bits for the switch-on partial data record section d _l with that word 635 for d _o on the one hand and that by the shift registers 636 and 637, respectively selected most significant digit of the switching times of the day - subsections 624, 627 - values stored in intermediate registers 638, 639 are compared on the other hand and consequently only an H signal at the outputs of the NAND elements 640, 641, ie at the output of the AND element 642 only then is an enable signal (H) passed on to the first input of the AND gate 643. Then the above-mentioned requirements for the first part are only fulfilled.

In a corresponding manner, the requirements regarding the switching channels Kp and K _{A are} determined by the comparator stage 644, for the number of days of the week d _{A / 1} or d _{A / l / AZ + 1} (in the intermediate memories 645 and 646) and the number of days of the week dp _{/ o} or d _Alo (buffer memory 635, 647), as well as d _{p / l} or d _{A / l} in the comparator stages 648, 649, the data of the symbols O _{/ p} and O _{/ A} in the subareas 625, 650 and finally the data of the symbols I _l p and I _A or I _{/ A / AZ + 1} (the latter in the partial areas 651, 652) in the comparison stages 653, 654 checked or compared; the result signals of these comparator stages must be H without exception, so that the AND gate 655 also provides an H signal at its output, which is present at the second input of the AND gate 643 and at the first input of the AND gate 643a, the output signal of which addresses counter 629 increased by one. This completes the second part of the prerequisites.

The actual plausibility check consists in the further linking steps: First, at the inputs of the comparator stage 656 via shift registers 636 and 657, the data selected and stored in the intermediate registers 638 and 658, respectively, of the most significant digits of the ON-switching times Tp _{ll of} the programming memory 621 and 627, respectively T _{A / l of} the working memory 418, ie of the register 630 -also of the addressed switching time data record; At the inputs of the comparator stage 659, the selected data of the most significant digits of the OFF switching times of the day Tp _{/ o of} the data record memory 621 or T _{A / O of} the register 630 of the selected and stored in the intermediate registers 639 or 661 are located via shift registers 637 or 660 Working memory 418 - with the same addressing as with the ON switching time of day; Finally, at the inputs of the comparator stage 662, together with the output signals of the intermediate registers 638 and 663 - the latter via the shift register 664 - are the data of the most significant digits of the OFF switching times Tp _{/ o of} the data record memory 621 or T _{A / l / AZ +1 of} the next higher address of the working memory 418 for the same days of the week and switching channels.

The outputs of the comparator stages 656, 659 and 662 are connected by the OR gate 665, the AND gate 666 and partly by the AND gate 643a, the output signal of which increases the address counter 629 by one, and finally the AND gate 667 is linked in such a way that that on output line 668 - if conditions are met - an enable signal for the transfer of the complete switching time data record in data record memory 621 to the addressed subarea between AZ and AZ + 1 of working memory 418 occurs via line 669 and AND elements 670, 671; the AND gate 671 also becomes conductive only when the inputs of the completeness check are present at its inputs 672, 673 (outputs of the AND gates 375, 376 in FIG. 11b). The outputs 415 to 417 and the inputs, including for W / R and C / S switching of the working memory 418, correspond to those of FIG. 11; An enable signal for the deletion of the data record or of its partial areas in the data record memory or, depending on the actuation of the pushbuttons, of the main memory is output via line 674.

Additions to this exemplary embodiment of the compatibility check are readily possible for any person skilled in the art on the basis of the above description in conjunction with FIG. 17; the use of further tests is only a question of the maximum allowable effort. However, this is usually not so important if the data links are carried out by means of serial processing according to a program, to which the example of parallel processing can easily be transferred, as has already been explained in connection with the completeness check.

Claims (43)

1. An electronic time-programme commutating device comprising:

an electronic clock component having a clock unit and a number of divider stages for period data signals, such as weekday "d", hour "h", minute "m", if necessary second "s", and timing signals for longer periods;

a central unit having read-write primary stores with addressable registers as intermediate store cell groups and constant value stores, arithmetic/ logic computer units for processing the data output signals of such components, and program stores with associated program counter and decoding devices for the generation and distribution of function signals for the control of electronic components of the central unit;

a luminous digital indicator subdivided into subzones (30, 32) and having display areas (4) for groups of signs, such as digits, letters, flags and/ or symbols,

an input unit having control elements, such as keys and switches, combined in subzones and associated in groups with the display areas (4),

an output unit for the energization or de-energization of switching devices, such as electromagnetic relays, electronic switching devices, for load circuits, if necessary with a number of channels and/or switching amplifiers,

control and power supply components and a casing in whose front wall operating and setting areas, and at least one luminous digital device are disposed,

characterised in that

(a) the switches and keys for

(a1) for a first function selection take the form of on/off switches or changeover switches (341) for basic circuits such as "AUTOMATIC/ SETTING" (9) and/or ON and OFF switching of the switching channels (10 to 13),

(a2) for a second function selection take the form of function selection keys (321 to 325) for switching data, such as setting the actual clock time (CLOCK) (15) and on (ON) (16) and off [(OFF) (17)] switching times, and selecting switching channel (AS1, ...) (27) and/or automatic (AUT) (26),

(a3) for the control of the switching time data hour "h" (20), minute "m" (21) and if necessary second "s", the selection between ON and OFF switching time input, the selection of the weekdays (d) (23) and the switching channels (24) and their intermediate storage, take the form of setting keys for the inputting of divider stage pulses and selection and acknowledgement keys (25),

so that the switches and keys are ordered in groups as regards priority,

namely the function selection switches (9 to 13), function selection keys (15 to 17; 26 to 29) and setting keys (20 to 25) are combined in a matrix with addressing lines in one coordinate and read-out lines in the other coordinate, as control elements at their points of intersection;

when the address associated with the particular switch or key is connected to the associated output of the read-out lines

a CODE appears, which is clearly defined in characteristically limited numerical ranges for the groups of control elements, and accordingly

(b) the subzones (30, 32) of the luminous digital device are provided with display areas for

clocktime data of ON (30), OFF switching times (32) and output switching channels (37),

flags "I" (31) and "O" (33) for association with the on and off switching times,

double point(s) (34) between hours "h" and minute "m" display elements for the

continuous display of the seconds beat by blinking,

and seven beams (35, 36) and arrows (38) disposed one beside the other for the weekdays, and

(c) the display areas (4) for the clocktime data of ON and OFF switching times and component data records associated with output switching channels (37) can be transferred from a data record store, of fixed format and acting as an intermediate store cell group, into the central unit only as a whole by means of one of the function selection switches or keys, with mutual exclusion or mutual release of a single switch or key in any sequence, suitably organised in groups, connected to control inputs or outputs of the central unit, and can be processed at that place, and
logic parallel and/or serial combination circuits (326 to 335) for the selective inputting or correction of components of the data record signal group are provided, in which the cell groups for component data records,

(c1) are ordered in priority

(c2) and/or can be inputted partially erasable or acknowledged

(c3) and in which the data records can be checked for completeness and/or compatibility (plausibility),

can be connected to the corresponding inputs and outputs of a matching independent data record store of fixed format (392, 412) and/or inside a read-write primary store (418) via logic parallel and/or serial combination or comparator stages.

2. A time program switching device according to claim 1,
characterised in that the code is defined for keys within the hexadecimal range 0 to F, namely in its bottom part, e.g., "2" for the "AUT" key, in its top zone, e.g., greater than "10" for the function keys (hexadecimally greater than "A"), and in its central zone therebetween from "3" to "10" and "A", both included, for setting keys except "AUT".

3. A time program switching device according to one of claims 1 and 2,
characterised in that cell groups of the data record store (392, 412) of fixed format are at least partly provided with an adapted limit value overflow for seven weekdays, ten places of tens and six places of ones in the case of the clock times, and/or with two inputs for opposite polarity ("+/-") of the pulses to be inputted.

4. A time program switching device according to one of claims 1 to 3,
characterised in that the addressable registers are addressable separately as cell groups of the formatized data record store and the read-write primary store, being associated with

(a) a section of the formatized intermediate store (at 392) for a half date record with clocktime data and data of the ON or OFF switching times and if necessary of the switching channels,

(b) registers of an external additional read-write store, spatially separated therefrom, as a buffer store,

(c) at least one auxiliary buffer store (412) for a complete data record with ON and OFF switching time data, including data for weekdays, and if necessary for switching channels,

(d) a separately addressable buffer store in the primary store (418), whose write-in inputs (407, 409,411,414,408,410,421) can be connected to outputs (321 to 325, 351 to 358) of the input unit and/or of the other registers (393, 394).

5. A time program switching device according to one of claims 1 to 4,
characterised in that the cell groups of the data record store (392, 412) of fixed format and of the read-write primary store (418) are associated with separately addressable registers in the primary store (418)

for data of the clock time (441 to 445), and for data of the ON and OFF switching times, for data of the weekdays, for data of the switching channels, for data of the ACTUAL states of the switch devices,

together with setting flags and/or markers for switch and/or key codes, constants, addresses, and time counter data can be connected to its write-it inputs (414), and its read-out outputs (415 to 417) can be connected to inputs of the auxiliary buffer store (412) acting as the input store of the luminous digital device or of an associated separate intermediate store.

6. A time program switching according to one of claims 1 to 5,
characterised in that to check the full data record for completeness, the outputs (393, 394) of all cell groups of the data record store (392,412) of fixed format are applied to the inputs of a logic combination component, whose output signals are each applied to an input of an AND element in a chain of AND elements, whose other input is connected to the output of the data record store (392) and whose outputs are connected when the combination condition is fulfilled to matching inputs (414) of a further auxiliary register in the primary store (418), while if such condition is not fulfilled, each display element belonging to the unoccupied cell groups of the fixed-format data record store delivers a blinking signal.

7. A time program switching device according to claim 6,
characterised in that the logic combination component comprises at least one AND element (377) to whose inputs the setting outputs of FLIP-FLOP elements (379, 380) are applied which are associated in groups with the setting keys for switching time data (claim 1, a3).

8. A time program switching device according to claim 6,
characterised in that the logic combination component comprises at least one NAND element (with OR element 375, 376) to whose inputs the outputs of the FLIP-FLOP elements (368 to 372) associated with the switching time data and of the FLIP-FLOP elements (232, 233) of the function key circuits of ON and OFF switching times are applied (claim 1, a2).

9. A time program switching device according to one of claims 1 to 8,
characterised in that for the purpose of checking the inputted data for compatibility and plausibility, the outputs (393, 394) of all cells of the data record store (392) associated with places in the complete data record are applied together with outputs upon the function selection circuits (claims 1, a1) are applied to the inputs of a logic combination component for connections of counters (634, 635, 645, 646, 647), shift registers (636, 637, 657, 660, 664) and/or comparator stages (632, 633, 644, 648, 649, 653, 654, 656, 657, 662), their output signal being applied to an input of an AND element (670, 671) whose other inputs are connected to the outputs of the program store (392), and its other input is connected to the output of the AND element (670, 671) belonging to the combination component for the completeness check, such connection(s) being made only if the compatibility condition is met, or if it is not met, the display elements belonging to the incompatibly occupied store cells deliver a blinking signal.

10. A time program switching device according to claim 9,
characterised in that the logic combination component comprises at least one AND element (642, 643, 643a, 666, 667), to whose inputs are applied the outputs of intermediate registers for switching time/clock time data, the output signals of intermediate registers for switching time/weekday data and the output signals of FLIP-FLOP elements which are acted upon by the output signals of the cells for switching-on time, switching-off time, weekday and switching channel, and also switching-time times of the day.

11. A time program switching device according to claim 9,
characterised in that the logic combination component comprises at least one pair of NAND elements (640, 641), whose inputs are acted upon by signals in the mutually complementary outputs of comparator stages (632, 633), each of which is controlled by the signals of the ON and OFF switching positions of the data record store (392, 412) on the one hand and by the storage content signals of the intermediate stores (634, 635) on the other.

12. A time program switching device according to claim 9,
characterised in that the logic combination component comprises at least one OR element (665) or EXOR element.

13. A time program switching device according to claim 9,

characterised in that for the purpose of checking compatibility prior to the recharging of a complete data record in the data record store (392, 412) of fixed format and its auxiliary register into the read-write primary store (418), instead of another data record stored therein, the outputs of the ON switching component data record (weekday, time of the day) of the data record store and the read-out outputs of an ON switching component data record (weekday, time of the day - from 651 onwards) of the read-write primary store (418) can be connected to a comparator stage with AND elements (655, 643a; 656, 657, 662), the read-write primary store (418) by means of continuously raising the address counter (629) to one of the stored data records of the same switching channel data, whose ON switching component data record (from 652 onwards) is just larger than the OFF switching component data record of the data record store (392),

and moreover in the case of equality or a negative difference between the ON switching data record (658) of the read-write primary store and that (638) of the data record store (621) the result signal of the comparator stage blocks the latter from being transferred to the read-write primary store via an unoperated AND element (666) and an operated AND element (643a), while in the case of a positive difference between the ON switching data record (638) of the data record store (621) and that (658) of the read-write primary store (418), with the erasion of the complete ON/OFF switching data record (630) stored in the read-write primary store, the result signal of the comparator stage releases such complete ON/OFF switching data record (638) in the data record store (621) to be transferred to the read-write primary store (418) via an OR element (665).

14. A time program switching device according to claim 13,
characterised in that the contents of the cells of at least one group of cells of the register belonging to the displayed data record for at least one preselectable channel and/or weekday can be interchanged or erased by the actuation of associated key(s), independently of the other groups of cells.

15. A time program switching device according to one of claims 1 to 14,
characterised in that the contents of at least one cell of a group of cells of the register belonging to a data record can be changed optionally in the higher or lower direction by at least one stage of value, using an additional switch ("-" "or" "+/-"), by the individual actuation of a setting key, in accordance with such actuation lasting until a given waiting time has elapsed.

16. A time program switching device according to one of claims 1 to 15,

characterised in that each of the signal circuits for the setting keys (351 to 358) comprises a logic AND or OR parallel and/or serial combination stage (360 to 367; 326 to 335) in the inoperative condition for cancelling the electric effect of each previously actuated function selector key (321 to 325) - i.e. for CLOCK, ON, OFF, AS1 ..., AUT, and conversely for cancelling the blocking.

17. A time program switching device according to one of claims 1 to 16,
characterised in that each of the signal circuits for the adjusting keys (351 to 358), e.g. "d", "h", "m", "s", "S1 ...", ABF or CHECK, QUI, CLE, comprises a logic combination stage (360 to 367) for blocking the electric effect of the former by the function selection key AUT (325).

18. A time program switching device according to one of claims 1 to 17,
characterised in that the input store for TAG (weekday) and/or KAN (switching channel) takes the form of a shift-buffer store (387, 391) and between the latter and the corresponding register (387', 391') of the data record store (392, 412) is in each case a logic individual combination component (e.g. AND element 366) for acknowledgement on the storage of a number of successive TAG or KAN data and associated markers.

19. A time program switching device according to one of claims 1 to 18,
characterised in that disposed between the input circuits of the function selection keys (321 to 325) and the setting keys (360 to 367) is a logic combination stage (326 to 335) for blocking their electric effect by the function main selector switch "STEL/AUT" (341) in one of its positions.

20. A time program switching device according to one of claims 1 to 19,
characterised in that associated with the switching channels are channel selection switches by means of which the channels can be adjusted independently of the function and setting keys and superordinately thereto.

21. A time program switching device according to one of claims 1 to 20,
characterised in that the signal circuit of the adjusting keys for "h", "m" and if necessary "s" comprises a logic stage (375, 376, 379, 380) for the release of the signal circuit of the ABF (or CHECK) key when the AND condition is met with the signals of the function selection key AS1 ..., then of the ON (322) or OFF (323) and if necessary of the TAG (weekday) setting key (351).

22. A time program switching device according to one of claims 1 to 21,
characterised in that the signal circuit of the function selection (321 to 325) and setting keys (351 to 358) comprises a logic combination component with the signal circuit of the CLE (358) key for cancelling the electric effect of the key actuated immediately before or for erasing the associated section of the data displayed.

23. A time program switching device according to one of claims 1 to 22,
characterised in that the signal circuit of the function selection switches comprises a shift register device for their switchover from the control circuit of a particular associated function selection switch to the next one, e.g., in the sequence "CLOCK-ON-OFF-AS1 ... AUT-CLOCK ... etc." with successive actuation of the function selection keys.

24. A time program switching device according to one of claims 1 to 23,
characterised in that the signal circuit of the adjusting keys, e.g. "h", "m", and if necessary "s" comprises a shift register device for switching over the former, in the case of the setting keys "d" and "S1 ..." with the interposition of a logic combination component for previous actuation of the "QUI" key after the AND condition has been met when the particular adjusting key has been actuated once or more.

25. A time program switching device according to one of claims 1 to 24,
characterised in that the signal circuit of the function selection keys comprises a time function element for its resetting when a predeterminable period of time has elapsed, e.g., 40 seconds, without the actuation of an adjusting key.

26. A time program switching device according to one of claims 1 to 25,
characterised in that an AND logic member and a FLIP-FLOP element (360 to 373) are disposed between each of the function selection keys connected to a timing pulse source and the inputs of the logic stages for the data inputs of the components for actual time by the clock, for ON and OFF switching times, and also the switching channel of the program register, of the input store of the luminous digital display device, of the auxiliary register for a complete data record (e.g. 621, 630, 631), and also of the intermediate store for data of the actual time by the clock (442 to 445) and of the ON and OFF switching times, the weekdays and the switching channels (207, 412), Q outputs of all the other latter being connected to the other inputs of the former, so that each time a function key is actuated, the FLIP-FLOP components of all the others are reset.

27. A time program switching device according to one of claims 16 to 26,
characterised in that the logic combination component for parallel or serial data processing is constructed in the form of an AND or OR element group.

28. A time program switching device according to one of claims 26 and 27,
characterised in that an AND logic element (451), to whose other input the Q output signal of the FLIP-FLOP element (335) associated with the "AUT" key is connected, and a monostable FLOP element (468') with duration of the Q output signal limited in time and automatic resetting after a given lapse of time are disposed between each of the setting keys connected to a pulse generator (446) derived from the CLOCK component (441) and the inputs of the period divider stages (443 to 445) and of the switching channel stage, the Q output of the FLOP member (468') in connection with the output signals of the FLIP-FLOP elements (332, 333) of the "ON" and "OFF" function signal keys each operating a FLIP-FLOP element whose Q output signals, connected in an AND element (429), generate a release signal for the transfer of the output signals of the sections of the input stores (412) of the luminous digital display device.

29. A time program switching device according to one of claims 1 to 28,
characterised in that the timing pulse source used is a pair of AND elements (466; 467) which are connected on the output side, the first input of one (466) of these being applied to the "1-s" divider stage and the first input of the other (467) being applied to the "1/8-s" divider stage of the CLOCK component (446), their other inputs being applied to the Q output of a monostable FLOP element (468') controlled with a time delay, whose input is acted upon via a time delay element by the Q output of the monostable elements of the setting key signal circuits via a common OR element (375, 376).

30. A time program switching device according to one of claims 1 to 29,
characterised in that the output signal of the electronic CLOCK component (441) and the output signals of the intermediate stores for sections of the data of the actual time by the clock, the ON and OFF switching times (454, 455), including the weekdays and the switching channels (456) are connected to the inputs of the logic unit (LE) (460 to 463), each of the other inputs of the AND elements being operated by the output signal of the FLIP-FLOP element (335) of the switching group belonging to the "AUT" key (325).

31. A time program switching device according to one of claims 1 to 30,
characterised in that switches (342) having at least two positions are disposed in the control circuit of each of the switching groups for the release or blocking respectively of their ACTUAL state in one of their operating stages.

32. A time program switching device according to one of claims 1 to 31,
characterised in that disposed in the control circuit of each of the function selection keys (321 to 324), with the exception of the "AUT" key, is a switch (341) having two positions "STEL" and "AUT" for blocking the input with the setting keys in case the "AUT" key is actuated.

33. A time program switching device according to one of claims 1 to 32,
characterised in that connected in the resetting circuit of the monostable FLOP elements of the signal circuit of the setting keys is the output signal of the OR element (381), and connected in the resetting circuit of the FLIP-FLOP elements (331 to 335) of the signal circuit of function selection keys (321 to 325) is the Q output signal of a monostable FLOP element (T1) which is operated with a time delay and whose input is acted upon by an OR element (381), which is operated on the input side by the U output signals of the FLIP-FLOP elements in the signal circuits of function selection keys.

34. A time program switching device according to one of claims 1 to 33,
characterised in that the electronic components are at least partially made up from components of a commercially available microprocessor with arithmetic/logic unit, read-write primary store, input and output registers for the addressing, data read-out and data transfer of the groups of switches and/or of function selection and setting keys combined in a matrix, and also comprise data and address intermediate stores (n), inter alia accumulator (A), B register etc. and constants stores, counters for intervals of time, shift registers for logic combination and comparative routines of storage contents and their decision assessment by means of groups of AND or OR elements or are structurally integrated therein.

35. A time program switching device according to one of claims 1 to 34,
characterised in that the AND or OR, FLIP-FLOP and MONO-FLOP components, counters for intervals of time and/or store data words, shift registers, constants storage places of the serial logic combination and comparator stages are replaced at least partially by command-word-containing places of a programming store with decoder for the derivation of function signals from the operation parts of the stored command words.

36. A time program switching device according to claims 34 and 35,
characterised in that the microprocessor component, combined structurally preferably by C'MOS technology with a LED liquid crystal display element as a luminous digital display device and as a structure in the form of a semiconductor contact module (67), is mounted and connected on a printed circuit (120, 215) with galvanically applied strip conductors by means of the terminal lugs.

37. A time program switching device according to claim 36,
characterised in that the printed circuit (215) is disposed between a casing top member (201) having a display area containing a window aperture (83) for the luminous digital display device and an adjacent control and cutting area (3) with the function selector (15 to 17 and 27) and setting keys (21 to 24), and also function selector switches, and a casing bottom part (203), the matching wall edges of the casing parts being screwed together self-adjustably by fitting parts to form a complete case and being retained offset on both sides by ribs (e.g. 206), partitions (e.g. 114) and pins (e.g. 118).

38. A time program switching device according to claims 36 and 37,
characterised in that the luminous digital display device is constructed for a pair of switching times, the switching time image being subdivided into a top half (30) for an ON switching time with a first symbol "I" (31) and a bottom half (32) downwardly laterally inverted in relation thereto and having a second symbol, "O" (33), and each half comprises, in addition to the clock times "h", "m" and "s", with a double point between the data for "h", "m", below and above the latter, beam symbols (35, 36) at places one beside the other corresponding to the days of the week, and in another adjacent right-hand portion (37) of the display area (4) arrows (e.g. 38) one above the other for displaying the switching channels selected.

39. A time program switching device according to one of claims 36 to 38,
characterised in that the printed circuit (215) is reinforced by further printed circuits (216, 217) disposed on the printed circuit (215) at right angles on both longitudinal sides, such circuit boards (216, 217) carrying the power supply elements, amplifiers, a galvanic battery and/or capacitors (159-163) etc., the relays or the like and plug-in strips, the latter in the form of galvanically applied contact strips.

40. A time program switching device according to one of claims 36 to 39,
characterised in that the casing bottom part (213) has on two opposite walls grooves (228) preferably toothed on the inside for the clamping retention of such bottom part by dogs on the matching member, so that it can be inserted into the cutaway portion of a front side assembly plate of an electronic apparatus frame and is also suitable for use in build-up assembly by being placed on a pot-shaped build-up assembly cover casing (202), closed except for openings for connecting wires, to protect the rear parts and connections of the casing bottom from being touched accidentally.

41. A time program switching device according to one of claims 38 to 40,
characterised in that the function selection and setting keys are constructed in the form of fingers (55 to 59') produced by additives of a rubber-like material made conductive and have a neck (59) of rectangular cross-section and extend on the lower side of the front plate (109) through matching rectangular openings (105) having unitarily mode-on ribs (110 to 112) fitting the edges, the keys also being constructed with a head plate (60) bearing against the circuit board (51) as a current connector between the conductor strips contacted on key actuation and being joined unitarily and by self- substance to a joint resilient bearing surface (61) via mould-on fitting parts.

42. A time program switching device according to one of claims 36 to 41,
characterised in that the display area and the adjoining control and setting area of at least substantially identical adjoining side length are combined to form an elongate rectangle of side ratio two to one in the front plate of the casing top part and can be covered to be protected from dust and damage by a seethrough cover hood which can be fitted on to the casing top part between its side walls.

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