EA017061B1 - Data processing apparatus and method - Google Patents

Abstract

A data processing apparatus maps symbols received from a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols into an output symbol stream. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register ofand the permutation code forms, with an additional bit, a twelve bit address. The permutation code is changed from one OFDM symbol to another, thereby providing an improvement in interleaving the data symbols for a 4K operating mode of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestria12 (DVB-T2). This is because there is a reduced likelihood that successive data bits which are close in order in an input data stream are mapped onto the same sub-carrier of an OFDM symbol.

Description

FIELD OF THE INVENTION

The present invention relates to a data processing apparatus that, during operation, maps input symbols to signals of a subcarrier of an orthogonally frequency division multiplexed (ΟΓΌΜ, OFDM) symbol.

The present invention also relates to a data processing apparatus that, during operation, maps symbols received from a predetermined number of OFDM symbol subcarrier signals to an output symbol stream.

Embodiments of the present invention provide an OFDM transmitter / receiver.

State of the art

The Digital Terrestrial Television Broadcasting Standard (ΌνΒ-Ц, DTTB) uses orthogonal frequency division multiplexing (OFDM) to transmit data representing video images and sounds to receivers via broadcast radio signals. As you know, there are two models for the standard DTV, which are known as 2k and 8k. 2k mode provides 2048 subcarriers, while 8k provides 8192 subcarriers. Similarly, for the standard of Digital Television Broadcasting for mobile phones (ΌνΒ-Ц, DTV), a 4K mode was provided in which the number of subcarriers is 4096.

Error correction coding schemes, such as BESD / BCH coding (PCNP / BCH, low density parity check code / Bose-Chowdhury-Hockingham code) that have been proposed for DTTV2, work better when noise and degradation of symbol values as a result data transmissions are not correlated. Terrestrial broadcast channels can introduce correlated attenuation, both in the time domain and in the frequency domain. In this case, as a result of the spacing of the coded symbols into different signals of the subcarriers of the OFDM symbols at the greatest possible distance, the performance of error correction coding schemes can be improved. Accordingly, to improve the integrity of data transmitted using the DTTB or DTV, a symbol interleaver is provided to interleave the input data symbols, and these symbols are mapped to subcarrier signals of the OFDM symbol. Such a symbol interleaver comprises an interleaver memory and an address generator. The interleaver is arranged to read data symbols into the interleaver memory for displaying on the OFDM subcarrier signals and to read data symbols for the OFDM subcarriers from the storage device, the reading from the storage device being performed in a different order than the reading from the storage device, this order being determined by the set addresses generated by the address generator. For 2k mode and 8k mode, the configurations of address generation in the DTV standard for display were disclosed. Similarly, for the 4k mode, the DTV standard provided an arrangement for generating addresses for display, and an address generator for implementing this display is disclosed in European Patent Application 04251667.4. The address generator contains a linear shift register with feedback, which during operation generates a pseudo-random sequence of bits and a permutation scheme. The permutation circuit permutes the order of the contents of the linear shift register with feedback to generate the address. The address provides a location designator in the interleaver memory for writing an input data symbol to or reading an input data symbol from an interleaver memory for displaying an OFDM symbol on one of the signal subcarriers. Similarly, the address generator in the receiver is configured to generate addresses of an interleaver memory to write received data symbols to or read data symbols from an interleaver memory to generate an output data stream.

In accordance with the further development of the Digital Terrestrial Television Broadcasting standard, known as DTTV2, a need has arisen to improve data transmission and, more specifically, to provide an improved arrangement for interleaving data symbols with OFDM symbol subcarrier signals.

SUMMARY OF THE INVENTION

In accordance with an aspect of the present invention, there is provided a data processing apparatus adapted to display input symbols for transmission on a predetermined number of frequency division multiplexed (OFDM) subcarrier signals. The data processing device comprises an interleaver, during operation, reading a predetermined number of data symbols into the storage device for displaying on the OFDM subcarrier signals, and reading data symbols for the OFDM subcarriers from the storage device to perform the display, the reading from the storage device being performed in a different order than reading into the storage device, the order is determined by the set of addresses, as a result of which the data symbols are interleaved into subcarrier signals. The data processing device includes an address generator, which during operation generates a set of addresses, the address being generated for each of the input data symbols for mapping the input data symbols to subcarrier signals. The address generator comprises a linear shift register with feedback including a predetermined number of register stages that during operation generate a pseudo-random sequence of bits in accordance with the generator polynomial, a switching circuit configured to receive the contents of the shift register stages and perform permutation the order of bits present in the register stages, in accordance with the permutation code, to form the address of one of the subcarriers of the OFDM, and the control module, executed enny chance together with address verification circuit, re-generate an address when a generated address exceeds a predetermined maximum valid address. The specified maximum real address is approximately four thousand, the linear shift feedback register has eleven register stages and the generator polynomial for the linear shift register with feedback ~ U1I ’and the permutation order forms thirteen bit addresses with an additional bit. The data processing device is characterized in that the permutation scheme is adapted to change the permutation code, on the basis of which the cascade order of the register cascades is rearranged to form a set of addresses from one OFDM symbol to another. Embodiments of the present invention make it possible to form a data processing apparatus that performs symbol interleaver operation for displaying data symbols intended for transmission to an OFDM symbol having essentially four thousand subcarrier signals, which can provide improved integrity of the transmitted data. The improvement is achieved by changing the permutation code, which is used to change the order of the bits in the shift register with feedback from one OFDM symbol to another. For example, the permutation code used may be one of a sequence of different permutation codes that are cyclically repeated for each of the multiple OFDM symbols. The result is an improvement in reducing the likelihood that consecutive data bits or bits that are located close to each other in order in the input data stream will be mapped to the same subcarrier of the OFDM symbol, whereby coding for error correction may work more efficiently.

In one embodiment, the number of subcarrier signals may be a value of substantially two thousand to four thousand and ninety-six. In addition, the OFDM symbol may include subcarriers of pilot sequences that are capable of carrying known symbols, and the predetermined maximum valid address may depend on the number of pilot subcarrier symbols present in the OFDM symbol. At the same time, in the 4k mode, an effective interleaver of symbols can be provided, for example, for the ΌνΒ standard (DTV, digital broadcasting), such as DTV2, DTV or DTV.

In one example, a sequence of different permutation codes generates the address Kd] of thirteen bits for the ίth data symbol from the bit present in the ηth cascade of K'fi] register in accordance with the permutation code defined in the table ________________________________

The position of the bit Κ'ι [η] (og n = Bit position [η] ίοτ n = 10 7 nine IG 8 7 6 5 4 3 ’ 2 one 3 0 6

Although the sequence of permutation codes may include any number of permutation codes, in one example, two permutation codes are used. In one example, these two permutation codes are

The position of the bit K ', [and] Gog n = 10 nine ! 8 7 b 5 4 3 2 one ⁰ Bit position K, [n] Gog n = 7 10 5 8 one 2 4 nine 0 3 ⁶

Bit position [and] Gog n = 10 nine 8 7 6 5 4 3 2 one 0 Bit position K; [n] Gog n = 6 2 7 10 8 0 3 4 one nine 5

For example, approximately four thousand subcarriers may be provided as one of a plurality of operating modes, approximately four thousand subcarriers provide half or less than half the maximum number of subcarriers of OFDM symbols in any of the operating modes. Input data symbols may be formed in or may be considered as first sets of input data symbols for mapping to first OFDM symbols and second sets of input data symbols for mapping to second OFDM symbols. The data processing device during operation can interleave the input data symbols from both the first and second sets in accordance with the process of odd interleaving. The odd interleaving process includes writing the first sets of input data symbols to the first part of the interleaver memory in accordance with the sequence of the first sets of input data symbols, reading the first sets of input data symbols from the first part of the interleaver memory to the subcarrier signals of the first OFDM symbols in accordance with the order defined by one of the sequence permutation codes, recording the second set of input data symbols in the second part of the memory troystva interleaver in accordance with the order of the second sets of input data symbols, and reading out the second sets of input data symbols from the second part of the interleaver memory in the second sub-carrier signals of the OFDM symbols in Correspondingly

- 2 017061 wii with the order defined by other sequence permutation codes.

The first OFDM symbols may be odd OFDM symbols, and the second OFDM symbols may be even OFDM symbols.

In some conventional transmitters and receivers of OFDM, which operate in accordance with the modes 2k or 8k for DTTV and in 4k mode for DTV, two character interleaving processes are used in the transmitter and receiver; one for even characters ΘΕΜΌ and another for odd characters ΘΕΜΌ. However, analysis showed that the interleaving schemes developed for 2k and 8k symbol interleavers for DTTV and 4k symbol interleaver for DTV work better for odd characters than for even characters. Embodiments of the present invention are configured such that only an odd character interleaving process is used, unless the transmitter / receiver operates in a mode with a maximum number of subcarriers. Therefore, when the number of data symbols that can be carried by subcarriers of the OFDM symbol in one of a plurality of operation modes is less than half the number of data symbols that can be carried by the operation mode that showed the largest number of subcarrier signals carrying data to the OFDM symbol then the interleaver of the OFDM symbol transmitter and receiver is configured to interleave the data symbols in both the first and second sets using the process of odd interleaving. Since the interleaver interleaves the data symbols in both the first and second sets of data symbols into OFDM symbols using the odd interleaving process, the interleaver uses different parts of the interleaver memory to write and read data symbols. Thus, compared with an example in which the interleaver uses an odd interleaving process and an even interleaving process to interleave the first and second sets of data symbols with successive first and second OFDM symbols that use available memory, the amount of storage capacity used is twice data characters that can be carried by the OFDM symbol when using only odd interleaving. This is compared with the requirements of providing a memory capacity that corresponds to a single number of data symbols that can be carried by the OFDM symbol, in a mode in which the largest number of data symbols per OFDM symbol is used in both odd and even interleaving processes. However, the number of subcarriers per OFDM symbol for this maximum operating mode requires twice the amount of memory compared to the next largest number of subcarriers per OFDM symbol for any other mode of operation with the next largest number of subcarriers per OFDM symbol.

In accordance with some examples, therefore, the minimum size of the interleaver memory may be provided in accordance with the maximum number of input data symbols that can be carried over subcarriers of OFDM symbols that are available for transferring input data symbols in any of the operating modes.

In some embodiments, the mode of operation that provides the maximum number of subcarriers per OFDM symbol is 32k mode. Other modes may include one or more of 1k, 2k, 4k, 8k, and 16k modes. Thus, as can be seen from the above description, in the 32k mode, the processes of even and odd interleaving are used to interleave the data symbols so that the size of the interleaver memory can be sufficient only to take into account 32k data symbols. However, then in 16k mode and in any other modes, for example, the processes of odd interleaving are used, therefore, in 16k mode, a memory capacity equivalent to 32k characters is required, in 4k mode a memory capacity equivalent to 8k characters is required, and in 2k mode a memory capacity equivalent to 4k characters.

Various aspects and features of the present invention are defined in the appended claims. Other aspects of the present invention include a method for displaying input symbols to be transmitted over a predetermined number of frequency-division multiplexed (OFDM) subcarrier signals, as well as at a transmitter.

Brief Description of the Drawings

Embodiments of the present invention will be described below by way of example only with reference to the accompanying drawings, in which like parts are indicated by corresponding reference numerals and in which:

in FIG. 1 shows a block diagram of a coded OFDM transmitter that can be used, for example, with the DTTV2 standard;

in FIG. 2 is a block diagram of a portion of the transmitter of FIG. 1, in which the symbol display unit and the frame builder illustrate the operation of the interleaver;

in FIG. 3 is a block diagram of the symbol interleaver of FIG. 2;

in FIG. 4 is a block diagram of an interleaver memory shown in FIG. 3, and a corresponding unit for eliminating symbol interleaving in the receiver;

in FIG. 5 is a block diagram of the address generator of FIG. 3, for 8k mode;

in FIG. 6 is a block diagram of an encoded OFDM receiver that can be used, for example, with the DTTV2 standard;

- 3 017061 in FIG. 7 is a block diagram of an interleaving elimination unit, which is shown in FIG. 6;

in FIG. 8 (a) is a diagram illustrating the results of an interleaver for even OFDM symbols, and FIG. 8 (b) is a diagram illustrating results for odd OFDM symbols; in FIG. 8 (a) and (b) are graphs of the distance at the interleaver output for subcarriers that were located next to each other at the interleaver input;

in FIG. 9 is a block diagram of the symbol interleaver shown in FIG. 3, illustrating an operation mode in which interleaving is performed in accordance with an odd interleaving mode only; and in FIG. 10 is a block diagram of the symbol interleaver of FIG. 1, illustrating an operation mode in which interleaving is performed in accordance with an odd interleaving mode only.

DETAILED DESCRIPTION OF THE INVENTION

The following description is provided to illustrate the operation of the symbol interleaver in accordance with this technique, although it should be understood that the symbol interleaver can be used with other modes for other DTV standards and in other OFDM systems.

In FIG. 1 provides an example block diagram of an OFDM encoded transmitter that can be used, for example, to transmit video and audio signals in accordance with the DTTV2 standard. In FIG. 1 source of the program generates data intended for transmission by the transmitter COROM (COMCR). Video encoder 2, audio encoder 4 and data encoder 6 generate video, audio and other data for transmission, which are supplied to the program multiplexer 10. The output of the program multiplexer 10 generates a multiplexed stream with other information required for transmitting video, audio and other data. The multiplexer 10 provides a stream through the connecting channel 12. There may be many of these multiplexed streams that are fed to various branches A, B, etc. For simplicity, only branch A. is described.

As shown in FIG. 1, the SOMR transmitter 20 receives a stream in a multiplexer adaptation and energy distribution unit 22. The multiplexer adaptation and energy distribution unit 22 introduces a random element into the data and transmits the corresponding data to the forward error correction encoder 24, which performs stream error correction coding. An interleaver of 26 bits is provided for interleaving coded data bits which, for example, DTTB2, represent the output of a BESP / BCH encoder (PCNP / BCH, low density parity check code / Bose-Chowdhury Hawkingham code). The output from the interleaver 26 bits is served in block 28 display the bits on the set, which displays the group of bits at the point of the set that you want to use to transmit bits of encoded data. The outputs of the block 28 display the bits on the aggregate are labels on the points of the constellation, which represent the real and imaginary components. Population point labels represent data symbols formed from two or more bits, depending on the modulation scheme used. They will be called data cells here. These data cells are transmitted through an interleaver 30 in time, the operation of which consists in interleaving data cells obtained from a plurality of code words of the PNP.

The data cells are received by the 32 frame builder, and these data cells are received on branch B, etc. in FIG. 1, through other channels 31. The frame builder 32 then generates a plurality of data cells in a sequence that must be transmitted in RICH symbols, where RICH symbols contain a plurality of data cells, and each data cell is mapped to one of the subcarriers. The number of subcarriers depends on the mode of operation of the system, which may include one of the 1k, 2k, 4k, 8k 16k or 32k mode, each of which requires a different number of subcarriers in accordance with, for example, the following table.

The number of subcarriers adopted in DTTV / M

Thus, in one example, the number of subcarriers for 4k mode is three thousand twenty four. For the DTTV2 system, the number of subcarriers per OFDM symbol may vary depending on the number of pilot and other reserved subcarriers. Thus, in DTTV2, unlike DTTV, the number of subcarriers for data transfer is not fixed. Broadcast stations can choose one of the following operating modes: 1k, 2k, 4k, 8k, 16k, 32k, each of which provides a certain range of subcarriers for data per OFDM symbol, while max

- 4 017061 mum, available for each of these modes, is 1024, 2048, 4096, 8192, 16384, 32768 respectively. In DTTB2, the physical layer frame consists of many OFDM symbols. Typically, a frame begins with one or more preambles or P2 OFDM symbols, followed by a number of OFDM symbols carrying a payload. The end of the physical layer frame is marked with characters that close the frame. For each mode of operation, the number of subcarriers may differ for each type of symbol. In addition, it can vary for each of them depending on whether the selected bandwidth extension; whether some tone reservation is allowed and according to which a pilot subcarrier structure has been selected. At the same time, the generalization of a specific number of subcarriers per OFDM symbol is difficult to implement. However, the frequency interleaver for each mode can interleave any symbol whose number of subcarriers is less than or equal to the maximum available number of subcarriers for this mode. For example, in 1k mode, the interleaver can work for characters with a number of subcarriers less than or equal to 1024, and for 16k mode with an number of subcarriers less than or equal to 16384.

The sequence of data cells that are carried in each COMFR symbol is then transmitted to the symbol interleaver 33. The COMFR symbol is then generated using the COMFR symbol builder block 37, which inputs pilot and synchronization signals supplied from the pilot and embedded signal generator 36. The OFDM modulator 38 then generates an OFDM symbol in the time domain, which transmits to the protection insertion processor 40 to generate a protection interval between the symbols, then to the digital and analog converter 42, and finally to the radio frequency amplifier in the preliminary Raman (RF, radio frequency) processing unit 44 for transmission, ultimately, by the COMPR transmitter via antenna 46.

As explained above, the present invention provides the ability to provide a quasi-optimal mapping of data symbols to OFDM subcarrier signals. In accordance with an exemplary technology, a symbol interleaver is provided that optimally maps input data symbols to COMPCR subcarrier signals in accordance with a permutation code and a generator polynomial that has been verified by simulation analysis.

In FIG. 2 is a more detailed exemplary illustration of a block 28 for mapping a bit to a combination of a symbol and a frame builder 32 to illustrate an exemplary embodiment of the present technology. The data bits received from the 26-bit interleaver through channel 62 are grouped into sets of bits to be mapped to a data cell, in accordance with the number of bits per symbol provided by the modulation scheme. The groups of bits that form the data word are supplied in parallel through the data transmission channels 64 to the display processor 66. The display processor 66 then selects one of the data symbols in accordance with a predetermined display. The population point is represented by the real and imaginary components, which are fed into the input channel 29 as one of the input data sets for the frame builder 32.

The frame builder 32 receives the data cells from the bit-to-aggregate mapping unit 28 through the channel 29 together with the data cells from the other channels 31. After constructing the frame from the multiple sequences of the COMR cell, the cell of each COMR symbol is then written to the interleaver 100 and read from the memory 100 the interleaver in accordance with the record addresses and read addresses generated by the address generator 102. In accordance with the write and read order, data cells are interleaved by generating corresponding addresses. The operation of the address generator 102 and the interleaver memory 100 will be described in more detail below with reference to FIG. 3-5. The data cells after interleaving are then combined with pilot and synchronization symbols received from the pilot and embedded signal generator 36 in the OFDM symbol builder 37 to form the OFDM symbol, which is supplied to the OFDM modulator 38, as explained above.

Interleaver.

In FIG. 3, an example of parts of an interleaver 33 characters is provided, which illustrates the present technology for interleaving symbols. In FIG. 3 input cells from the frame builder 32 are written to the interleaver 100. The data cells are recorded in the interleaver 100 in accordance with the recording address that is received from the address generator 102 on the channel 104, and read from the interleaver 100 in accordance with the read address provided from the address generator 102 on the channel 106. The address generator 102 generates the write address and read address, as explained below, depending on whether the COMMR symbol is odd or even, which is identified by the signal supplied from channel 108, and depending on the selected mode, which which is identified by the signal coming from channel 110. As explained above, the mode may represent one of 1k mode, 2k mode, 4k mode, 8k mode, 16k mode, or 32k mode. As explained below, the write address and the read address are generated differently for the even and odd OFDM symbols, as explained with reference to FIG. 4, which is an example embodiment of an interleaver memory 100.

In the example shown in FIG. 4, an interleaver memory is shown as having an upper portion 100 illustrating an operation of an interleaver memory in a transmitter

- 5 017061 chip, and the lower part 340, which illustrates the operation of the interleaver memory in the receiver. The interleaver 100 and the interleaver elimination unit 340 are shown together in FIG. 4, for clarity, when describing their work. As shown in FIG. 4, the presentation of communication between the interleaver 100 and the interleaving elimination unit 340 through other devices and via the transmission channel has been simplified and presented as a section 140 between the interleaver 100 and the interleaving elimination unit 340. The operation of the interleaver 100 is described in the following paragraphs.

Although in FIG. 4 shows an example of only four input data cells; for an example of four signals of a sub-carrier of the COMF symbol, it should be understood that the technique illustrated in FIG. 4 can be expanded to a larger number of subcarriers, for example, 756 for 1k mode, 1512 for 2k mode, 3024 for 4k mode, and 6048 for 8k mode, 12096 for 16k mode and 24192 for 32k mode.

The input and output addressing of the interleaver memory 100 shown in FIG. 4 are presented for even and odd characters. For even COMFR characters, data cells are sampled from input channel 77 and written to the interleaver 124.1 memory in accordance with the address sequence 120 generated for each COMFM character using the address generator 102. Record addresses are used for an even character in such a way that, as shown, interleaving is performed by rearranging the record addresses. Therefore, for each symbol, after interleaving, y (11 (c |)) = y '(c |).

For odd characters, the same interleaver memory 124.2 is used. However, as shown in FIG. 4, for odd-numbered characters, write order 132 is the same address sequence used to read the previous even-numbered character 126. This property allows the interleaver to be implemented for even and odd-numbered characters so that it will only use one interleaver memory 100 in which a read operation performed for a given address before a write operation. The data cells recorded in the interleaver memory 124 during the odd characters are then read in the sequence 134 generated by the address generator 102 for the next COMM character and so on. In this way, only one address per character is generated, while reading into the memory device and writing from the memory device for odd / even characters, COMR are performed simultaneously.

In general, as shown in FIG. 4, after the set of addresses H (q) for all active subcarriers is calculated, the input vector Υ '= ^ 0', y'1, y'2, ... umax _max - 1 ') is processed to obtain the vector Υ = ^ 0, y1, y2, ..., _Kmax -1) of interleaving defined by yN (c |) = y's. | for even characters for c. | = 0 ..... X _max -1, yn] = y'H (c |) for odd characters for c = 0, ..., N ^ -1.

In other words, for even OFDM symbols, input words are written with permutation to the memory device and sequentially read, while for odd symbols they are written sequentially and read with permutation. In the case described above, the permutation H (c |) is defined by the following table.

Permutation for the simple case when And _max = 4

t 0 one 2 3 LF) one 3 0 2

As shown in FIG. 4, the interleaving elimination unit 340 during operation performs the reverse processing of the interleaving used in the interleaver 100, applying the same set of addresses that was generated by the equivalent address generator, but applying the addresses of writing to the memory and reading from the memory in the reverse order. Moreover, for even-numbered characters, the addresses 342 of the write to the memory represent the sequence, while the addresses 344 of reading from the memory are provided by the address generator. Accordingly, for odd characters, the order 346 of writing to the storage device is determined from the set of addresses generated by the address generator, while reading 348 from the storage device is an order.

Address generation for 4k mode.

The block diagram of the algorithm used to generate the interleaving function H (c |) is shown in FIG. 5 for 4k mode. In FIG. 5, a linear feedback shift register is formed with twelve shift register stages 200 for generating addresses from 0 to 4095 and an exclusive OR gate 202 that is connected to the shift register stages 200 in accordance with the generator polynomial. Therefore, in accordance with the contents of the shift register 200, the next bit of the shift register is obtained at the output of the exclusive OR gate 202 using an exclusive OR operation with respect to the contents of the shift register K. [0] and cascade K. [2] register. In accordance with the generator polynomial, a pseudo-random sequence of bits is generated from the contents of the shift register 200. However, to generate the address for the 4k mode, as illustrated, a permutation circuit 210 is provided that effectively performs interruption

- 6 017061 new order of bits in the shift register 200 from order B ' ₁ [and] to order KDi] at the output of the permutation circuit 210. Eleven bits from the output of the permutation circuit 210 are then supplied to the connection channel 212, to which the most significant bit is added via channel 214, which is provided by the switch unit 218. Thus, an address of twelve bits is generated on channel 212. However, to ensure the authenticity of the address, the address verification circuit 216 analyzes the generated address to determine if it does not exceed the maximum number of subcarrier signals. If this happens, a control signal is generated and transmitted through the connection channel 220 to the control module 224. If the generated address exceeds the maximum number of subcarrier signals, then this address is discarded and a new address is regenerated for this particular symbol.

In general, (Ν _Γ - 1) the bitword K ' ₁ is determined for Ν _Γ = 1ο2 M _max , where M _max = 4096 in 4k mode, using LЕ8К (ЛСРОС, linear shift register with feedback).

The polynomials used to generate this sequence are as follows:

where ί varies from 0 to M _max -1.

After one word K ' _{1 has} been generated, it goes through a permutation to obtain another (Ν _Γ - 1) bit word, called K ₁ . K _{1 is} obtained from K ' ₁ as a result of the permutation of the bits defined in the table below.

Swapping bits for 4k mode

As an example for the permutation code above, this means that for 4k mode, bit number 10 K ' _{1 is} transmitted at bit position 7 for K ₁ .

The address H (c |) is then obtained from K ₁ using the following equation:

Ν.-2

N (W) = (Ϊ tiSHCH · 2 ⁴ ' ¹ + 2X 0)

Part (ίιηο62) · 2 ^Νι-1 in the above equation is shown in FIG. 5 block T218 switch.

Then, the address check for H (p. |) Is performed to verify that the generated address is in the range of acceptable addresses: if (Η (φ <Ν ^), where in one example Ν _ιηαχ = 3024 in 4k mode, then the address is valid. If the address is not valid, the control module is informed about this and it tries to generate a new H (c |) by successively increasing the index ί.

The role of the switch block is to ensure that an address greater than Ν ^ is not generated twice in a row. As a result, if an excess value is generated, this means that M8B (SZB, the most significant bit, that is, the switching bit) of the address H (s |) was equal to one. Thus, the next generated value will have the SZB set to zero, which ensures that a valid address is obtained.

The following equations bring together common behavior and help understand the structure of the loop of this algorithm:

= 0;

Gog (Ϊ = 0; ί <Mschah; · ~ ί + 0 (H (<p = (ί πιο (32) 2 ⁱ : - ¹ + 2/0) -2 ¹ ;

1G (H (<1) <H _max ) ₄ = <p1; }

For a brief explanation, in one example of an address generator, the permutation code described above is used to generate an address for all OFDM symbols. In another example, permutation codes may vary between characters, as a result of which the set of permutation codes is cyclically repeated through consecutive OFDM symbols. To this end, control lines 108, 110, along which an indication is transmitted whether the OFDM symbol is odd or even, and the indication of the current mode are used to select a permutation code. This example mode, in which a plurality of permutation codes are cyclically repeated, is particularly appropriate for an example in which only the odd interleaver is used, which is explained below. A signal indicating that a different permutation code should be used is transmitted through the control channel 111. In one example, possible permutation codes are previously stored in the code permutation circuit 210. In another example, the control unit 224 transmits a new permutation code to be used for the OFDM symbol.

Receiver.

In FIG. 6 shows an exemplary illustration of a receiver that can be used with the present technology. As shown in FIG. 6, the COMPR signal is received using an antenna 300, detected with

- 7 017061 using the tuner 302 and digitized using an analog-to-digital converter 304. A guard interval processor 306 removes the guard interval from the received COMCHR symbol before restoring data from the COMCHR symbol using the Fast Fourier Transform (FFT) processor 308 in combination with a channel estimator and a correction processor 310 that operate in conjunction with an embedded signal decoding unit 311, in accordance with known techniques. The demodulated data is restored from the display unit 312 and fed to the symbol interleaving deletion unit 314, which during operation performs a reverse mapping of the received data symbols to regenerate the output data stream with the data interleaving eliminated.

A symbol interleaver removal unit 314 is formed from a data processing device such as that shown in FIG. 6, with an interleaver memory 540 and an address generator 542. The interleaver memory is such a device as shown in FIG. 4, and works, as already described above, to eliminate interleaving by using the sets of addresses generated by the address generator 542. An address generator 542 is formed as shown in FIG. 7, and is configured to generate corresponding addresses for mapping data symbols reconstructed from each OFDM subcarrier signals to the output data stream.

The remaining parts of the COMFR receiver shown in FIG. 6 are provided for performing error correction decoding 318 for error correction and restoring the estimate of the original data.

One of the advantages provided by this description for both the receiver and the transmitter is that the symbol interleaver and the symbol interleaver eliminating unit operating in the receivers and transmitters can be switched between 1k, 2k, 4k, 8k, 16k and 32k modes by changing the polynomials of the generator and the permutation order. Therefore, the address generator 542 shown in FIG. 7 includes an input signal 544 providing a mode indication, as well as an input signal 546 indicating whether the odd / even NUMBER characters follow. In this way, a flexible embodiment is provided since the symbol interleaver and the interleaver can be formed as shown in FIG. 3 and 7, with such an address generator as shown in FIG. 5. The address generator can therefore be adapted to different modes by changing the generator polynomials and permutation orders indicated for each of the modes. For example, this can be accomplished using a software change. Alternatively, in other embodiments, the embedded signal indicative of the DTTB2 transmission mode can be detected at the receiver in the embedded signal processing module 311 and used to automatically configure the symbol deinterleaver block according to the detected mode.

Optimal use of odd interleaving.

As shown in FIG. 4, two symbol interleaving processes, one for even OFDM symbols and the other for odd OFDM symbols, can reduce the amount of memory used during interleaving. In the example shown in FIG. 4, the recording order of the odd characters is the same as the reading order of the even characters, therefore, while the odd character is read from the storage device, the even character can be written to the location from which the reading was just performed; after that, when the even-numbered symbol is read from the storage device, the next odd-numbered symbol can be written to the location from which the reading was just performed.

The choice of the generator polynomial and permutation code explained above was identified after analyzing the simulation of the relative interleaver performance. The relative performance of the interleaver was evaluated using the relative ability of the interleaver to separate consecutive characters or interleaving qualities. A relative measure of interleaver quality can be determined by determining the distance Ό (in the number of subcarriers). Criterion C is selected to identify the number of subcarriers that are at a distance <Ό at the output of the interleaver that were at a distance <Ό at the input of the interleaver, and the number of subcarriers for each distance Ό is then weighted with respect to the corresponding distance. Criterion C is evaluated for both even and odd COMPR characters. Minimizing C allows you to get an interleaver of exceptional quality.

1 where H, _yep (φ and Ν _ο11 (φ are the number of subcarriers for the even and odd symbol, respectively, at the output of the interleaver, which remains within the interval 1 between the subcarriers.

As noted above, during the experimental analysis of the operational characteristics of the interleavers (using criterion C, as defined above) and for the example shown in FIG. 8 (a) and (b) determined that the interleaving schemes developed for 2k and 8k symbol interleavers for DTTV and 4k symbol interleaver for DTV work better for odd characters than for even characters. That

- 8 017061 thus, to align the results of the operational characteristics of the interleavers, for example for 16k, as shown in FIG. 8 (a) and (b) determined that the odd interleavers work better than the even interleavers. This can be seen by comparing FIG. 8 (a), which shows the results for an interleaver for even symbols, and FIG. 8 (b), illustrating the results for odd characters: it can be seen that the average distance at the interleaver output between subcarriers that were adjacent to each other at the interleaver input is greater for the interleaver for odd characters than in the interleaver for even characters.

As you can understand, the amount of interleaver memory required to implement the character interleaver depends on the number of data characters that need to be mapped onto characters bearing COMFR. Thus, a 16k symbol interleaver requires half the storage space required to implement the 32k mode interleaver, and likewise, the amount of memory required to implement an 8k symbol interleaver is half that required for the 16k interleaver. Therefore, when the transmitter or receiver is configured to implement the symbol interleaver in a mode that sets the maximum number of data symbols that can be transmitted to the OFDM symbol, such a receiver or transmitter will include enough memory to implement two odd interleaving processes for any other mode which provides half or less than half the number of subcarriers per OFDM symbol in this given maximum mode. For example, a receiver or transmitter including an 32k interleaver will have enough memory to accommodate two odd 16k interleaving processes, each of which occupies its own 16k memory.

Therefore, to use the best characteristics of the odd interleaving process, the symbol interleaver configured to accommodate a plurality of modulation modes can be arranged such that only the odd interleaving process of characters will be used in a mode that contains half or less than half the number of subcarriers in the maximum mode that represents The maximum number of subcarriers per OFDM symbol. Therefore, maximum mode sets the maximum memory size. For example, in a transmitter / receiver that is capable of operating in 32k mode, when operating in a mode with fewer carriers (i.e., 16k, 8k, 4k or 1k), instead of using a separate even and odd symbol interleaving process, two odd interleavers can be used.

In FIG. 9 shows an adaptation illustration of the symbol interleaver 33, which is shown in FIG. 3, when the interleaving of input data symbols onto subcarriers of OFDM symbols is performed only in the odd interleaving mode. The symbol interleaver 33.1 corresponds exactly to the symbol interleaver 33 shown in FIG. 3, except that the address generator 102.1 is configured to perform only the process of odd interleaving. For the example shown in FIG. 9, the symbol interleaver 33.1 operates in a mode in which the number of data symbols that can be transmitted for the OFDM symbol is less than half the maximum amount that can be carried by the OFDM symbol in an operation mode with the largest number of subcarriers to the OFDM symbol. In this case, the interleaver 33.1 characters is arranged so that it shares the storage device 100 of the interleaver. For the present illustration shown in FIG. 9, the interleaver memory 100 is then divided into two parts 401, 402. As an illustration of the symbol interleaver 33.1 operating in a mode in which data symbols are mapped to OFDM symbols using the odd interleaving process, FIG. 9 is an exploded view of each half of an interleaver memory 401, 402. This exploded view is an illustration of the odd-numbered mode as shown for the transmitter side for the four characters A, B, C, Ό reproduced in FIG. 4. Thus, as shown in FIG. 9, for consecutive sets of first and second data symbols, data symbols are written to the interleaver 401, 402 in sequence, and read in permutation according to the address generated by the address generator 102, as explained above. Thus, as shown in FIG. 9, since the odd interleaving process is performed for successive sets of the first and second sets of data symbols, the interleaver memory must be divided into two parts. Symbols from the first set of data symbols are recorded in the first half of the interleaver memory 401, and symbols from the second set of data symbols are symbols that are recorded in the second part of the interleaver 402. This is because the symbol interleaver is no longer able to reuse the same parts of the symbol interleaver memory that can be allocated when operating in the even and odd interleaving modes.

A corresponding example of an interleaver in a receiver, which is shown in FIG. 7, but which is configured to work only with the process of odd interleaving, is shown in FIG. 10. As shown in FIG. 10, the interleaver memory 540 is divided into two halves 410, 412, and the address generator 542 is configured to write data symbols to the interleaver memory and read data symbols from the interleaver memory, respectively

- 9 017061 interleaving memory parts 410, 402 of the interleaver for consecutive sets of data symbols when implementing only the process of odd interleaving. Therefore, in accordance with the representation shown in FIG. 9, in FIG. 10 shows a display of the interleaving process that is performed at the receiver and which is shown in FIG. 4, as an exploded view, working for both the first and second halves of the interleaver memory 410, 412. Thus, the first set of data symbols is recorded in the first part of the interleaver memory 410 in the permutation order determined in accordance with the addresses generated by the address generator 542, as represented by the recording order in the data symbols, which provides a sequence of 1, 3, 0, 2 entries. As shown, the data symbols are then read from the first part of the interleaver memory 410 in sequence, thereby restoring the original sequence A, B, C, Ό.

Accordingly, a second subsequent set of data symbols that are reconstructed from the serial OFDM symbol are recorded in the second half of the interleaver memory 412 in accordance with the addresses generated by the address generator 542 in the permutation order and read into the output data stream in the sequence.

In one example, the addresses generated for the first set of data symbols for writing to the first half of the interleaver memory 410 can be reused to write the second consecutive set of data symbols in the interleaver memory 412. Accordingly, the transmitter can also reuse the addresses generated for one half of the interleaver for the first set of data symbols, for reading the second set of data symbols that were recorded in the second half of the storage device in sequence.

Odd interleaver with offset.

The performance of an interleaver using two odd interleavers can be further improved by using a sequence of only odd interleavers instead of using only one odd interleaver, so that any data bit supplied for interleaving does not always modulate the same character carrier OFDM

A sequence consisting only of odd interleavers can also be implemented by adding an offset to the interleaver address equal to the modulus of the number of carriers carrying data; or using a sequence of permutations in an interleaver.

Add offset.

Adding an offset to the interleaver address equal to the modulus of the number of carriers carrying data effectively shifts and performs ring shift of the OFDM symbol so that any data bit entered into the interleaver is not always modulated to the same carrier of the OFDM symbol. Thus, the address generator may, if necessary, include a bias generator that generates a bias at the address generated by the address generator on the output channel H (q).

An offset can change each character. For example, such an offset may provide a cyclic sequence. This cyclic sequence may, for example, have a length of 4 and may consist, for example, of primes. For example, such a sequence may be 0, 41, 97, 157.

In addition, the offset can be a random sequence that can be generated by another address generator from a similar interleaver of OFDM symbols or can be generated using some other means.

Using a sequence of permutations.

As shown in FIG. 5, the control line 111 continues from the control module of the address generator to the permutation circuit. As noted above, in one example, the address generator may apply another permutation code from the set of permutation codes for consecutive OFDM symbols. Using a sequence of permutations in the interleaver address generator reduces the likelihood that any bit of data input into the interleaver will modulate the same subcarrier of the OFDM symbol.

For example, such a sequence may be a cyclic sequence, such that a different permutation code in the set of permutation codes in the sequence is used for consecutive OFDM symbols and then repeated. Such a cyclic sequence may, for example, be two or four. For an example of a 4k symbol interleaver, a sequence of two permutation codes that are cyclically repeated for the OFDM symbol can be, for example:

10 5 8 1 2 4 9 0 3 6 **

2 7 10 8 0 3 4 1 9 5 whereas a sequence of four permutation codes can be

10 5 8 1 2 4 9 0 3 6 **

2 7 10 8 0 3 4 1 9 5

- 10 017061

5 4 2 3 10 10 6 8 7

4 10 3 9 7 2 6 5 0 8

Switching one permutation code to another code may be performed in response to an odd / even signal change on the control channel 108. In response, the control unit 224 changes the permutation code in the permutation code circuit 210 through the control line 111.

For example, the symbol interleaver 1k, two permutation codes can be

3 2 10 5 6 7 8

2 5 0 1 4 7 8 6 whereas four permutation codes can be

3 2 10 5 6 7 8

2 5 0 1 4 7 8 6

5 3 8 2 6 1 4 0

I 6 8 2 5 3 4 0 7

Other combinations of sequences may be possible for 2k, 4k and 16k carrier modes or, of course, for 0.5k carrier modes. For example, the following permutation codes for each of the 0.5k, 2k, 4k, and 16k modes provide good decorrelation of characters, and they can be used cyclically to generate an offset for the address generated by the address generator for each of the corresponding modes:

2k mode:

7 5 1 8 2 6 9 3 4 *

8 3 2 9 0 1 5 6 7

3 9 0 2 1 5 7 4 6

0 4 8 3 6 9 1 5 2

8k mode:

11 3 0 10 8 6 9 2 4 1 7 *

10 7 6 0 5 2 1 3 9 4 11

II 3 6 9 2 7 4 10 5 10 8

8 1 7 5 6 0 11 4 2 9 3

16k mode:

4 3 2 0 11 1 5 1 2 10 6 7 9

9 5 3 11 1 4 0 2 1 2 10 8 6

11 7 5 2 3 0 11 0 8 1 2 9 4

1 2 9 0 3 10 2 4 6 7 8 11 1

For the permutation codes indicated above, the first two can be used in two cycles of the sequence, while all four can be used for four cycles of the sequence. In addition, some additional sequences of four permutation codes, which are cyclically repeated to provide a bias in the address generator, to obtain good decorrelation in characters received after interleaving (some of which are identical to the ones given above), are provided below.

0.5k mode:

7 4 6 1 2 0 5

2 5 7 3 0 1 6

3 6 0 4 1 2 7

1 0 5 2 7 4 3

2k mode:

7 5 1 8 2 6 9 3 4 *

2 7 0 1 5 8 4 9 6

8 3 2 9 0 1 5 6 7

3 9 5 2 1 0 6 4 8

4K mode:

10 5 8 1 2 4 9 0 3 6 **

2 7 10 8 0 3 4 1 9 5

3 4 1 2 7 0 6 8 5 9

8 9 5 10 4 6 3 2 1 7

8k mode:

11 3 0 10 8 6 9 2 4 1 7 *

8 5 4 2 9 10 6 7 3 11

6 9 8 4 7 2 10 10 5 3

3 11 7 9 1 5 6 4 0 2 10 * - these permutations are intended for the standard DTV, ** - these permutations are intended for the standard DTV.

Examples of address generators and corresponding interleavers for 2k, 4k and 8k modes are disclosed

- 11 017061 in the application for European patent No. 04251667.4, the contents of which are incorporated herein by reference. An address generator for the 0.5k mode is disclosed in our pending UK patent application No. 0722553.5. Various modifications may be made to the embodiments described above without departing from the scope of the present invention. In particular, an exemplary representation of the generator polynomial and permutation order that were used to represent aspects of the invention is not intended to be limiting and continues to the equivalent forms of the generator polynomial and permutation order.

It should be understood that the transmitter and receiver shown in FIG. 1 and 6, respectively, are provided for illustration only and are not intended to be limiting. For example, it should be understood that the position of the symbol interleaver and the interleaving elimination unit with respect to, for example, the bit interleaver and the display unit and the display eliminating unit can be changed. It should be understood that the effect introduced by the interleaver and the interleaving elimination unit does not change depending on its relative position, although the interleaver can perform interleaving Ι / O (in-phase and in quadrature) symbols instead of ν-bit vectors. Corresponding changes can be made to the receiver. Accordingly, the interleaver and the deinterleaver can operate with different types of data and can be installed in other places, rather than in the positions described in the exemplary embodiments.

In accordance with one embodiment of the receiver, a data processing device is provided for displaying symbols received from a predetermined number of signals of a frequency division multiplexed (OFDM) subcarrier symbol into an output signal symbol stream.

As explained above, the permutation codes and polynomial of the interleaver generator, which were described with reference to the embodiment of a particular mode, can equally be applied to other modes by changing the specified maximum allowed address in accordance with the number of subcarriers for this mode.

As noted above, embodiments of the present invention are intended for use in DTV standards, such as DTTV, DTTV2 and DTV, which are incorporated herein by reference. For example, embodiments of the present invention can be used in a transmitter or receiver operating in accordance with the DTV standard, in mobile terminals or handsets. Mobile terminals can be integrated with mobile phones (second, third or higher generation) or handheld personal computers or, for example, with tablet PCs. Such mobile terminals may be able to receive signals compatible with DTV or DTVB inside buildings or when moving, for example, in train trains, even at high speed. Mobile terminals can, for example, operate on batteries, on an electrical network or on a low voltage direct current source, or on a car battery. Services that can be provided by DTV can include voice services, messaging, browsing the Internet, listening to the radio, watching still and / or moving video images, television services, interactive services, video broadcasts or broadcasts close to video on demand, and other options . Services can work in combination with each other. In other examples, embodiments of the present invention can be applied to the DTTB2 standard, as defined in accordance with standard ΕΤ8Ι (European Telecommunication Standardization Institute) ΕΝ 302755. In other exemplary embodiments of the present invention, the present invention may find application in the cable data standard known like DTV-C2. However, it should be understood that the present invention is not limited to use with DTV and can be extended to other standards for the transmission or reception of both fixed and mobile.

Claims (52)

CLAIM 1. A data processing device configured to display input characters for transmitting a predetermined number of subcarrier signals of a symbol orthogonally frequency division multiplexed (OFDM), comprising an interleaver configured to read a predetermined number of data symbols into a memory device for mapping onto subcarrier signals OFDM and read from the storage device data symbols for the subcarriers of OFDM to perform the display, and reading from the memory guide devices operate in a different order than the reading of the memory device, wherein the order determined by the set of addresses, whereby the data symbols are interleaved on the sub-carrier signals; an address generator, configured to generate a set of addresses, the addresses being generated for each of the input symbols to indicate one of the subcarrier signals onto which the data symbol is to be mapped, comprising a linear shift register with feedback including a predetermined number of register stages and executed with the ability to generate a pseudo-random sequence of bits in accordance with the generator polynomial; - 12 017061 permutation scheme, configured to receive the contents of the cascades of the shift register and permutation of the bits present in the cascades of the register, in accordance with the permutation code and the polynomial of the generator to generate the address; a control module configured to, in combination with the address verification circuitry, re-generate the address when the generated address exceeds a predetermined maximum real address at which a predetermined maximum real memory address and a predetermined number of subcarriers are approximately four thousand; a linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback ⁼ Α-ι [θ] ® Α-ιΜ and the permutation code forms an address of twelve bits with an additional bit, characterized in that the permutation circuit is arranged so that it changes the permutation code, which permutes the order of the bits of the register cascades to form addresses from one OFDM symbol to another. 2. The data processing device according to claim 1, in which the permutation circuit is configured to cyclically repeat a sequence of different permutation codes for consecutive OFDM symbols during operation. 3. The data processing device according to claim 2, in which one of the sequence of different permutation codes generates an address K ₁ [i] consisting of twelve bits for the ί-th data symbol from the bit represented in η-th K ' ₁ [and] register cascade in accordance with the permutation code defined in the table ____________________________________________________________________ Bit position K. '; [n] Gog n = 10 9 8 7 6 5 4 3 2 1 0 The position of the bit K [and] Gog n = 7 10 58 1249036 4. The data processing device according to claim 2 or 3, in which the sequence of permutation codes contains two permutation codes, which are The position of the bit K. ’, [n] Gogh n = 10 98765432 10 The position of the bit K [and] Gog n = 7 10 58 1249036 and _________________________________________________________________ The position of the bit K. \ [n] Gogh n = 10 9876543210 The position of the bit K, [n] Gog n = 6 2 7 10 8 0 3 4 1 9 5 5. The data processing device according to claim 1, in which the specified maximum valid address is a value essentially between two thousand and four thousand and ninety-six. 6. The data processing device according to claim 5, in which the OFDM symbol includes pilot subcarriers that are capable of carrying known symbols, and the predetermined maximum valid address depends on the number of pilot subcarriers present in the OFDM symbol. 7. The data processing device according to claim 1, in which approximately four thousand subcarriers are provided in one of a plurality of operating modes, in which approximately four thousand subcarriers provide half or less than half the maximum number of subcarriers in OFDM symbols in any of the operating modes, and input data symbols include first sets of input data symbols for displaying on first OFDM symbols and second sets of input data symbols for displaying second OFDM symbols, wherein the processing device data during operation interleaves the input data symbols from both the first and second sets in accordance with the processing of the odd interleaving, and the processing of the odd interleaving includes the steps of writing the first sets of input data characters to the first part of the interleaver memory in accordance with the order of the first sets of input data characters; reading the first sets of input data symbols from the first part of the interleaver memory into the signals of the subcarriers of the first OFDM symbols in accordance with the order determined by the set of addresses generated by one of the sequence permutation codes; recording a second set of input data symbols in a second part of the interleaver memory in accordance with the sequence of the second sets of input data symbols; read the second sets of input data symbols from the second part of the interleaver memory onto the subcarrier signals of the second OFDM symbols in accordance with the order determined by the set of addresses generated with other of the sequence permutation codes. 8. A transmitter for transmitting input data symbols using frequency division orthogonal multiplexing (OFDM), the transmitter including a data processing device for mapping input data symbols to a predetermined number of OFDM symbol subcarrier signals, the data processing device includes an interleaver that reads during operation in the storage device, a predetermined number of data symbols for displaying on the OFDM subcarrier signals and reading from the storage - 13 017061 device data symbols for subcarriers OFDM to perform the display, and the reading from the storage device is performed in a different order than the reading in the storage device, the order is determined by the set of addresses, resulting in the interleaving of data symbols on the signals of the subcarriers; an address generator, configured to generate a set of addresses during operation, the address being generated for each of the input symbols, for mapping to one of the subcarrier signals, comprising a linear shift register with feedback including a predetermined number of register stages and generating during operation a pseudo-random sequence of bits in accordance with the generator polynomial; a permutation circuit configured to receive the contents of the shift register cascades and perform permutation of the order of bits present in the register cascades in accordance with the permutation code to form the address; a control module configured to, during operation, in combination with an address verification circuit, re-generate an address when the generated address exceeds a predetermined maximum real address at which a predetermined maximum real memory address and a predetermined number of subcarriers are approximately four thousand; A linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback M ¹⁰ ! ⁼ Αι [θ] ® ΑιΜ and the permutation code generates an address of twelve bits with an additional bit, characterized in that the permutation circuit is capable of changing the permutation code, which permutes the order of the bits in the register stages to form addresses from one OFDM symbol to another. 9. The transmitter of claim 8, wherein the transmitter is capable of transmitting data in accordance with a Digital Television Broadcasting standard, such as a Digital Terrestrial Television broadcasting standard, a Digital Terrestrial Broadcasting standard for mobile phones, or a Digital Terrestrial Broadcasting standard 2. 10. A method of displaying input symbols for transmitting to a predetermined number of signals of subcarriers of an orthogonal frequency division multiplexed symbol (OFDM), comprising the steps of: reading a predetermined number of data symbols into a memory device for mapping onto the OFDM subcarrier signals; reading data symbols for the OFDM subcarrier from the storage device for display, wherein reading from the storage device is performed in a different order than reading into the storage device, the order is determined by a set of addresses, as a result of which data symbols are interleaved with subcarrier signals; generating a set of addresses, the address being generated for each of the input symbols to indicate one of the subcarrier signals onto which the data symbol is to be mapped, generating a set of addresses comprises the steps of using a linear shift register with feedback including a given number of register stages , to generate a pseudo-random sequence of bits in accordance with the generator polynomial; using permutation schemes, which during operation, accept the contents of the shift register stages to rearrange the order of bits present in the register stages, in accordance with the permutation code for generating the address; re-generate the address when the generated address exceeds the specified maximum valid address, in which the specified maximum valid memory address and the specified number of subcarriers are approximately four thousand; a linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback ί ~ H and the permutation code generates an address of twelve bits with an additional bit, characterized in that they change the permutation code, which permutes the order of the bits of the register cascades, to form a set of addresses from one OFDM symbol to another. 11. The method of claim 10, wherein changing the permutation code includes cyclically repeating a sequence of different permutation codes for consecutive OFDM symbols. 12. The method according to claim 11, in which one of the sequence of different permutation codes generates twelve address bits KDP] for the ί-th data symbol from the bit present in the η-th stage K ' ₁ [p] of the register in accordance with the permutation code, defined by table - 14 017061 Bit position T <', [n] Gog n = Bit position K; [and] Gogh n = 10 9876543210 7 10 581249036 13. The method according to claim 11 or 12, in which the sequence of permutation codes contains two permutation codes, which are Bit position K ', [n] Gog n = K bit position; [and] Gogh n = 9876543210 10 5 8 1 Bit position K) [n] Gog n = The position of the bit K [and] Gog n = 627 10 8034195 14. The method of claim 10, wherein the predetermined maximum valid address is a value essentially between two thousand and four thousand and ninety-six. 15. The method of claim 14, wherein the OFDM symbol includes pilot subcarriers that are capable of carrying known symbols, and the predetermined maximum valid address depends on the number of pilot subcarriers present in the OFDM symbol. 16. The method of claim 10, wherein approximately four thousand subcarriers are provided in one of a plurality of operating modes, wherein approximately four thousand subcarriers provide half or less than half the maximum number of subcarriers of OFDM symbols in any of the operating modes, the method comprising splitting input data symbols including first sets of input data symbols for mapping to first OFDM symbols and second sets of input data symbols for mapping to second OFDM symbols; interleaving the input data symbols from both the first and second sets in accordance with an odd interleaving process comprising recording the first sets of input data symbols in the first part of the interleaver memory in accordance with the sequence of the first sets of input data symbols; reading the first sets of input data symbols from the first part of the interleaver memory onto the signals of the subcarriers of the first OFDM symbols in accordance with the order determined by the set of addresses generated by one of the sequence permutation codes; recording the second set of input data symbols in the second part of the interleaver memory in accordance with the sequence of the second sets of input data symbols; reading the second sets of input data symbols from the second part of the interleaver memory onto the signals of the subcarriers of the second OFDM symbols in accordance with the order determined by the set of addresses generated with other of the sequence permutation codes. 17. A method for transmitting data using orthogonal frequency division multiplexing (OFDM), comprising the steps of reading a predetermined number of data symbols into a memory device for mapping onto the OFDM subcarrier signals; reading data symbols for the OFDM subcarriers from the storage device to perform display, wherein reading from the storage device is performed in a different order than reading into the storage device, the order is determined from the set of addresses, as a result of which the data symbols are interleaved with subcarrier signals; generating a set of addresses, the address being generated for each of the input symbols to be mapped onto one of the subcarrier signals, the generating of the set of addresses comprising the steps of using a linear shift register with feedback including a predetermined number of register stages to generate a pseudo-random sequence of bits in accordance with the generator polynomial; using a permutation scheme, during operation, receiving the contents from the cascades of the shift register to rearrange the order of bits present in the cascades of the register in accordance with the permutation code to generate the address, and regenerate the address when the generated address exceeds the specified maximum valid address, while the specified the maximum valid memory address and the specified number of subcarriers is approximately four thousand; a linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback ί ~ [ ² ] and the permutation code forms an address of twelve bits with an additional bit, characterized in that they change the permutation code, which permutes the order of the cascade bits register for the formation of a set of addresses from one symbol of the OFDM to another. 18. The transmission method of claim 17, wherein the transmission includes transmitting in accordance with a Digital Television Broadcasting standard, such as a Digital Terrestrial Television Broadcasting standard, a Digital Terrestrial Broadcasting Standard for mobile phones, or a Digital Standard - 15 017061 terrestrial broadcasting 2. 19. An address generator for use in transmitting data symbols for which an orthogonally frequency division multiplexed (OFDM) symbol was interleaved into subcarriers, the address generator during operation generates a set of addresses, each address is generated for each of the data symbols to map data symbols to one of the subcarrier signals, and the address generator contains a linear shift register with feedback, which includes a given number of register stages and during operation generate s pseudo-random bit sequence in accordance with a generator polynomial; a permutation circuit that, during operation, receives the contents of the shift register cascades and performs a permutation of the order of bits present in the register cascades, in accordance with the permutation code, to form the address; a control module, during operation in combination with an address verification circuit, generating an address when the generated address exceeds a predetermined maximum real address in which a predetermined maximum real memory address and a predetermined number of subcarriers are approximately four thousand; a linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback 1 ^D - ί ~ X М® X Н and the permutation code forms an address of twelve bits with an additional bit, characterized in that the permutation circuit is executed with the ability to change the permutation code, on the basis of which the permutation of the order of the bits of the register cascades is performed, to form a set of addresses from one OFDM symbol to another. 20. The address generator according to claim 19, in which the permutation scheme during operation cyclically uses a sequence of different permutation codes for consecutive OFDM symbols. 21. The address generator according to claim 20, in which one of the sequence of different permutation codes generates addresses K ₁ [n] from twelve bits for the ί-th character from the bit present in the ηth cascade of the register K ' ₁ [n] in accordance with permutation code defined by table The position of the bit KD [p] Gog p = 10 9876543210 The position of the bit K, [n] Gog n = 710581249036 22. The address generator according to claim 20 or 21, in which the sequence of permutation codes contains two permutation codes, which are The position of the bit KD [p] Gog p The position of the bit DB [p] Gog p = The position of the bit KD [and] Gog n = The position of the bit K., [n] Gog n = 10 9876543210 7 10 5 8 Ϊ 2 4 9 b 3 6 10 9876543210 6 ~ 2 7 10 8 b 3 4 ΐ 9 5 23. A data processing device for displaying symbols received from a predetermined number of frequency division multiplexed symbol (OFDM) subcarrier signals (OFDM) into an output symbol stream containing an interleaving elimination unit, during operation, reading into a memory device a predetermined number of data symbols from OFDM subcarrier signals and reading data symbols from the storage device into the output symbol stream for displaying, reading from the storage device is performed in In a different order than reading into the storage device, the order is determined by the set of addresses, as a result of which elimination of the interleaving of data symbols from the OFDM subcarrier signals is performed; an address generator, during operation, generating a set of addresses, the address being generated for each of the received data symbols to map the data symbol received from the OFDM subcarrier signal to the output symbol stream, the address generator containing a linear shift register with feedback, including the number of stages of the register and configured to generate a pseudo-random sequence of bits in accordance with the generator polynomial; a permutation circuit, during operation, receiving the contents from the cascades of the shift register and performing permutation of the bits present in the cascades of the register, in accordance with the permutation code, to form the address for one of the subcarriers of the OFDM; a control module, during operation in conjunction with the address verification circuitry, re-generating the address when the generated address exceeds a predetermined maximum real address, in which a predetermined maximum real memory address and a given number of subcarriers are approximately four thousand; feedback linear shift register has eleven register stages with polynomial - 16 017061 generator for a linear shift register with feedback and the permutation code generates with an additional bit an address of twelve bits, characterized in that the permutation circuit is configured to change the permutation code, in accordance with which the permutation of the order of the bits of the register cascade is performed to form a set addresses from one OFDM symbol to another. 24. The data processing device according to item 23, in which the permutation circuit during operation cyclically works with a sequence of different permutation codes for consecutive OFDM symbols. 25. The data processing device according to paragraph 24, in which one of the sequences of different permutation codes generates an address K ₁ [p] of twelve bits for the ί-th data symbol from the bit present in the p-th cascade K ' ₁ [p] of the register in accordance with the permutation code defined in the table Bit position K ', [n] £ og n = 1098765 4 3210 The position of the bit K, [n] Gog n = 7 10 58 1249036 26. The data processing device according to paragraph 24 or 25, in which the sequence of permutation codes contains two permutation codes, which are Bit position K ', [n] Gog n = 10 98765 4 3210 The position of the bit K, [and] Gog n = 7 10 581249036 and ________________________________________________________________ Bit position K /, [n] Gog n = 10 9876543210 The position of the bit K, [and] Gog n = 6271080341 95 27. The data processing device according to item 23, in which the specified maximum valid address is a value essentially between two thousand and four thousand and ninety-six. 28. The data processing apparatus according to claim 27, wherein the OFDM symbol includes pilot subcarriers that are arranged to carry known symbols, and the predetermined maximum valid address depends on the number of pilot subcarrier symbols present in the OFDM symbol. 29. The data processing apparatus of claim 23, wherein approximately four thousand subcarriers are provided in one of a plurality of operating modes, wherein approximately four thousand subcarriers provide half or less than half the maximum number of subcarriers in OFDM symbols in any of the operating modes, and symbols the data includes first sets of data symbols received from the first OFDM symbols, and second sets of data symbols received from the second OFDM symbols, and the data processing device performs eliminating the interleaving of the first and second sets of data symbols in the output data stream in accordance with the processing of the odd interleaving, the processing of the odd interleaving includes the steps of writing the first sets of data symbols received from the subcarriers of the first OFDM symbols to the first part of the interleaver memory in accordance with the order determined by the set of addresses generated with one of the sequence permutation codes; reading the first sets of data symbols from the first part of the interleaver memory into an output data stream in accordance with the sequence of the first sets of input data symbols; writing a second set of data symbols received from subcarriers of the second OFDM symbols to the second part of the interleaver memory in accordance with the order determined from the set of addresses generated with another of the sequence permutation codes; read the second sets of data symbols from the second part of the interleaver memory into the output data stream in accordance with the sequence of the second sets of input data symbols. 30. A receiver for receiving data from symbols modulated with orthogonal frequency division multiplexing (OFDM), the receiver being configured to receive OFDM symbols to recover data symbols from a predetermined number of OFDM symbol subcarriers, the receiver includes a data processor that is configured to the ability to display data symbols received from the OFDM symbols into the output data stream, the data processor comprising an interleaving elimination unit, which reads into memory during operation a specified number of data symbols from the OFDM subcarrier symbols and reading data symbols from the storage device to the output data stream for displaying, wherein the reading order from the storage device is different from reading into the storage device, the order is determined by the set of addresses, as a result of which elimination is performed interleaving data symbols from OFDM subcarrier signals; an address generator, during operation generating a set of addresses, the address being generated for - 17 017061 of each of the received data symbols for mapping the received data symbols from the OFDM subcarrier signal to the symbol output stream, the address generator contains a linear shift register with feedback including a predetermined number of register stages and during operation generating a pseudo-random bit sequence in accordance with generator polynomial; a permutation circuit that, during operation, receives the contents of the shift register cascades and performs a permutation of the order of bits present in the register stages in accordance with the permutation code to form the address of one of the OFDM subcarriers; a control module operating in combination with an address verification circuitry for re-generating an address when the generated address exceeds a predetermined maximum real address at which a predetermined maximum real memory address and a predetermined number of subcarriers are approximately four thousand; a linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback = k ι [θ] ® ^ .- ι [ ² ] and the permutation code forms an address of twelve bits with an additional bit, characterized in that the permutation scheme is configured to change the permutation code, in accordance with which the permutation of the order of the bits of the register cascades is performed to form a set of addresses from one OFDM symbol to another. 31. The receiver of claim 30, wherein the receiver is configured to receive data modulated in accordance with a Digital Television Broadcasting standard, such as a Digital Terrestrial Television Broadcasting standard, a Digital Terrestrial Broadcasting Standard for mobile phones, or a Digital Terrestrial Broadcasting standard 2. 32. A method of displaying symbols received from a predetermined number of signals of subcarriers of an orthogonally frequency division multiplexed (OFDM) symbol onto a stream of output symbols, the method comprising the steps of reading a predetermined number of data symbols from the signals of the OFDM subcarriers into the memory; reading data symbols from the storage device into the output data stream for display, moreover, reading from the storage device is performed in a different order than reading into the storage device, the order is determined by the set of addresses, as a result of which the interleaving of the OFDM subcarrier signals is eliminated in the data symbols; generating a set of addresses, the address being generated for each of the received data symbols, to indicate the OFDM subcarrier signal from which the received data symbol is to be mapped to the symbol output stream, the generation of the address set comprising the steps of using a linear shift register with feedback, including a predetermined number of register stages, for generating a pseudo-random sequence of bits in accordance with a generator polynomial; using a permutation scheme for receiving the contents of the shift register stages and performing a permutation of the order of bits present in the register stages in accordance with the permutation code to generate an address; re-generate the address when the generated address exceeds the specified maximum valid address, in which the specified maximum valid memory address and the specified number of subcarriers are approximately four thousand; a linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback I ^th * & ~ Μ® ^ -ι I ² ] and the permutation code forms an address of twelve bits with an additional bit, characterized in that they change permutation code, in accordance with which the permutation of the order of the cascade bits of the register is performed to form a set of addresses from one OFDM symbol to another. 33. The method according to p, in which changing the permutation code includes the cyclical use of a sequence of different permutation codes for consecutive OFDM symbols. 34. The method according to p. 33, in which one of the sequences of different permutation codes that form the address K ₁ [p] of the twelve bits for the ί-th data symbol from the bit present in the η-th cascade K ' ₁ [p] register, in accordance with the permutation code is determined by the table ___________ The position of the bit B. '; [n] Gogh n = 10 9876543210 The position of the bit K, [n] Gog n = 7 10 581249036 35. The method according to p. 33 or 34, in which the sequence of permutation codes contains two permutation codes, which are The position of the bit B. \ [n] Gog n = 10 98765432 1 0 B bit position; [n] Gogh n = 7 10 58 1249036 - 18 017061 and The position of the bit K. ', [n] Gogh n = 10 9876543210 The position of the bit K, [n] Gog n = 627 10 8034195 36. The method according to p, in which the specified maximum valid address is a value essentially between two thousand and four thousand and ninety-six. 37. The method of claim 36, wherein the OFDM symbol includes pilot subcarriers that are capable of carrying known symbols, and the predetermined maximum valid address depends on the number of pilot subcarrier symbols present in the OFDM symbol. 38. The method of claim 32, wherein approximately four thousand subcarriers are provided in one of a plurality of operating modes, wherein approximately four thousand subcarriers provide half or less than half the maximum number of subcarriers in OFDM symbols in any of the operating modes, and the data symbols include the first sets of data symbols received from the first OFDM symbols and the second sets of data symbols received from the second OFDM symbols and read a predetermined number of characters in the memory fetching data from the OFDM subcarrier signals and reading data symbols from the memory device into the output symbol stream in accordance with the odd interleaving process, the odd interleaving process including: write the first sets of data symbols received from the subcarriers of the first OFDM symbols to the first part of the interleaver memory in accordance with the order determined by the set of addresses generated with one of the sequence permutation codes; reading the first sets of data symbols from the first part of the interleaver memory into an output data stream in accordance with the sequence of the first sets of input data symbols; writing a second set of data symbols received from subcarriers of the second OFDM symbols to the second part of the interleaver memory in accordance with the order determined by the set of addresses generated with another of the sequence permutation codes; read the second sets of data symbols from the second part of the interleaver memory into the output data stream in accordance with the sequence of the second sets of input data symbols. 39. A method of receiving data from symbols modulated with orthogonal frequency division multiplexing OFDM, comprising the steps of receiving data symbols from a given number of signals of subcarriers of an orthogonally multiplexed frequency division multiplexed (OFDM) symbol for generating symbols in the output stream; reading a predetermined number of data symbols from the OFDM subcarrier signals into the storage device; reading data symbols from the storage device into the output symbol stream for displaying, wherein the reading is performed in a different order than reading into the storage device, the order is determined from the set of addresses, as a result of which the interleaving of the data symbols from the OFDM subcarrier signals is performed; generating a set of addresses, the address being generated for each of the received symbols, for mapping the received data symbols from the OFDM subcarrier signal, to the output symbol stream, the generating of the address set comprising the steps of using a linear shift register with feedback including a predetermined number register stages, for generating a pseudo-random sequence of bits in accordance with the generator polynomial; using a permutation scheme for receiving the contents of the shift register cascades and permuting the order of bits present in the register cascades, in accordance with the permutation order for generating the address; re-generate the address when the generated address exceeds the specified maximum valid address, in which the specified maximum valid memory address and the specified number of subcarriers are approximately four thousand; A linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback M ¹⁰ ! ⁼ Α-ιΜ _{and the} permutation _code forms an address of twelve bits with an additional bit, characterized in that they change the permutation code, on the basis of which the permutation of the bit order in the register stages is performed to form a set of addresses from one OFDM symbol to another. 40. The method according to § 39, in which the data reception is performed in accordance with the standard of Digital television broadcasting, such as the standard of Digital terrestrial television broadcasting, standard - 19 017061 Digital terrestrial broadcasting for mobile phones or Digital terrestrial broadcasting standard 2. 41. An address generator for use in receiving data symbols arranged alternately on subcarriers of an orthogonal frequency division multiplexed symbol, wherein the address generator is configured to generate a set of addresses, each address is generated for each of the data symbols to indicate one of the subcarrier signals to which this data symbol is to be mapped, containing a linear shift register with feedback, including a given number of regression cascades pa and operable to generate a pseudo-random bit sequence in accordance with a generator polynomial; a permutation circuit that, during operation, receives the contents of the shift register cascades and performs a permutation of the order of bits present in the register cascades in accordance with the permutation code to form the address; a control module, during operation in combination with an address verification circuitry, re-generating an address when the generated address exceeds a predetermined maximum real address, in which a predetermined maximum real memory address and a predetermined number of subcarriers are approximately four thousand; A linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback AI® AD-] _{and the} permutation code forms with an additional bit an address of twelve bits, characterized in that the permutation circuit is designed to change permutation code, on the basis of which the permutation of the order of the bits of the cascades of the register is performed to form a set of addresses from one OFDM symbol to another. 42. The address generator according to paragraph 41, in which the permutation scheme during operation cyclically uses a sequence of different permutation codes for consecutive OFDM symbols. 43. The address generator according to claim 42, wherein one of the sequence of different permutation codes generates an address Κ ₁ [η] of twelve bits for the ίth data symbol from the bit present in the ηth cascade Κ ' ₁ [η] of the register according to the permutation code defined in the table ______ The position of the bit K. ', [and] Gogh n = 10 98765432 1 O The position of the bit K, [and] Gog n = 7 10 58 1249036 44. The address generator according to claim 42 or 43, wherein the sequence of permutation codes comprises two permutation codes, which are The position of the bit K. ', [n] Gog n = Bit position K, [n] Gog n = 9876543210 10 58 1 249036 Bit position K ', [n] Gog n = The position of the bit K, [and] Gog n = 10 9876543210 6 ~ 2 7 10 8 0 3 4 Ϊ 9 5 45. A data processing device configured to display input data symbols intended to transmit frequency-division multiplexing OFDM symbols to a predetermined number of subcarrier signals of OFDM, the predetermined number of subcarrier signals being determined in accordance with one of a plurality of operation modes, and the input data symbols include the first sets of input data symbols for displaying on the first symbols of the OFDM and the second sets of input data symbols for displaying on the second symbols OFDM elements, wherein the data processing device contains an interleaver, during operation, reads into the storage device a predetermined number of data symbols for display on the OFDM subcarrier signals and reads data symbols for OFDM subcarriers from the storage device to perform display, and reading from the storage device is performed in a different order than reading into the storage device, the order is determined by the set of addresses, as a result of which the data symbols are interleaved by the signals of the tray cabbage; an address generator, during operation generating sets of addresses, the address being generated for each of the input symbols for displaying input data symbols in one of the subcarrier signals, the address generator comprising a linear shift register with feedback including a predetermined number of register stages and working for generating a pseudo-random bit sequence in accordance with the generator polynomial; a permutation circuit that, during operation, receives the contents of the shift register cascades and performs a permutation of the order of bits present in the register cascades, in accordance with the permutation code, to form the address of one of the OFDM subcarriers; a control module during operation in combination with an address verification circuitry that regenerates the address when the generated address exceeds the specified maximum valid address, in which one of the many operating modes represents approximately four thousand subcarriers - 20 017061 per OFDM symbol, and these approximately four thousand subcarriers represent half or less than half of the maximum number of subcarriers in the OFDM symbols in any of the operating modes, with a given maximum valid memory address and a given number of subcarriers being approximately four thousand; a linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback 9 ί ~ € ι М® Н and the permutation code forms an address of twelve bits with an additional bit, and the data processing device is capable of interleaving input characters data from both the first and second sets in accordance with the process of odd interleaving, while the process of odd interleaving contains stages in which the first sets of input characters nnyh the first part of the interleaver memory device in accordance with the following order of the first sets of input data symbols; reading the first sets of input data symbols from the first part of the interleaver memory onto the signals of the subcarriers of the first OFDM symbols in accordance with the order determined by the set of addresses; recording a second set of input data symbols in a second part of the interleaver memory in accordance with the sequence of the second sets of input data symbols; read the second sets of input data symbols from the second part of the interleaver memory according to the signals of the subcarrier of the second OFDM symbols in accordance with the order determined by the set of addresses. 46. The data processing device according to item 45, in which the permutation code generates an address K ₁ [and] of twelve bits for the ί-th data symbol from the bit present in the η-th cascade K ' ₁ [and] of the register in accordance with the code permutations defined by table Bit position K ', [n] & r n = 10 9876543210 The position of the bit K., [and] Gogh n = 7 10 581249036 47. A method for displaying input data symbols intended for transmitting orthogonal frequency division multiplexing OFDM symbols to a predetermined number of subcarrier signals, the predetermined number of subcarrier signals being determined in accordance with one of a plurality of operation modes, and the input data symbols include first sets of input symbols data to be displayed on the first OFDM symbols and second sets of input data symbols for the second OFDM symbols, the method comprising the steps of reading m to the storage device a predetermined number of data symbols for display on the OFDM subcarrier signals; reading data symbols for OFDM subcarriers from the storage device to perform display, wherein reading from the storage device is different in order from reading into the storage device, the order is determined by the set of addresses, as a result of which the data symbols are interleaved onto the subcarrier signals; generating a set of addresses, the address being generated for each of the input characters, for mapping the input data characters to one of the subcarrier signals, the generating of the set of addresses comprising the steps of using a linear shift register with feedback including a predetermined number of register stages, for generating a pseudo-random sequence of bits in accordance with the generator polynomial; use permutation schemes, which, during operation, accept the contents of the shift register stages to rearrange the order of bits present in the register stages in accordance with the permutation code to form the address; re-generate the address when the generated address exceeds the specified maximum valid address, in which one of the many modes of operation represents approximately four thousand subcarriers, approximately four thousand subcarriers represent half or less than half the maximum number of subcarriers of OFDM symbols of any of the operating modes, while the specified maximum a valid memory address and a predetermined number of subcarriers is approximately four thousand; a linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback% [-] and the permutation code generates an address of twelve bits with an additional bit; interleaving the input data symbols from both the first and second sets in accordance with the odd interleaving process, which comprises the steps of writing the first sets of input data symbols to the first part of the interleaver memory in accordance with the sequence of the first sets of input data symbols; - 21 017061 read the first character sets of input data from the first part of the interleaver memory to the subcarrier signals of the first OFDM symbols in accordance with the order determined by the set of addresses; recording a second set of input data symbols in a second part of the interleaver memory in accordance with the sequence of the second sets of input data symbols; read the second sets of input data symbols from the second part of the interleaver memory to the signals of the subcarriers of the second OFDM symbols in accordance with the order determined by the set of addresses. 48. The method according to clause 47, in which the permutation code generates an address K ₁ [and] of twelve bits for the ί-th data symbol from a bit present in the η-th cascade K ' ₁ [and] register in accordance with the permutation code, defined by table Bit position K ', [n] Gog n = 10 9876543210 The position of the bit K, [n] Gog n = 7 10 5812 4 9036 49. A data processing device, during operation, displaying data symbols received from a predetermined number of signals of subcarriers of orthogonal multiplexing symbols with frequency division of OFDM into the output data stream, a predetermined number of subcarrier signals is determined in accordance with one of a plurality of operating modes, data symbols are divided into first sets of data symbols for mapping to the first OFDM symbols and second sets of data symbols for mapping to the second OFDM symbols, wherein the data processing device holds the interleaver, during operation it reads into the storage device a predetermined number of data symbols from the OFDM subcarrier signals and reads data symbols from the storage device into the stream of output data symbols for display, the reading from the storage device being different from reading to the storage device, the order determined by a set of addresses, as a result of which the data symbols are alternately interleaved onto the OFDM subcarrier signals, the address generator, during a generating set of addresses, the address being generated for each of the received data symbols, for mapping the received data symbol from the OFDM subcarrier signal to the output symbol stream containing a linear shift register with feedback including a predetermined number of register stages and generating a pseudorandom during operation a sequence of bits in accordance with the generator polynomial; a permutation circuit that, during operation, receives the contents of the shift register cascades and performs a permutation of the order of bits present in the register cascades, in accordance with the permutation code, to form the address of one of the OFDM subcarriers; a control module, during operation in combination with an address verification circuitry, re-generating an address when the generated address exceeds a predetermined maximum valid address, in which one of the many operating modes provides OFDM symbols with approximately eight thousand subcarriers, which represent half or less than half of the maximum number of subcarriers of OFDM symbols of any of the operating modes; the preset maximum valid memory address and the preset number of subcarriers are approximately four thousand, a linear feedback shift register has eleven register stages with a generator polynomial for a linear feedback shift register i, [1 о] = A, '_ | [o] f [g] | _{and the} permutation _code generates with an additional bit an address of twelve bits, and the data processing device during operation eliminates the interleaving of the first and second sets of data symbols in the output data stream in accordance with the odd interleaving process, while the odd interleaving process comprises the steps in which the first sets of data symbols received from subcarriers of the first OFDM symbols to the first part of the interleaver memory in accordance with the order determined by the set of addresses; reading the first sets of data symbols from the first part of the interleaver memory into an output data stream in accordance with the sequence of the first sets of input data symbols; recording a second set of data symbols received from subcarriers of the second OFDM symbols in the second part of the interleaver memory in accordance with the order determined by the set of addresses; read the second sets of data symbols from the second part of the interleaver memory into the output data stream in accordance with the sequence of the second sets of input data symbols. 50. The data processing apparatus according to claim 49, wherein the permutation code generates an address K ₁ [and] of twelve bits for the ί-th data symbol from a bit present in the η-th cascade K ' ₁ [and] of the register in accordance with the code permutations defined by table - 22 017061 Bit position K ', [η] Gog η = 10 9876543210 The position of the bit K, [n] Gog n = 7 10 5 8 1 2 4 9 0 3 6 51. A method of displaying data symbols received from a predetermined number of signals of subcarriers of orthogonal multiplexing symbols of frequency division multiplexing in the output data stream, wherein a predetermined number of subcarrier signals is determined in accordance with one of a plurality of operation modes, data symbols include first sets of data symbols, received from the first OFDM symbols, and second sets of data symbols received from the second OFDM symbols, the method comprises the steps of reading a predetermined th number of data symbols from OFDM subcarrier signals; reading data symbols from the storage device into the output symbol stream for displaying, reading from the storage device is performed in a different order than reading into the storage device, the order is determined by the set of addresses, thereby eliminating the interleaving of symbols from the OFDM subcarrier signals; a set of addresses is generated, an address is generated for each of the received symbols to map the data symbol received from the OFDM subcarrier signal to the output symbol stream, the generation of the address set comprising the steps of using a linear shift register with feedback including a predetermined number register stages, for generating a pseudo-random sequence of bits in accordance with the generator polynomial; using a permutation scheme to receive the contents of the shift register cascades and permuting the order of bits present in the register cascades in accordance with the permutation order to form the address; re-generate the address when the generated address exceeds the specified maximum valid address, in which the specified maximum valid memory address and the specified number of subcarriers are approximately four thousand; a linear shift register with feedback has eleven register stages with a generator polynomial for a linear shift register with feedback M ¹⁰ 3 ⁼ ΑιΜ® ΑιΜ and the permutation code forms an address of twelve bits with an additional bit; the operating mode represents approximately four thousand subcarriers per OFDM symbol, which is half or less than half the maximum number of subcarriers in the OFDM symbols in any of the operating modes, a predetermined number of data symbols are read from the OFDM subcarrier signals into the storage device, and data symbols are read into the storage device the output stream of characters in accordance with the process of odd interleaving, the process of odd interleaving includes: recording a first set of data symbols received from subcarrier symbols of the first OFDM in the first part of the interleaver memory in accordance with the order determined by the set of addresses; reading the first set of data symbols from the first part of the interleaver memory into the output data stream in accordance with the sequence of the first sets of input data symbols; recording a second set of data symbols received from subcarriers of the second OFDM symbols in the second part of the interleaver memory in accordance with the order determined by the set of addresses; read the second sets of data symbols from the second part of the interleaver memory into the output data stream in accordance with the sequence of the second sets of input data symbols. 52. The method of claim 51, wherein the permutation code generates an address K ₁ [i] of twelve bits for the ίth data symbol from a bit present in the ηth cascade K ′ ₁ [i] of the register, in accordance with the permutation code which is determined by the table Bit position K \ [n] Gog n = Bit position K, [n] Gog n =