DK158694B - PROCEDURE AND APPARATUS FOR INPUTING AN ADDRESS SIGNAL IN A VIDEO SIGNAL - Google Patents

Description

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DK 158694B

The invention relates to a method of the kind set out in the preamble of claim 1.

A method of this kind is known in principle, cf.

5 e.g. DE Publication No. 2,052,679. However, it is a disadvantage of the known prior art method that the insertion of an address signal into a video signal cannot be performed so safely that the address signal in question can also be easily retrieved.

10 Certainly it is already generally known, cf. "Taschenbuch der Nachrichtenverarbeitung" by K. Steinbuch, Springer-Verlag, Berlin, Heidelberg, New York, 1967, page 1044, to add code groups to information for control purposes. In this context, however, there are no proposals for methods of the kind mentioned above or corresponding apparatus.

On the other hand, it is also known, cf. "Fernseh- und Kino-Technik", No. 8, 1975, pages 235-238, to use the unused time intervals in a television signal to transmit additional information. However, even in this context, there are no proposals for methods of the kind mentioned above or corresponding apparatus.

Furthermore, methods and equipment for phase adaptation of color synchronization signals ("color burst signals") are known, cf. eg. DE Publication No. 2,440,089, which takes steps to identify sub-images with even and odd numbers, as well as the color synchronization signal phase. However, it is also not known to use such measures in connection with the method mentioned above or the corresponding apparatus.

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Finally, an information processing system for color images is known, cf. DE Publication No. 2,359,824, wherein in the video signal also 5 synchronization bits are transmitted at any time. However, it is also not known to apply this principle to a method of the kind mentioned or equipment initially mentioned.

Accordingly, it is an object of the invention to provide a method of the kind mentioned in the preamble mentioned in the preamble of claim 1, by which an address signal can be inserted in a relatively simple manner in a video signal and at the same time a security of the address indication can be obtained, and this object is achieved by a method which, in accordance with the invention, also exhibits the trunk of claim 1.

This makes it possible to insert the address signal into the video signal in a very simple and secure way with the desired result with a limited circuit technical effort. Thus, the placement of the error control code designed as a cyclic redundancy check code in direct connection to the address signal time code bits makes it easier to obtain an accurate readout of the time code.

The invention also relates to an apparatus for practicing the method according to the invention. This apparatus is of the kind set forth in the preamble of claim 6, and according to the invention is peculiar to the design according to the characterizing part of claim 6.

The invention will be explained in more detail below with reference to the drawing, in which 1 is a schematic representation of a portion of a magnetic tape on which a video signal is recorded in oblique tracks and in which an address signal has been recorded according to the prior art; 3

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FIG. 2 is a schematic diagram showing an SMPTE time code signal recorded on the tape; FIG. Figure 3 shows a portion of a magnetic tape on which a video signal and an address signal are recorded by means of an apparatus according to the invention; 4A and B are diagrams showing a pattern of signals on a tape recorded by an apparatus according to the invention; Fig. 4C is a schematic diagram showing a time code signal recorded on the tape by the apparatus of the invention; 5A is a diagram of a signal pattern recorded on a tape by the apparatus of the invention; FIG. Figures 5B to 5K show waveforms for explaining the operation of the apparatus according to the invention; 6 is a block diagram of a circuit according to the invention to be used to generate time code signals and record them on a magnetic tape; FIG. 7 is a block diagram of a circuit according to the invention for reproducing the time code signals from a magnetic tape and decoding address; and FIG. Figures 8 and 9 show waveforms for explaining the operation of the circuit according to the invention.

FIG. 1 shows a method known to the past for recording an address signal on a magnetic tape T, on which an address signal is recorded in addition to a video signal.

In FIG. 1, Tv represents a plurality of video tracks on a magnetic tape T, and each of the video tracks Ty comprises a video signal for a partial image. Of course, a video signal for an entire image can also be recorded on one video track. TA denotes a track on the band T containing the audio signal. A trace Tq represents the trace containing the cue signals, and Tq represents a trace containing the control signals. In the key slot Tq is 4

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recorded an address signal. In this case, an SMPTE time code signal is used as the address signal, and two video tracks Ty, which together form an entire image, are identified by one SMPTE time code signal.

The SMPTE timecode has been approved as the US standard time and control code for video and audio tapes for television systems with 525 lines / 60 frames on April 2, 1975 and published in the SMPTE Journal, Year 84 of July 9-10, 1975.

As shown in FIG. 2, which schematically illustrates the SMPTE code signal, each address corresponds to one image and consists of 80 bits numbered from 0 to 79 and the bit frequency is selected at 2.4 kHz. Time address bits in FIG. 2 consists of 26 bits, 15 in the example indicating image # 29, second # 59, minute # 59, and hour # 23. Bit # 10 is the drop frame flag, bit numbers 11, 27, 43, 58 and 59 are unassigned address bits, and the bit numbers 4-7, 12-15, 20-23, 28-31, 36-39, 44-47, 52-55 and 60-63 are 20 user bits. The 16-bit synchronization word is arranged to determine whether the tape is fed in the right direction, such that the SMPTE time code signal is output in the direction indicated by arrow F, or whether the band is fed in the opposite direction so that the SMPTE time code signal is output 25 the direction indicated by arrow R. Thus, the time code signal can be read out correctly no matter which direction the tape is advanced. In this case, the code signal is reproduced such that its information "1" and "0" are reproduced as two-phase marking, as shown in FIG. 2nd

If, as explained above, the address signal of each image in the video signal is reproduced on the track Tq extending longitudinally of the tape T, editing of the tape can be performed very quickly and accurately.

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However, in the case of slow playback or single image playback, the speed of the tape becomes very slow or the tape is practically stopped and so the code signal in the track Tq cannot be read out.

FIG. Figures 3 to 9 show an example of the use of the invention, thereby producing an address signal which can be read out even by single image reproduction, and thus editing a tape can be effected effectively. The video signal in the 10 NTSC system is used as an example.

FIG. 3 shows a magnetic tape T on which the video signal and the address signals are recorded in an apparatus according to the invention.

According to the invention, an address signal S & a, which identifies a video signal corresponding to each TV track, is introduced into the video signal as a digital signal, the video signals being recorded on the tape as inclined track Ty as before. The address signals recorded in the video tracks TV are indicated as shaded areas in FIG. 3. The address signals are input 20 into the video signals in the odd and even sub-frames of an image and then recorded as shown in FIG. Third

According to the invention, the time code signals comprise synchronization bits which are input at a predetermined bit in each time code signal and then recorded in the video track Ty, so that by reading the clock phase at each such predetermined bit by utilizing the synchronization signal it is possible to output the code signal and the address signal. exactly, although the bit rate of the coding signal varies by the buzzer, bias or other noise factors or by variation of the line frequency in a slow reproduction mode or single image reproduction.

Furthermore, an error check code is provided in the code signal to avoid readout errors.

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As shown by the shading of FIG. 4A and 4B, which comprise a signal pattern recorded on the magnetic tape not shown in an apparatus according to the invention, an address signal is applied in a 5 line interval in the interval of the suppressed lines during the switch-off period or the vertical interval outside the part comprising a period. and a period T ^ p for equalization pulses. The address signal is input during the period following the color synchronization signals Sp, and it is desirable that the same address signals be input repeatedly in three consecutive line intervals. This address signal will then be referred to as the vertical interval time code (VITC) signal. The above-mentioned 15 suppressed line intervals correspond to the 10th to the 21st line intervals in the NTSC system.

The bit frequency fp in the VITC signal is selected as the color subcarrier frequency fsc which is equal to 3.58 MHz divided by an integer, e.g. half the frequency fsc.

20 If the line frequency is referred to as% and the sub-frame frequency fy, the following relationship exists: j. _ 455 ~ 455 x 525 _, Λ.

fsc - 2 ~ = -2- fV ................ i1 '·

Therefore, assuming the following conditions: = j ^ sc ................................., (2) , the following equation is obtained: * B »T5% ................................ (3).

The code signal arrangement of the invention will now be explained with reference to FIG. 4C. The code signal is recorded in the video track Ty, so that it is not necessary to use the synchronization word in front of the SMPTE time code signal, as shown in FIG. 2. First, two synchronization bits are placed at the top of the code signal, as shown by shaded parts in FIG. 4C. Each additional pair

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7 synchronization bits are spaced at ten bits, as shown by shaded parts in FIG. 4C. Thus bits # 0, 1, 10, 11, 20, 21, 30, 31, 40, 41, 5 50, 51, 50, 61, 70, 71, 80 and 81 are synchronization bits.

Time address bits are placed corresponding to the SMPTE time code.

Bit # 2-5 is picture only, 12-13 picture tens, 22-25 is second only, 32-34 is second tens, 42-45 are minute ones, 52-54 are minute tens, 62-65 are 10 hours singles and 72-73 are hour tens. Bit # 14 is the image dropout flag, bit # 15 is a sub-image marker, bits # 35, 55, 74, and 75 are unassigned address bits, and bits # 6-9, 16-19, 26-29, 36-39 , 46-49, 56-59, 66-69 and 76-79 are user bits.

15 By setting bit # 15 to "0" for the first and third frames or "1" for the second and fourth frames, the frame selection can indicate whether it is an even or odd frame. The total number of bits for these information bits, synchronization bits, time code bits, user bits 20, etc. is 82 bits. After these bits of information, there is an error checking code for the preceding code, e.g. cyclic redundant control code, hereinafter referred to as CRC code, consisting of 8 bits. Using CRC code, the data between bits # 0 and 81, totaling 82 bits, contains data of a predetermined code or polynomial (constant, x® + 1), and the excess residue is encoded into the last 8 bits . The last 8 bits are the CRC code. In the decoding process, all 90 bits, including the CRC code, are divided by the predetermined code which is constant and can be expressed at x ^ 30 + 1. The predetermined code used in the decoding process is the same predetermined code as used in the coding process. The excess residue acts as an indicator of failure. If there is an excess residue, the information is wrong, if not, the information is correct.

FIG. 5A illustrates an example of a time code signal 8

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represents an address. The 90-bit code signal is input in the period of 50,286 microseconds and the time Ts, e.g. 10,616 microseconds, after the leading edge of the horizontal synchronization signal at time 2.65 microseconds before the leading edge of the following horizontal synchronization signal. The code signal of FIG. 5A indicates an address of image # 29, second # 59, minute # 59, hour # 23, the same as the address in FIG. 2nd

In this case, it is sufficient that the information "1" and "0" of the VITC signal are expressed as different levels, NRZ (no return to zero) signals, as shown in FIG. 5A. Eg. the information "0" is selected as the off level and information "1" is selected 15 as 50 IRE units or a signal higher than the "0" level, and then the opposite level signals relative to the horizontal synchronization pulses are recorded from the off level.

FIG. 6 shows a circuit for generating the VITC signal and recording it on a magnetic tape.

1 FIG. 6, an input terminal 1 receives a video signal to be recorded. The video signal is applied to a fixation circuit 2 and a synchronization signal separator 3 which separates a synchronization signal from the video signal. There is a fixation pulse generator 4 which produces a fixation pulse of the synchronization signal. The video signal is transmitted from the fixation circuit 2 to an addition circuit 6 through a vertical off period form circuit 5 and to a synchronization signal separator 7. a monostable multivibrator 10. The monostable multivibrator 10 removes

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9, a compensating pulse from the signal generates a signal with the line frequency% applied to a phase comparison stage 11. The phase comparison stage 11, a variable 5 oscillator 12 and a clock generator 13 form a phase-locked loop (phase-locked loop). The clock generator 13 generates a signal with a frequency spring and clock pulses Ρχ to Ρχο shown in FIG. 5B to 5K. The signal at a frequency% generated by the clock generator 10 13 is applied to the phase comparison stage 11 to compare it with the input signal of the monostable multivibrator 10. The resulting output of the phase comparison stage is applied to the variable oscillator 12 as the starting signal thereof. Thus, the clock pulses R 1 are generated to R 1q which are synchronized with the line synchronization signal in the video signal.

The clock pulse Ρχ has the same frequency as the color subcarrier frequency fsc. The clock pulse P2 has a frequency of 1/2 fqca and a period of the clock pulse P2 is equal to a bit-20 unit in the code signal of FIG. 5A. Furthermore, the clock pulse P3 has a frequency of l / fsc. The clock generator 13 is arranged to produce the clock pulses P4 to Pg by means of a decimal counter from the clock pulse P3, and the clock pulses P7 to Ρχο by means of a hexadecimal counter. The clock pulses of the clock generator 13 and an output of the timer 9 are fed to a time code encoder 14 to form a time code, i.e. image code, second code, minute code and hour code passed to an addition circuit 15. Synchronization bits are formed by the synchronization bit generator 16 using pulses from the clock generator 13 and the user bits are formed by a user bit encoder 17. These synchronization bits and user bits are fed to the addition circuit 15. Accordingly, from the addition circuit, the code signal consisting of the time code, user bits, and synchronization bits is located on the one in FIG. 4C. Output 10

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the signal from the addition circuit 15 is then applied to a CRC code encoder 18. The FIG. Thus, the code signal shown in 4C is derived from the addition circuit 19, which is supplied to the CRC code derived from the CRC code encoder 18. The code signal is fed to a port 20.

Port-opening pulses corresponding to three consecutive line intervals in the switch-off interval are derived from the gate pulse generator 22 based on a sub-picture synchronization pulse separated by a sub-picture synchronization signal separator 21 from the output signal from the synchronization signal signal separator 7. a 15 code signal which may be introduced in the switching interval is removed by the vertical switch-off circuit 5 from the video signal by supplying the gate pulse from the gate pulse generator 22. The output signal from the shut-off circuit 5 is then applied to the additional circuit 6.

The video signal, in which the code signals are input for three consecutive line intervals within the off period, is derived from the output terminal 23. The video output signal is recorded on a magnetic tape through the recording equipment of a video tape recorder which includes an FM modulator, etc..

Furthermore, it is possible to obtain the SMPTE time code from a terminal 24 and to synchronize the SMPTE time code with the time code to be input to the video signal. The synchronization can be achieved by the timer 9 when a contact 26 is closed. The SMPTE time code is supplied through a 30 decoder 25 and switch 26.

In FIG. 7 is a block diagram of a circuit according to the invention for reproducing the video signal recorded on the magnetic tape as explained above for readout

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11 of the code signal from the video signal and for decoding the address.

In FIG. 7, an input terminal 31 receives a video signal 5 reproduced from the video signal recorded on the track Ty. The code signal is derived from an output terminal 32 as follows. First of all, the video signal is applied to a code separator 33. The code signal is separated from the video signal by a synchronization signal which is separated from the video signal by a synchronization separator 34. There is furthermore an oscillator 35 which operates at a frequency which is twice the frequency of the color carrier wave fSC / where is an integer, e.g. equal to 8.

An output of the oscillator 35 is applied to a hexa-15 counter 36. The output of the hexadecimal counter 36 having a frequency of 1/2 fsc is applied to a decimal counter 37. An output of the decimal counter 37 is applied to a hexadecimal counter 38. The clock pulses are Ρχ and P2 the same as the pulses at the recording, are obtained or derived from the counter 36, the clock pulses P3 to P5 are obtained from the counter 37, and the clock pulses P7 to Ρχο are obtained from the counter 38. These pulses are synchronized with the code signal separated from the reproduced video signal.

A monostable multivibrator 39 produces an impulse Ρχχ 25 shown in FIG. 8C, which is narrower than a line interval, but wider than the interval at which the 90-bit code signal occurs, while a flank pulse generator 40 produces a flank pulse corresponding to the rear flank of the code signal.

The output of counter 37 is applied to an opening pulse generator 41 to produce a synchronous bit opening pulse P ± 2r shown in FIG. 8B, which corresponds to the clock pulse P5 having a value "1" at the phase corresponding to synchronizing bits.

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Assuming that the code signal comprising synchronization bits "1.0", as shown in FIG. 9A, is separated from the video signal so that the flank pulse generator 40 5 produces a flank pulse corresponding to or synchronized with the trailing edge of the coding signal, as shown in FIG. 9B. This flank pulse and the synchronous bit-opening pulse P ^ 2 in FIG. 9C is applied to an AND gate 42 to derive only a flank pulse synchronized with the trailing edge of the synchronizing bit.

This edge pulse is applied to the counter 36 as an adjustment pulse through an OR gate 43 and an AND gate 44. As shown in FIG. 9D, therefore, the phase difference t between the output of counter 36 with frequency 1/2 fsc and the code signal is corrected and the output signal of counter 36 is synchronized with the code signal. In the above construction, the clock pulse period is synchronized with the rendered code, although the time base fluctuates around the normal time base at the shake or slow reproduction.

In addition, synchronization bits are introduced for every 10 bits, so that a very accurate synchronization is possible.

In the above, oscillator 35 is a fixed oscillator, but an oscillator which is phase locked to e.g. the line sync signal in the rendered video signal can further expand the range of time-synchronous signals that can be synchronized. In that case, it is possible to output the code signal, even in single image reproduction where the magnetic tape is stopped, and in fast advance, where the tape 30 is advanced at a rate several times the normal reproduction rate. Counters 37 and 38 are adjusted by the leading edge of pulse Pn, which is the output of monostable multivibrator 39, through OG gate 45.

The output pulses from counters 36, 37 and 38 are applied to one

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13 timing pulse generator 46 to generate necessary timing pulses.

The code signal separated by the code separator 33 and the output pulse of the counter 36 are applied to a series parallel converter circuit 47 which includes a switch register. to convert the code signal with the exception of synchronization bits and CRC code, i.e. the time codes and the user bits, totaling 64 bits, for parallel codes, in which each code consists of 10 bits.

These parallel codes are loaded into a buffer memory 48 with a RAM unit and also supplied with a code check circuit 49.

The code control circuit 49 decodes the time code consisting of 15 bits which are supplied from the circuit 47 by the time pulse P14 corresponding to the period of the time code signal of FIG. 8E, which is generated by the time pulse generator 46, and checks whether the decoded numbers are possible or not. There is some possibility that e.g. the hour code shows 27 hours to 20 seconds, or the second code shows 81 seconds, which is obviously wrong and caused by noise voltages.

The code check circuit 49 produces a signal "1" when the code is correct and a signal "0" when the code is incorrect. The code signal from the code signal separator 33 is applied to a 25 CRC code control circuit 50. The pulse P13 in FIG. 8D, which coincides with the phase of the CRC code generated by the timing control pulse generator 46, is applied to the CRC code control circuit 50. In the CRC code control circuit 50, the code signal along with the information code and the CRC code, for a total of 90 bits, are divided by a predetermined. constant code or polynomial, and the excess residue is checked.

If there is no excess residue, the code is correct and circuit 50 gives a signal "1". If there

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14 is an excess residual, the code is incorrect and the circuit gives a signal "0". Furthermore, synchronization bits are separated from the code signal by means of a gate circuit 5 running 51 with the synchronizing bit-opening pulse P ^ 2 in fi <J · 8B. The separated synchronization bits are fed to a control circuit 52 for these. Whether or not synchronization bits are controlled by the expected synchronization bits from the timing control pulse generator 46.

10 If correct, circuit 52 emits a signal "1" if it does not output a signal "0".

The output signals from the synchronization bit control circuit 52, the code control circuit 49, and the CRC code control circuit 50 are applied to an AND gate 53. When the output signal 15 from OG gate 53 is "1", which means that the code signal is true, a holding circuit 54 produces an impulse. P3.5, which is "1" and shown in FIG. 8G, by means of the timing control pulse from the timing control pulse generator 46. The holding circuit 54 is reset by a partial synchronization pulse 20 Typ shown in FIG. 8F, from a vertical synchronization pulse separator 55 connected to pulse separator 34. Output pulse P15 from holding circuit 54 is applied to 0G ports 44 and 45. Thus, when pulse P15 is given the value "1", the counters 36, 37 and 38 will be reset. be prevented. The pulse P15 is applied to an AND gate 56 and a memory pulse generator 57. The AND gate 56 supplies a write clock pulse to the buffer memory 48. During the period when the pulse P15 is "0", 4-bit codes from the conversion circuit 47 are continuously inserted into the buffer 30. memory 48, but if the impulse P15 is "1", entry into memory is prevented.

The pulse generator 57 produces a memory pulse Ρχβ which coincides with the leading edge of the pulse P15 / as shown in FIG. 8G. Upon supplying the memory pulse Pig to an AND gate 58, a write clock is applied 15

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pulse to a buffer memory 59 through AND gate 58. The contents of buffer memory 48 are thus transmitted to buffer memory 59. Output data consisting of time code 5 and user bits, totaling 64 bits, are output from output terminal 32 by supplying a readout address signal through terminal 60. Readout data a reproducing and / or editing apparatus is added.

As mentioned earlier, code signals are entered in three consecutive line scan intervals in the off interval. If the code signal in the first line is incorrect, the impulse P15 from the holding circuit 54 will not appear, and data will then not be transmitted from the buffer memory 48 to the buffer memory 59.

15 The code signal in the next line interval is checked in the same way. Therefore, only the correct code signal is stored in the buffer memory 59. Thus, it is not necessary to enter code signals in subsequent horizontal scan intervals. The code signal can be entered at any of the 20 intervals if it is not in the usable scan interval. Furthermore, the number of repetitions of the code signal is not limited.

Although only one of the code signals is read out correctly, the holding circuit 54 will produce the pulse P15 and the system 25 is operating satisfactorily.

In the above example, the code signal representing an address is recorded on the track T. However, at the same time, the SMPTE time code signal representing the same address recorded on the track Ty may be recorded on the track 30 Tq extending in the longitudinal direction of the magnetic tape. The SMPTE time code signal can be recorded as a two-phase signal, the same as the signal recorded in the trace Ty.

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Since an address signal indicating a video signal is recorded as a digital signal in the video signal trace, due to the design of the recorder, the digital signal corresponding to the address can be read out safely even by slow playback or single image reproduction, and thus editing the video tape performed very effectively.

Also, synchronization pulses and other pulses are not converted, but the address signal is introduced in the line interval between the line synchronization pulses in the off interval, so that no undesirable influence on the signal reproduction, such as e.g. fixing the video signal, separation of synchronization signals 15, etc., and the reproduction will in no way be disturbed.

The bit frequency fg of the input VITC signal is selected as an integer fraction of the subcarrier frequency fsc, so that the rendered video signal if the video signal with the 20 VITC signal is passed through the time base corrector is entered into the memory of the clock pulse whose frequency is a whole number of times greater than color subcarrier frequency, and then the inscribed signal is read out in memory to correct its time base. Thus, the clock references are the same in number at each bit unit in the address signal, and the state of the address code is not affected by the time base correction.

Further, synchronization bits are introduced at each predetermined bit in the code signal, readout errors can be checked by synchronization bits, and by generating pulses synchronized with synchronization bits, readout of the code can be obtained accurately, even if the bit rate in the code signal varies due to the difference in frequency or direction or variation of the line frequency in a slow or single image reproduction.

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The CRC code error check code is added to the code signal so that the readout of the code signal can be obtained more accurately.

The above examples correspond to the cases in which the video signal in the NTSC system is utilized so that the bit rate of the VTIC signal is chosen as in fsc where n is an integer. When using video signals from other systems, such as PAL systems or other types, it is necessary to select the bit rate of the VITC signal 10 based on the predetermined relationship with the line frequency so that all bits of the VITC signal can be introduced in a line interval, e.g. 455/4 ffj.

Claims (6)

A method of inserting an address signal into a video signal by 5 a) providing an address signal with a plurality of backup bits and time code bits corresponding to the video signal recorded in a track in a record carrier, and by b) selecting at least one horizontal line interval before for a vertical scan interval in each of the video signal's sub-frames or entire images, characterized by, (c) using an address signal displaying a plurality of time code bits followed by an error control code signal and being inserted into the respective selected horizontal and d) the use of a cyclic redundancy check code which is formed by dividing the address signal data by a specific code as the error control code. Method according to claim 1, characterized in that a bit rate is used for the address signal corresponding to the color subcarrier frequency frequency of the video signal divided by n, where n is an integer greater than 1. Method according to claim 2, characterized in that the bit rate of the address signal is half of the frequency 25 of the color signal color carrier. Method according to claim 1, characterized in that the address signal is continuously provided with synchronized bits in certain bit positions. Method according to claim 1, characterized in that the address signal is provided with sub-picture identification bits. DK 158694 B 19 Apparatus for performing the method according to claim 1 and having means for a) delivering an address signal having a plurality of backup bits and time code bits corresponding to the video signal recorded in a track in a record carrier, and to b) selecting at least one horizontal line interval within a vertical scan interval in each of the video signal sub-frames or whole images, characterized by means for c) generating an address signal corresponding to a video signal or whole picture including a plurality of time code bits, d) generating a cyclic redundancy check code signal formed by dividing the address signal data by a particular code; e) adding the cyclic redundancy check code signal after the address signal; line interval. island