DE8334403U1 - Semiconductor component with bump-like, metallic connection contacts and multilayer wiring - Google Patents

Description

Siemens Aktiengesellschaft Our mark

Berlin and Munich VPA 83 P 1 9 1 5 DE

Semiconductor component with bump-like, metallic connection contacts and multilayer wiring

-. The invention relates to a semiconductor component with Bump-like, metallic connection contacts and multilayer wiring according to the preamble of the claim 1.

As is known, electronic semiconductor circuitry must be used with the other parts be connected to an electrical circuit, which z. B. happens by solder or wire connections. Included However, due to the risk of damage, this connection is generally not made directly on the semiconductor component.

$ ' element (chip) of such a semiconductor circuit f | produced, but on a "connector". Such

for a connector, for example, is a contact flute

■ on the carrier of a so-called micropack construction.

This design is well known in the semiconductor industry

known. It avoids an otherwise necessary direct one

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mechanical access of the component customer to the semiconductor component of the semiconductor circuit. The necessary connection of the mentioned contact patch with a corresponding connection contact on the semiconductor component itself is still carried out by its manufacturer, at the same time in one operation for all

Contact connections of the component. This process is called automatic tape bonding. The contact connections of the

Semiconductor components are in the form of metallic bumps ι

Ke 1 EM / 01/16/1986

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executed, may consist of several materials, of which at least the top layer is solderable or thermocompressible, and are either made of gold or coated with a gold layer (contact is made via thermocompression) or exist at least on their surface from a solderable material, such as Gold, silver or copper coated with tin or a lead-tin alloy. You can see both on the edge of the semiconductor component, the so-called inactive area, or also in its active area Area.

The increasing complexity and the increasing integration density of integrated semiconductor components has to do with this led that the signal and potential guidance within these components nowadays often takes place in the so-called multi-layer technology in contrast to the earlier single-layer technology. The electrical signals and potentials used are no longer only routed in one level, but in several, each separated by electrically insulating layers, such as. B. silicon dioxide, silicon nitride, various polyimides. The connection of individual layers of the same signals or potentials is the first Line through in the area of the respective connection contact guided.

In the case of semiconductor technologies that have been customary up to now,

under a base of the

Connection contacts essentially lie in the following layers:

1. electrical conductor tracks under the entire base area;

2. Insulating layers ΐ in the form that they are under half of the base area each have a large opening within which parts of the interconnects lie;

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3. A so-called end passivation layer, likewise with a large opening, on the uppermost interconnect below the base

The base of the connection contacts is defined as a horizontal cut surface duroh a connection contact at the height at which it has the greatest horizontal extent on the end passivation layer.

The insulating layers and the end passivation are used in the manufacture of the known semiconductor component initially applied over the entire area and then in a partial area of the base area of the area to be applied later Connection contacts are etched away again so that cylindrical or cuboid contact holes are created at these points, which are partially connected to the interconnects of the multilayer wiring harness, for example consisting of aluminum, Aluminum with up to U% silicon or copper content, metal sequences such as titanium, platinum, gold and / or electrical leading suicides.

The top layer is then applied to this arrangement in the area of the base area of the connection contacts to be applied later by vapor deposition or sputtering a 0.1 to 2 µm thin metallic layer sequence as an adhesive layer .. and Diffusion barrier between the interconnect and the end pass layer on the one hand and the future metallic, hump-like connection contacts on the other hand upset. The connection contacts themselves are made over the entire surface, for example by vapor deposition or galvanic Deposition generated in connection with photo technology steps and in the case of full-surface vapor deposition in the Areas outside of the connection contacts to be manufactured are etched away again.

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So essentially lies under the connection contacts a Sohichtsequence of plastically deformable layers such. B. metallic interconnects, polyimides and brittle Layers consisting, for example, of silicon nitride »various silicon oxides. During the later contacting process the contact joint by means of thermocompression or solder bonding, there is now a great risk that in this sequence of events in the area of the interconnects and insulating layers due to the large occurring Pressures in the area below the base surface cracks and breaks, which reduce the reliability of the semiconductor component up to an electrical failure.

The object of the present invention is to provide a remedy here and a semiconductor component with hump-like, to create metallic connection contacts and multilayer wiring in which these cracks and breaks cannot occur and consequently the electrical reliability is not impaired.

In the case of a semiconductor component of the type mentioned at the outset, this object is achieved according to the invention by the characterizing features Features of claim 1 solved.

The occurrence of cracks and breaks in the area under the connection contacts during the contacting process is through The inventive arrangement of the insulating layers is reliable prevented.

Refinements of the semiconductor component according to the invention are characterized in the subclaims.

The invention is explained in more detail below with reference to the advantageous embodiments of Figures 1 to 3:

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3 shows a section from a semiconductor component according to the invention in cross section. FIGS. 1 and 2 represent the same excerpts from other developments of a semiconductor component according to the invention represent.

In the figures, the same elements are given the same reference symbols.

The semiconductor component according to the invention according to FIG. 3 contains a hump-like, metallic connection contact K with the thin adhesive layer H in the area shown and adjoining interconnects 2, 4, 6, 8 and insulating layers 3 · 5, 7 including final passivation 9, with each

1 · 5 the individual insulating layers 3 »5» .7 at least 5 ^ am

* from an imaginary vertical projection line R des

; - End of the edge of the base G of the terminal contact K on a base layer 1 away. In the production of the semiconductor component according to the invention, this

!: «Ο Base layer 1, for example an oxide layer, an interconnect 2, for example consisting of aluminum, applied over the entire surface. A first insulating layer 3 is first applied over the entire surface of this Leitb & Hn 2. This can consist of a polyimide varnish , for example, be sprayed on. In the area inside and outside the projection line R of the downwardly projected base area G of the subsequent connection contact K, this insulating layer 3 is then detached again, for example by etching, so that this insulating layer 3 is at least

30 ends 5 µm from the projection line R. Now will, again over the whole area, a second conductive path 4 applied,

* which of course with the one previously described

^ The edge of the insulating layer 3 produced by the peeling process

Level forms. An insulating layer 5 is then applied over the entire surface of this interconnect 4. Then it will be the part of the insulating layer 5 which is over the peeled off

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Area of the insulating layer 3 is detached. Then, analogously to the interconnect 4 and the insulating layer 5 alternatively, additional interconnects and insulating layers are applied, the insulating layers correspondingly partially detached again until all the required interconnects have been applied to the semiconductor component. Finally a so-called final passivation 9 is then applied, which is below the base G of the future Terminal contact K is detached again in a smaller area than that of this base area G. Thereupon As described above, the adhesive layer H and the connection contacts K are applied. Mention should be made that the number of interconnects is not limited to the four layers shown in the figures. Likewise the dimensions of the connection contacts, the interconnects and insulating layers shown in the figures are exemplary. In this way, on the one hand, all interconnects come

2, U, 6, 8 to lie under the connecting contacts K and on the other hand forming the insulating layers 3, 5, 7 are each at least 5 to outside the projection line R of the base surface G of the connection contacts K. During the subsequent contacting process is so the crevice described, adverse and Breakage in the layers below the connection contacts K reliably avoided.

The embodiments according to the invention according to FIGS. 1 and 2 are designed quite similarly, only the individual insulating layers 3, 5, 7 do not all end at the same point, viewed horizontally, but rather at different distances away from the mentioned projection line R, However does not fall below any of the insulating layers according to the invention

3, 5, 7 the minimum distance of 5 ^ m from the projection line R.

4 claims 3 figures

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Claims (4)

I «ί · ·· Ψ ■ · · a» · »• * * e · Ad« I I «· · I -7- VPA 83 P 1 9 t 5 DE npriiche 1. Semiconductor component with bump-like, metallic connection contacts and multilayer wiring, its various Conductors of each electrical signal or potential to be wired in multi-layer technology, with the exception of a sub-area under a base area of the correspondingly associated connection contacts in each case are electrically separated from one another by at least one insulating layer, said base area defining is the horizontal section through the relevant connection contact at the height at which it is the largest horizontal expansion on an underlying final passivation layer owns, characterized in that each of the individual insulating layers (3, 5, 7) outside from an imaginary, vertical projection line (R) of the edge of the base area (G) of the associated connection contact (K) ends. 2. Semiconductor component according to claim 1, characterized in that that the distance of each individual insulating layer (3, 5, 7) to the projection line (R) is at least 5 µm. 25th 3. Semiconductor component according to claim 2, characterized in that that all insulating layers (3-5, 7) are the same distance from the End projection line (R) away. 30th 4. Semiconductor component according to claim 2, characterized in that that the individual insulating layers (3, 5, 7) end at different distances from the projection line (R). 35 Il (t * t · I »# I · I · «I * I I * * t I i I