DE602007011812D1 - Integrierte schaltung zum codieren von daten - Google Patents

Integrierte schaltung zum codieren von daten

Info

Publication number
DE602007011812D1
DE602007011812D1 DE602007011812T DE602007011812T DE602007011812D1 DE 602007011812 D1 DE602007011812 D1 DE 602007011812D1 DE 602007011812 T DE602007011812 T DE 602007011812T DE 602007011812 T DE602007011812 T DE 602007011812T DE 602007011812 D1 DE602007011812 D1 DE 602007011812D1
Authority
DE
Germany
Prior art keywords
outputs
inputs
binary
configurable
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007011812T
Other languages
English (en)
Inventor
Martial Gander
Emmanuel Ardichvili
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ST Ericsson SA
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602007011812D1 publication Critical patent/DE602007011812D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H03M13/235—Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6513—Support of multiple code types, e.g. unified decoder for LDPC and turbo codes

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
DE602007011812T 2006-11-14 2007-11-12 Integrierte schaltung zum codieren von daten Active DE602007011812D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06291775 2006-11-14
PCT/IB2007/054588 WO2008059431A2 (en) 2006-11-14 2007-11-12 Integrated circuit to encode data

Publications (1)

Publication Number Publication Date
DE602007011812D1 true DE602007011812D1 (de) 2011-02-17

Family

ID=39329763

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007011812T Active DE602007011812D1 (de) 2006-11-14 2007-11-12 Integrierte schaltung zum codieren von daten

Country Status (5)

Country Link
US (1) US8312355B2 (de)
EP (1) EP2092675B1 (de)
AT (1) ATE494687T1 (de)
DE (1) DE602007011812D1 (de)
WO (1) WO2008059431A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009051012A2 (en) * 2007-10-17 2009-04-23 Nec Corporation Signal processing circuit for realizing different types of convolutional encoders, scramblers and crc generators
CN106656213B (zh) * 2016-12-22 2019-10-11 东南大学 基于k段分解的低复杂度极化码折叠硬件构架的实现方法
JP6875539B2 (ja) * 2017-09-28 2021-05-26 株式会社日立国際電気 ビームフォーミングアンテナ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970009756B1 (ko) 1994-12-23 1997-06-18 한국전자통신연구원 에러 정정 및 프레임 복구용 순환 선로 부호화 장치
JP3185727B2 (ja) * 1997-10-15 2001-07-11 日本電気株式会社 プログラマブル機能ブロック
US6807155B1 (en) * 1999-05-07 2004-10-19 Infineon Technologies Ag Method of profiling disparate communications and signal processing standards and services
IL141800A0 (en) * 1999-07-06 2002-03-10 Samsung Electronics Co Ltd Rate matching device and method for a data communication system
US6810502B2 (en) 2000-01-28 2004-10-26 Conexant Systems, Inc. Iteractive decoder employing multiple external code error checks to lower the error floor
JP3922979B2 (ja) 2002-07-10 2007-05-30 松下電器産業株式会社 伝送路符号化方法、復号化方法、及び装置

Also Published As

Publication number Publication date
US8312355B2 (en) 2012-11-13
WO2008059431A3 (en) 2008-07-10
EP2092675A2 (de) 2009-08-26
ATE494687T1 (de) 2011-01-15
EP2092675B1 (de) 2011-01-05
WO2008059431A2 (en) 2008-05-22
US20100115378A1 (en) 2010-05-06

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: ST-ERICSSON SA, PLAN-LES-OUATES, CH