DE3333894A1 - STORAGE MANAGEMENT UNIT - Google Patents

Description

PATENTANWÄLTE ZENZ & HELBER-D 4 <3O0 ESSEN 1 · AM-RUHRSTEIN 1 · TEL .: (02 01) 4126 Page - y- S- A 76

APPLE COMPUTER, INC. 10260 Bandley Drive, Cupertino, California 95014, V.St.A,

Storage management unit

The invention relates to computer memories and, more particularly, to a memory management unit (MMU).

In most computers, a central processing unit (CPU) is directly connected to both an address bus and a data bus Link. These buses or collecting lines are with a main memory or main memory systems as well as with numerous other components, such as input / output units, special processors, DMA units, etc. The main computer memory is usually the most expensive component of the computer, especially when you consider its price with the more recently available Compare microprocessors such as the 8080, 8086, 6800, and 68000. It is therefore important to use the main memory of the computer to be used with high efficiency.

According to the state of the art, memory management units (MMUs) are used to make effective use of the main memory of the computer. Such units take on organizational and administrative functions, such as remapping, etc. Often points an MMU has a memory storing a data reloading system. The higher order bits of the logical address the processor (CPU) are used to address the MMU memory. From the point of view of the CPU, for example, these bits make a Main memory segment selected. The selected CPU

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The segment number is replaced by a new number from the MMU memory, resulting in a shift between the Logic address from the CPU and the physical address used to access the main memory.

Another function performed by known MMU ■ s is to Check the addresses from the CPU to see whether they fall within the specified ranges. One stored in MMU memory Limit number is compared with low-order bits or digits of the logical address (e.g. the page offset), to ensure that the page offset falls within a given address range of the selected segment number. This prevents, for example, "data" from being accidentally read from memory locations in which it is not inserted have been.

The invention is based on these known MMUs, which a reload base and address range verification enable. As will be seen, the MMU memory is extended in one respect to the type of to store signals representing information stored in the main memory. This gives access to the main memory controlled and, for example, random writing to programs and user access to the operating systems prevented. On the other hand, the MMU memory is expanded in such a way that an overlapping memory management is created will. This enables various processes (program and data) to be executed by the computer without reprogramming of the MMU memory.

According to the invention, an improved memory management unit (MMU) is proposed for use with a computer, which has a central processor (CPU) and a main memory. The MMU has a reloading or reloading base and upon receipt of first address signals from the processor, provides second address signals for access to the memory.

7th

The MMU also has storage means for receiving and storing of signals that are stored in places in the main memory Types of information are representative. Access means are provided which allow access to these stored Enable signals when the corresponding locations in the main memory are accessed. The saved Signals from the storage means are transmitted to the main memory, for example in order to determine an access limit Types of data in main memory, e.g. B. to the operating systems. These signals can also be used to perform a read-only operation of programs and reading and writing of data.

In the preferred embodiment of the invention, the storage means are an integral part of the MMU memory. Of the MMU memory has four times the capacity that is required for this, the shifting or reloading base numbers and limit numbers to create for the entire main memory. As will be described in more detail below, this enables additional Capacity a form of "bank switching" and the execution of various processes via the computer without reprogramming of the MMU memory.

In the following the invention is explained in more detail with reference to an embodiment shown in the drawing. In the Drawing show:

Figure 1 is a general block diagram with a central processing unit or a processor (CPU), a memory management unit (MMU), a main memory and their connections in a computer;

Fig. 2 is an organizational diagram of the data stored in the memory of the MMU;

Fig. 3 is a block diagram of the MMU; and

Figure 4 is a diagram describing the various contexts used in the operation of the MMU and the resulting organization of the information stored in the computer main memory,

A memory management unit (MMU) for use is described in a digital computer that has a processor (CPU) and main memory. In the following description numerous details (e.g. special memory sizes, part numbers, etc.) are provided to aid understanding specified of the invention. It will be apparent to those skilled in the art that these details cannot be used to practice the present invention required are. In other cases, well-known circuits, etc. are not described in detail for the sake of explanation of the invention not to burden with superfluous details.

In Fig. 1, the coupling between an MMU, a processor (CPU) and a main memory is illustrated. This coupling scheme is similar in the invention to that of the prior art. The computer of FIG. 1 has a bidirectional data bus 16, which is connected to the CPU 10, the main memory 14 and the MMU 12. The address bus 18 receives address signals from the CPU 10 and transmits some of these addresses to the MMU 12 and some to the Main memory 14. Other control signals are provided as shown by lines 35 and 37 between the CPU 10 and MMU 12 are transferred. Further connections exist between the MMU 12 and the main memory 14, such as is illustrated by lines 57.

The MMU 12 is programmed from the CPU 10 via the data bus 16; addresses are transferred via the bus 18 from the CPU IO to the MMU and enable the MMU 12 to be loaded.

In the described embodiment, the CPU contains IO a 68000 processor. The CPU 10 supplies 24 bit addresses for this processor. (In fact, the lowest order bit is. The signal is not physically present as such, but is encoded in other signals; however, for the purpose of explanation assumed that this bit is also an ordinary address

bit.) It is also assumed here that the seven Most significant bits of each logical address select from the CPU a segment in memory that the next eight lower valued bits contain a page offset and that the lowest valued nine bits contain an offset (offset) include.

In the described embodiment, the segment and the page offset of each address are transferred to the MMU 12. The MMU delivers by exchanging the segment index from the CPU 10 with a number of segments stored in MMU 12 forms a reloading base. In particular, the number of segments is addressed from the CPU 10, a memory within the MMU 12, and this memory provides a segment base for addressing of main memory 14. The page offset portion of the address from CPU 10 is checked to see if the page offset falls within a predetermined area of the segment. For example, this would prevent all zeros from coming out of one unused space in the main memory can be read and interpreted as data. The segment base from the MMU becomes added together with the page offset and then transferred to the main memory 14 on the bus 18a and 18b of FIG. the nine least significant bits are passed directly from the CPU to main memory over bus 18c.

Reference is made to FIG. 3 below. With the one described In the exemplary embodiment, the MMU contains an MMU memory 20. This memory is a memory with direct access, which is made from commercially available static MOS RAM's. In a realized implementation there will be three Number 2148 RAM's used as memory 20, resulting in a total capacity of 12 k bits. The organization of the MMU memory is explained in more detail in connection with FIG.

The address from the CPU is shown in the uppermost part of Fig. 3 as a 24-bit address (logical address). 'The seven am

The highest significant bits of this address are transmitted via the bus 18a to the MMU memory and for addressing the MMU memory used. The next lower valued bits (bus 18b) are applied to an adder 27, and the the lowest significant nine bits (offset) are applied to a register 28 via the bus 18c. The output of the MMU memory consists of two 12-bit words (bus 22 and 23). These words are transmitted to a 12-bit bus 30 via a multiplexer 25. One of the 12-bit words from memory 20 forms the segment base from the stored reload base. the The second 12-bits consist of eight bits for boundary checking of the page offset and four additional bits for which the invention assigns special functions.

(In the exemplary embodiment described, there is no physically separate multiplexer 25, but the output of memory 20 is time-division multiplexed. However, for the purpose of explanation it is easier to name a specific Multiplexer 25 to be shown.)

The multiplexer 25 is also used to load information from the bus 16 into the memory 20. The signal on the line 47 comes from an access test logic 40 and creates access to the memory 20 just like the signals on a line 35. The signal on line 37 controls the multiplexing of the data between either bus 22 or the bus 23

The 12-bit bus 30 from multiplexer 25 is with the adder stage 27 coupled. This adder also receives the eight bits via bus 18b. As will be described below, the adder 27 determines when the page offset is within a predetermined range of the selected or driven segment falls. The adder 27 also combines the reloading (segment basis) from the MMU memory with the page offset to the twelve most highly valued bits of the physical ad-

resse to form. These twelve bits, along with the nine bits from bus 18c, are applied to register 28 to create one 21-bit address to which the main memory IA is transmitted. (Register 28 per se does not exist in the exemplary embodiment described, but is used for explanatory purposes shown.)

The four access check bits are provided by the multiplexer 25 the line 45 transferred to the access logic AO. Be here decodes the signals to form a main memory control signal and other control signals as follows: a bit controls the type of main memory access (1 = read-only operation, 0 = read / write operation). The second bit controls the input / output access (1 = input / output, 0 = no input / output access). The third bit controls main memory access (1 = memory access, 0 = no main memory access). The fourth bit controls the stacking or stacking (1 = stack segment - check whether there is no overflow, 0 = normal segment - check for overflow). The access check logic AO is coupled in Fig. 3 to the main memory controller via a line A7 and controls the memory access and the type of access allowed (i.e. read or read / write). The logic AO is connected to the adder 27 via overflow / carry input lines and to the memory 20 via the line A7 to enable access to the memory 20 coupled.

The particular access control bit pattern used in the described Embodiment is used is shown below.

ACCESS CONTROL BITS

Storage
MEM / Input
Output
ΙΟ / Just
reading
RO / stack
STK / Bits O 1 O O O 1 O 1 O 1 1 O O 1 1 1 1 O O 1 1 1 O O 1 1 1 1 other

Address space and access to main memory - read-only storage Main Storage - Read Only Main Storage - Read / Write Stack Main memory - read / write I / O space

Wrong page (segment does not exist) Special I / O space inadmissible (unpredictable result)

It is initially assumed that the memory 20 has been programmed from the CPU. For the first level of explanation In MMU operation, the function of the two bits on lines 35 is to be ignored. When the CPU uses the main memory addressed, the highest valued seven bits address the MMU memory 20. The twelve bits from the transfer data segment are transmitted to adder 27 via bus 22 and bus 30. There they are with the page offset (bus 18b) combined, and the resulting address is combined with the new bits of the offset in register 28 to obtain the final physical address combined. This part of the MMU works in a similar way to known MMUs. Therefore, the transhipment segment basic data programmed into memory (ignoring line 35) in a known manner.

The twelve bits forming the limit and access data become routed via bus 23 through multiplexer 25. The eight bits of the boundary data are applied to the adder 27. The four Bits of the access data are applied to the logic via line 45. The limit data are used in the described

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management example in one's complement form in memory 20 for saved a non-stacked segment. For stacked segments, the stored limit is "length minus 1" (for example a two-page segment would be stored in memory 20 as 0000 0001.) If this page offset boundary data is in the adder 27 are added, the result of this addition determines whether the page offset is in the specified range of the segment falls or not. This is an improvement over known limit tests, where additional logic steps were required.

Non-stacking example

Reference is now briefly made to FIG. 4, which shows a representation of the main memory 14 of the computer is. Assume that data is stored in locations 50. It is also assumed that the highest page offset (1111 1111) for data 50 extends to location 52 and that within this segment data extends up to a page offset from 1110 0000 (line 51). For this page offset, the one's complement of 1110 0000 (0001 1111) becomes in memory 20 of FIG. 3 is stored. When this segment is addressed and assuming that the page offset address Uli 1111 is (i.e. in the free space of the memory), adds the adder 27 1111 1111 to the stored number 0001 1111. An overflow results from the adder 27, and this overflow condition is sensed by logic 40 in FIG. In this example, an overflow indicates that the line offset is not within range and a signal is developed on line 57 to show that the address is incorrect. The logic 40 prevents access to the main memory via line 57, and / or it is generates an error signal.

Referring again to FIG. 4, assume that a

Program is stored in locations 53 and that the highest page offset (1111 1111) for program 53 to location 50 is sufficient, which lies outside the actual program ending at position 54. If the page offset for the place 54 0011 0000, then 1100 1111 is stored in memory 20 in FIG. 3 for the segment that begins at location 55. If this segment is addressed and the page offset is 0000 0001, (addressing the program) the adder adds 27 1100 1111 and 0000 0001. This time no overflow occurs and no signal is applied to logic 40, which means that access is free. Please note that with a page offset of 0100 0000 (not within of the range) and adding this number to the stored number of 1100 1111 an overflow occurs. This overflow indicates to logic 40 that the page offset is out of range and memory access is disabled.

Stack example

For some programming languages (e.g. Pascal), stacks (in memory) are very desirable. Stacks can by moving up of data, however, are time-consuming. In the system described it is allowed that stacks in the Grow down memory with a different boundary checking method.

Assume a one-sided stack segment. In the storage room 20, the limit number is stored as the one's complement of the page offset (1111 1111 -? 0000 0000) which is the same is like the size minus one (0000 0001 - »0000 0000). The access check bits ensure that the logic 40 supplies a carry-in of 1. When the page offset 1111 is 1111, an overflow occurs. This overflow is scanned by the logic 40 and found to be correct (within the Range) condition interpreted. When the page offset

1111 1110 (stack has grown too much), no overflow occurs and this is interpreted as an address out of range.

Similarly, 0000 0001 is stored in memory 20 if the stack is a two-page segment. Again the Carryover set to a one. A page offset of 1111 1110 would lead to an overflow, the one in range Address indicates, while with a page offset of 1111 1100 no overflow would occur - i.e. an address outside of it of the area would be displayed.

Figure 4 example

Reference is again made to FIG. 4, where assumed it becomes that a process (program and data) is stored in main memory 14 between locations 0 and 500 KB, The three remaining access bits in memory 20 corresponding to the segment addresses for the locations 0 - 500 KB are used, as mentioned, to create a special control. For example, for those segments that only contain a program, only reading of the memory is permitted. This of course prevents accidental writing to the program. Against it Both read and write commands can be permitted in those segments which contain data. This gives from the information to the right of program 49 and data 60 in FIG. 4.

The memory? 0 is programmed (i.e. access check bits), to prevent some segments of the main memory from being read, with the exception of certain operating modes (e.g. monitoring mode). This happens, for example, when a user is to be prevented from reading an operating system and then copied. When the program 59 is running, no access to the memory 20 is permitted, since such access is thereto could lead to the reloading base, the limit data or

the access data are changed randomly. Therefore, the four access data protect the program stored in the main memory and also limit access to certain information stored in memory. In a typical use case an operating system is loaded from a disk into main memory. As soon as it is in main memory, the CPU can run the operating system access in Uberwachungsmoden, while the user on an access and thus on a copy option the operating system is prevented.

In the invention, the memory has four times the capacity that is usually used to create a reloading base and for the limit and access data for the main memory is required. The signals from the CPU on lines 35 enable the selection or control of each quadrant of the memory 20. Each of these quadrants is shown in the following Description referred to as a context (context 0-3).

The organization of the MMU memory 20 is shown in FIG as four separate quadrants: 20a (context 0), 20b (context 1), 20c (context 2) and 2Od (context 3). Context 1,

2 and 3 are each organized in a 256 χ 12 bit arrangement (128 χ 12 bits for the reloading base and 128 χ 12 bits for the limit and access data). Context 0 is used by the CPU selected or activated during the control operation, and this context stores management data relating to the Refer to operating system. Note that any context is suitable for storing information that will encompass the entire Spanning main memory so that there are three overlapping MMU memories for user operations.

The utility of these overlapping memories is best seen in FIG. The main memory ^ is programmed with

3 processes P1, P2 and P3 shown. Process 1 is between 0 and 500 KB, process 2 between 600 KB and 1 mB, and process 3 stored between 1.2 mB and 1.5 mB. Data referring to

referring to the operating system are between 1.8 mB and 2 mB saved. A suitable reload base is stored in memory so that addresses 0-200 KB during control operations automatically select 1.8 mB to 2 mB in main memory. Appropriate limits are also loaded to ensure

that during the control operation the free space in the memory is not accessed. During the control operation (context 0) is, as shown in Fig. 4 under the heading "Context 0" full access to the MMU memory and the main memory is possible (except for access bits, which prevent writing to the operating system stored in main memory, thereby protecting the program from damage due to a program error is protected). Since the MMU memory is accessible at this time, it can be accessed via the bus 16 accordingly Representation in Fig. 3 and the previous explanation can be programmed.

Assume that context 1 is to be used for program 59 and data; a quadrant of MMU memory 20 corresponding to context 1 is programmed to indicate the location of program 59 and data 60. The limit and access bits are set as specified under context 1. Therefore, if context 1 is activated or selected, program 59 can (only) be read, and reading and writing of data 60 is permitted. No other access to other memory locations is possible, and it is also not possible to write to the MMU memory.

A second process can be stored in memory. The operating system knows the place of the first process and can program another quadrant of memory 20 for process 2. The reloading base is programmed in such a way that if the CPU addresses spaces between 0-400 KB, spaces 600 KB to 1 mB are provided for the main memory. As shown under the heading Context 2 in Figure 4, the access bits are programmed to have read and

Letter jß. the data 50 and a read-only of the program 53 eri $ ögli $ beii. E $ is also no access (for writing) to the MMU memory is permitted, nor is there any access to others Places in the main memory possible. Similarly, a third process in the main memory for context 4 can be shown as shown can be stored in FIG.

The advantage of the arrangement according to FIG. 4 is that three separate. P. £ Q £ es; s, e stored within the main memory and that each process can be easily selected through the MMU memory, i. H. by activating or selecting Context 1, 2 or 3. A separate context (context 0) is reserved as a starting point for the operating system in the exemplary embodiment described. This enables the execution three separate programs without reprogramming the MMU memory. This versatility is due to the Overlapping memory management capacity of the MMU memory has been reached.

An improved memory management unit was therefore described, which makes it possible to run a wide variety of programs without reprogramming the computer's MMU memory be allowed to expire. The improved unit also limits and prevents access to certain types of data random writing in programs.

Claims (13)

PATENTANWÄLTE ZENZ & HELBER- D "4300, .ESSEN-1 --AM RUHR3TEIN 1 · TEL .: (02 01) 412687 Page - 1 - A 76 APPLE COMPUTER, INC. Claims Memory management unit as part of a computer having a processor (CPU) and a main memory, wherein the memory management unit (MMU) is designed so that it receives first addresses from the processor and second Generated addresses for access to the main memory, characterized in that that the memory management unit (12) has: an MMU memory (20) for receiving and storing Signals representative of the types of information stored in locations (50, 53, 59, 60) of main memory (14) are, wherein the MMU memory (20) is coupled to the processor (CPU 10) such that it is at least can include part of the first address, an access device for accessing those in the MMU memory (20) stored signals if corresponding locations in the main memory (14) of the second addresses accessed, and a coupling arrangement for coupling the information representing the types of information stored in the main memory (14) Signals to main memory to limit access to certain types of information (operating systems, programs). 2. Memory management unit according to claim 1, characterized in that that the MMU memory (20) and the access device contain a memory with direct access, in Z / bu. which is also a reloading base of the storage management unit (12) can be saved. 3. Memory management unit according to claim 1 or 2, characterized in that the coupling arrangement is designed so that it enables read-only operation of other types of information (programs stored in main memory). 4. Memory management unit according to claim 3, characterized in that that the coupling arrangement is designed so that it read and write operations on again other types of information (data stored in main memory). 5. Memory management unit according to one of claims 1 to 4, characterized in that the MMU memory (20) is also provided for storing limit numbers. 6. Memory management unit according to one of claims 1 to 5, characterized in that the MMU memory (20) has several memory sections (20a, 20b, 20c, 20d - contexts 0-3), each of which is used to record the first addresses and to generate different second addresses as a function of of the selected contexts is suitable, so that the contexts result in an overlapping memory management. 7. Memory management unit as part of a processor (CPU) and a computer system containing a main memory, characterized in that the memory management unit (MMU 12) an MMU memory (20) with several memory sections (20a, 20b, 20c, 20d - contexts 0 ... 3) and a the MMU memory section selecting control means (25, 27, 40) connected to the processor (CPU 10) is, and that each of the MMU memory sections (20a, 20b, 20c, 20d) receives first addresses from the processor and others second addresses for access to the main memory (14) are generated in such a way that the MMU memory sections (20a, 20b, 20c, 20d) create an overlapping memory management so that the Memory management unit (MMU 12) a reloading base for several processes stored in the main memory without reprogramming the MMU forms. 8. memory management unit according to claim 7, characterized in that that one (20a) of the MMU memory sections can be controlled in a control mode of the processor (CPU 10) is. 9 “Storage management unit according to claim 7 or 8, characterized characterized in that in the MMU memory (20) limit numbers can be stored with which it can be determined whether certain Main memory addresses fall within a predetermined range or not. 10. Memory management unit according to claim 9, characterized in that that an adder (27) is connected to the MMU memory (20) in such a way that it takes the limit numbers from the MMU memory sections (20b, 20c, 20d) can accommodate, and that the limit numbers in a complementary binary form in the MMU memory sections for non-stacked sections are stored so that after being combined in the adder (27) an overflow or an underflow from the adder is indicative of whether the addresses are in the specified Area to fall or not. 11. Memory management unit according to claim 10, characterized in that that the limit numbers for stacked (stacked) segments in the form of the size or the length of the segment -1 are stored. 12. Memory management unit according to one of claims 7 to 11, characterized in that the MMU memory (20) Has storage means for storing signals representing the types of information stored in the main memory (14). 13. Memory management unit according to claim 12, characterized by the use of the stored signals to control access to the main memory.