DE2364408A1 - SYSTEM FOR CREATING CIRCUIT ARRANGEMENTS FROM HIGHLY INTEGRATED CHIPS - Google Patents

Description

The invention relates to a system for creating circuit arrangements of highly integrated chips, especially in HOS technology, for data processing devices, with a computing and control unit (HSE) and at least two memory chips as well as a bus connecting the chips (collective communication).

In a switching arrangement for door microprogramniiertö devices, the punctures of the device _r such. B-. arithmetic basic functions "keyboard input, Druckwerksausgabβ, tabulation, Intarpretation of user Pregranaen etc., as a result of Elenentaranweisungen running the microprogram" In represents Green & aucrüstung such a circuit arrangement are oval τ ** ß $ E present, a ROM and a RAU. The RS'E leads the j. . arithmetic, logical and iPransferoperationon for the inoculation of their memories and registers and takes over and controls the exchange of information within the entire circuit. These operations can be used, for example, to display any arithmetic operations, output or receive data and control signals to other modules or peripheral units, make logical decisions and read data from and into additional memories.

The RAM is required in order to store data to be processed, intermediate values, etc. and for further processing. draw. All arithmetic operations are carried out between the V RAM and a calculation register of the ftSE .

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Finally, Ia UCn contains the microprogram that. through continuous addressing of the memory locations in constant readiness chart "is, conit quasi in a rest- ■ loop circles and "if there is an input - e. B. ·. from a keyboard - branches at the appropriate point whereupon according to the output from the ROM received "Mikroprogranaes the processing of the input err · follows. .. «... '

Simple devices for data processing, such as, for example, less demanding desktop computers, get by with an EOM for a set of microinstructions, as can be implemented on a chip with an economically justifiable expense that two or more chips are required. In known geworde- ■: ien circuit arrangements of this kind is' provided in the RSE a (z * B ₀ by £ ählimpulse steadily continued scarf tb are s) Address Register ·, which via the bus, the individual memory locations of ^RCl-I:. S stefiq able to call. If a processing (for example that of an arithmetic task) is to be carried out, then the RSE will set the address register with the ent -'-: ·· .ρχeehen. Microprogram address carried out a jump to the associated ßtello the microprogram, and the reading of the individual Prograauaechritte begins "This srfolgt following ■ ', the branch address the sfetige" port circuit of the address ^ ^e;:.: Gisterß, is transporting a each address via the bus and the chip-internal control of the associated memory location ia the ROM chips ·. ·.,.-... \.. _: -

However, the time required for this solution is very high - and * V. Is particularly important in the case of MOS technology, with '^; λ '. the signal flow, compared to the bipolar technology, very ^{slow - 1} V sam let - the calibration for each individual addressing of the micro «Τ.Γ; program steps from the. Part-time "address transport

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The invention is based on the object "in circuit arrangements of the type described above, depending on the application two or more chips provided with a ROM, which have a related microprogram content, with a to work together, whereby the time requirement should be short and addressing should be easy.

The solution to the problem is that in each chip (5, 4, 5) containing a memory there is an address register (6, 7, 8), which can be incremented by counting pulses, for addressing all memory locations, the additional positions for the selection of further , Memory containing chips (3,4,5).

The advantage of the invention is in particular that the memory contents of two or more chips are treated as if they were all contained in one chip Addressing counting pulses incrementable address register in the memory locations of the respective chip separately and in parallel for each chip ROM's. In the additional places, however, it is indicated which of the chips is currently being used to read out the memory content comes into consideration. Since these additional digits are also incremented by the counting pulses, after reaching the end address of the first chip automatically the first memory location of the next chip addressed. If a request is made by the BSE to read out the content of a specific memory location, all ROM chips are addressed via the bus; only the ROM chip, which is activated by the content of the additional Register locations is addressed. Only the memory space addressed in this chip is read out. The address registers of all chips continuously counted. If the ROH of the chip is read out to the end, and program steps from the next one follow Chip on, the further addressing there takes place simply by increasing the address continuously without any loss of time.

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INSPECTED

The time required is kept very low because only the chip-internal time is required for each addressing of a memory location is needed ^. and there is no transport by bus. The required Circuitry is limited to one address register per ROM chip, which is generated by a counting pulse (e.g. the one in such a circuit usually present clock) can be continuously incremented and a few additional digits (normally one or two digits) for the selection of the ROM chips. As a further advantage -

part results from this solution that each ROM chip in the structure is completely the same, regardless of the (of course, limited by the scope of the register) used in a circuit arrangement Number. A system constructed in this way is therefore extremely flexible and can be used to implement a wide variety of circuit arrangements Use cases suitable.

Another advantage arises when the system uses sub-program technology and in each ROM chip, in addition to the one address register, further address registers for receiving return addresses available. In this pail it is particularly important that a large contiguous address book is available, which has several Chips is enough. With the subroutine technique it is very important that a subroutine at a certain point in the memory area can be jumped to from all memory addresses.

Embodiments of the invention are shown in the drawings and are explained in more detail below. Show it

1 shows a first embodiment and FIG. 2 shows a second embodiment.

In Figure 1, five chips 1 to 5 are symbolically shown, of which one chip 1 a computing and control unit (RSE), a second chip 2 a read / write memory (RAM) and three chips 5, 4, 5 read-only -Memories (ROM's) included. Each ROM chip 3, 4, 5 has a storage capacity of 1,024 microinstruction words, so that the microinstruction set stored therein has a total of 3,072 values. Each ROM chip 3, 4, 5 also contains an address register 6, 7 »8 _; the ten places indicated by crosses for addressing the 1,024 words of the associated memory area of the chip 3i 4 ·, 5.

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as well as two additional digits that are provided for selecting the ■ j 3 ^ / ^ 5. Each of these three address registers 6, 7 * 8; can be continuously incremented by a counting pulse - indicated by the arrows 9, 10, 11 at the right end of the registers 6, 7, 8. A data bus 12, an address bus 13 and a control bus 14, each with several lines, extend from the RSE chip 1 have and are connected to the chips 2, 3, 4, 5 of the circuit arrangement. The address registers 6, 7, 8 can also be set by addresses transported by the RSE chip 1 via the data bus 12 and address bus 13.

A keyboard 15 is provided for the input of data to be processed provided, which is connected via a peripheral channel 16 to the circuit arrangement and to this in. Not shown in detail Cooperates in a way. Likewise, a printing unit 17 is connected to the circuit arrangement via a peripheral channel 18 for data output and allows the output of final results, intermediate values, entered data and, depending on the task of the device and accordingly Design of the periphery and the microprogram, the output of alpha texts.

When starting the device, among other things, all address registers the ROM chips 3 »4, 5 are set to Hull. The address registers 9> Counting pulses supplied to 10, 11 have the effect that the addresses are continuously incremented so. that parallel in each ROM chip 3, 4, 5 Storage space is addressed after the other. Should be due to a Input via the keyboard 15 processing can be carried out, so we get the corresponding 12-digit address from RSE Chip 1 via data bus 12 and address bus 13 in the address registers 6, 7, 8 of all three ROM chips 3, 4, 5 transported, a decoding device not shown in detail now assigns the first ten bits of the address to a memory location and uses the remaining two bits to select one of the three chips. At the instigation of a coming from the RSE chip 1 via the control bus 14 Control command, the content of this memory location is read out and switched to the data bus 12 in the selected chip. Of this The address registers are now based on the written address 6, 7 »8 in all three ROM chips 3, 4, 5 continuously by counting pulses

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ORlGiNAL INSPECTED

switched, and in the chip affected by the start address, for example the ROM chip 3i , the following microprogram steps required for processing are continuously read out. As soon as the content of the last memory location in the ROM chip 3, which can be addressed by the ten-digit address, has been read out, the two-digit address section is incremented by the next counting pulse in all three address registers 6, 7 »8. The ten-digit address part receives the initial value so that the first memory location is automatically read from the ROM chip now addressed by the two-digit address part. The same process can possibly also take place during the transition to the third ROM chip 5.

If the processing required by the keyboard input has been carried out, for example terminated by an output of the printing unit 17, a "circling" of the microprogram is now in a "rest loop" causes.

The circuits contained in RSE chip 1 and RAM chip 2 and from these functions to be carried out do not belong to the invention and are therefore not explained in more detail for the sake of clarity. Your basic tasks are already in the introduction to the description It should be noted, however, "that both the peripheral channel 16 and the peripheral channel 18 only work with the RSE chip, regardless of which one Chip they are physically related. The signal exchange, for example, of the peripheral channel 18 with the RSE-Chpp 1 takes place thus via an "internal wiring" contained in the RAM chip 2 «it Bus.

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In Figure 2, the ROM chip shown in Figure 1 is 3, 4-, 5 modified to the effect that three address registers 31, 32, 33 are provided instead of a single address register 6, 7 »8 are. Further address registers of type 32, 33 can also be added. The address register 31 is continuously countable and can be set in the same way as registers 6, 7 »8 (Fig. 1). In the case of a special jump command, a so-called subprogram jump, the content from register 32 to register 33 and from register

31 taken over after register 32 and register 3I set again. This saves the address for the return (return address) in the ¹ program part run through before the subprogram jump.

The return to the one run through before the subprogram jump The program takes place by taking over the contents of the register

32 to register 3I and from register 33 to register 32. Register 33 and possibly the following are used in a first subprogram jump to nest further subprogram jumps.

Although in the description of read-only memories (ROMs) is mentioned, it is of course also possible to use read / write memories (RAMs) instead.

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Claims (4)

Patent claims 'Λ J) System for creating circuit arrangements from highly integrated chips, especially in MOS technology, for data processing devices, with a computing and control unit (RSE) and
at least two memory chips and a bus connecting the chips (collecting line), ■ characterized in that in each chip (3, 4, 5) containing a memory, an address register (6, 7, 8) which can be incremented by counting pulses is arranged for addressing all memory locations, the additional places for
Selection of further, memory containing chips 0,4-, 5). 2.) System according to claim 1, characterized in that all positions of the address registers (6,7 »8) in the memory containing chips (.3,4,5) can be set by addresses coming from outside. , 3. System according to one of claims 1 or 2, characterized
characterized in that the memory chips are read-only memories (ROMs) and that sequentially callable microprogram instructions are stored in them. 4. System according to one of claims 1, 2 or 3 »thereby
identified that further address registers
(32, 33) are provided for receiving return addresses in chips containing microprograms. 509827/0399 Lee rseι te