DE3218992C2 - - Google Patents

Description

The invention relates to a monolithically integrated Circuit with subcircuits integrated on a chip, where the linkage of at least two Subcircuits after the subcircuits have been manufactured is changeable.

In the manufacture of monolithically integrated Circuits is with fixed manufacturing technology the electrical behavior of the circuits by the Structures of the photo masks clearly defined.

The function of the circuit is only limited afterwards to influence. Such a change in Function is desirable for several reasons, so z. B. to improve functionality (for example for comparison), to improve the yield (use of redundancy circuits) and to reduce the Variety of types.

As integrated circuits, the possibility of different Offer connection of subcircuits, the so-called gate arrays are known in which Sub-circuits having predetermined gate structures by changing the metallic connecting them Conductor tracks linked together as required by the customer can be. However, this link must at the semiconductor manufacturer and can not from Customers are carried out themselves.  

It is also known for programming a PROM (Programmable Read Only Memory) and to replace defective ones Memory parts in dynamic RAM’s (Random Access Memory), d. H. to replace a faulty address through a redundant address, the melting of Use fusible links. The application of appropriate Fusible links is e.g. B. from W. Söll u. J.-H. Kirchner, Digital memory, Vogel publishing house, Würzburg, 1978, Pages 156 to 159. Fusible links in MOS However, circuits require additional circuits and additional arrangements like drivers, guard rings, windows in the passivation layer and power supply lines are chip-intensive and also have a reliability risk because, for example, the one with evaporation of metal associated with melting away can have adverse effects and such memory cannot be fully tested by the manufacturer.

A subsequent function influencing an integrated Circuit is also through the software Definition of a microprocessor that acts as a program memory an EPROM (Erasable PROM) - or EEPROM (Electrically Erasable PROM) technology executed memory has, by description of its program memory possible. However, they are disadvantageous in many applications the lower processing speed compared to hardware wiring and those high for small systems Processor costs.

The object of the present invention is to remedy this to create and a monolithically integrated Provide circuit whose electrical function too defined in terms of hardware after product completion and can be permanently influenced.  

This task is done with an integrated circuit of the type mentioned in the invention solved in that at least one EEPROM cell is provided depending on their programming status different subcircuits using a Circuit arrangement are linked together. On this way it succeeds monolithically integrated Execute circuits so that their electrical function about the hardware even after completion of the product can still be changed because the This changes the hardware properties is that individual subcircuits of the integrated Circuits by using EEPROM cells in the Are linked together by deletion or writing the EEPROM's subsequently subcircuits be switched on or off. This change can for example during testing and corresponds to a hardware programming of Circuit properties or functions.

EEPROM cells in the sense of the invention include all Understand memory cells that are electrically programmable and are electrically erasable.

As EEPROM memory cells with the integrated Circuit are linked in such a way that their programming state the operation of the circuit remains changed, z. B. EEPROM cells from floating gate Type as used in Electronics, February 28, 1980, pages 113 to 117, are known. The data retention of corresponding memory cells is at 10 or 100 years longer than the expected Product life of the integrated circuit, see above that a corresponding technique for realizing the invention Circuits is particularly suitable.  

With the help of the EEPROM cells can afterwards all alone on a chip circuit parts, d. H. after making the integrated Circuit, be switched on or off. The invention Execution of a circuit is special easy if the integrated circuit as part of their Function anyway requires an EEPROM memory and additional process steps are not required. On the other hand, they are also more standard MOS technology at EEPROM’s necessary additional process steps economical in many applications justifiable.

Integrated circuits can then be produced, which for example when testing by programming the EEPROM cells to special customer requests or customer specifications be adjusted, for example for inversion of signal levels or for coding, such as. B. by Programming of addresses.

In the general case are implemented on the chip Subcircuits through free programming of the EEPROM Cells linked to each other in the desired way, where in contrast to gate arrays, the desired link can be carried out by the customer himself.

The EEPROM cells used according to the invention can finally used to compare analog functions will. The comparison itself is digital on the one hand, e.g. B. on the connection of resistors, and on the other hand analog, e.g. B. on the controlled shift the threshold voltage in an EEPROM cell. The controlled shift of the threshold voltage from EEPROM memory cells by means of time control is in the DE-OS 28 28 855 described.  

It is within the scope of the invention that as subcircuits a memory field and at least one redundant, in the number of memory cells a subrange of Memory array corresponding memory cell arrangement is provided, and that one designed as an EEPROM memory Error address memory is provided depending from its programming state the memory access from the memory field to the redundant memory cell arrangement is switchable.

A corresponding circuit is advantageous so designed that a controllable via a decoder Memory field is provided that a as EEPROM executed error address memory is provided in which is the address of an addressable memory area the memory field can be stored in that an address register in which the current memory address is cacheable and that with the decoder and the error address memory is connected, is provided, that a redundant memory cell arrangement is provided whose number of memory cells is addressable per se Corresponds to the memory area of the memory field, that a comparator is provided, the first input with the address register and its second input is connected to the error address memory and its Output with the redundant memory cell arrangement is connected and that a locking device is provided by means of which depending on the output signal access to the memory field can be blocked by the comparator is.

The invention is described below with reference to the figures explained in more detail.

It shows

Fig. 1 is a circuit diagram of a circuit arrangement which connects, depending on the programmed state of an EEPROM cell has two sub-circuits, alternatively, with a third sub-circuit,

Fig. 2 is a block diagram of an embodiment for re-decoding defective memory areas in EEPROM's to redundant memory cells and

Fig. 3 is a circuit diagram of an arrangement according to FIG. 2.

In the figures, the same elements have the same reference symbols designated.

Fig. 1 shows the diagram of a circuit arrangement which alternatively connects depending on the programmed state of an EEPROM cell has two sub-circuits T 2 and T 3 with a third circuit section T 1, wherein the EEPROM cell with its peripheral circuits for reasons of clarity not shown is. The sub-circuit T 2 is connected to the third sub-circuit T 1 via a transfer gate 2 , while the sub-circuit T 3 is connected to the third sub-circuit T 1 via a transfer gate 4 . The programmed state of the EEPROM cell, ie either a "1" or a "0", is at point 1 and thus on the one hand directly at the control gate of the transfer gate 2 and on the other hand inverted at the control gate of the transfer gate 4 via the inverter 3 . Thus, in the presence of a "1" at point 1, the transfer gate 2 is switched through and thus the subcircuit T 2 is switched through and thus the subcircuit T 2 is connected to the subcircuit T 1 while the transfer gate 4 is blocking. In contrast, if there is a "0" at point 1 , the transfer gate 2 is blocked and the transfer gate 4 controlled via the inverter 3 is open, so that the subcircuit T 3 is connected to the subcircuit T 1 . With a corresponding simple circuit arrangement, different subcircuits can thus be connected to one another by programming an EEPROM.

FIG. 2 shows a block diagram of an exemplary embodiment for redecoding a defective memory area of the memory S to redundant memory cells E. The active memory field of the z. B executed in EEPROM technology S is z. B. addressable by word, whereby n address bits are required for 2 ⁿ memory addresses (e.g. n = 11 for a 16 kbit memory with 8 bits per word). A memory word with at least one defective memory cell in the memory S should now be replaceable by a redundant memory word stored in the spare memory E , ie only one redundant memory cell E is provided in the exemplary embodiment shown. For this purpose, the arrangement according to FIG. 2 has an address register A in which the current memory address required for addressing the memory S can be buffered.

The address register A is connected to the row decoder D of the memory S. Other peripheral circuits belonging to the memory field S, such as column decoders, input and output circuits etc., are not shown in FIG. 2 for reasons of clarity and, like the row decoder (word decoder) D, can be carried out in a manner known per se (compare, for example, BW Söll and J . -H. Kirchner, Digitale Speicher, Vogel-Verlag-Würzburg, 1978, pages 128 to 131 and pages 152, 153). The line decoder D working as a 1 out of 2 ⁿ decoder can, for. B. from A. Reiss, H. Liedl, W. Spichall, Integrated Digital Modules, Siemens AG, Berlin-Munich, 1970, page 235, 236, can be designed as a NOR decoder.

To store the address information of the defective memory word of the memory S determined during the testing of the memory field S is a error address memory F which has EEPROM cells and is connected to a control circuit 5 which works in a manner known per se and with the programming _voltage U _pp for programming the EEPROM cells is connected, provided.

The contents of the address register A can be fed to the fault address memory F via the line 6 and to the first input of a comparator K via the line 7 . The second input of the comparator K is applied via the line 8 coming from the fault address memory F. The output signal KA of the comparator K , which works as a commercial comparator in such a way that it outputs a "1" on the output side as the output signal KA when its signals applied to the inputs coincide, acts on the one hand on the spare memory E and on the other hand a blocking device Sp . The blocking device Sp acts on the row decoder D or the memory field S in such a way that it blocks access to the memory field S as a function of the output signal KA of the comparator K.

. The circuit of Figure 2 operates as follows: Each standing in the address register A address information is compared in the comparator K with the number stored in Fehleradreßspeicher F during testing of the memory array S address of the defective memory area of the memory S. If the comparator K detects the faulty memory line in the case of address data equality, the output signal KA of the comparator K (KA = "1") is used to select both the replacement line which replaces the faulty memory area of the memory S , that is to say the replacement memory E , and the regular one Storage field S locked via the locking device Sp .

The circuit diagram of the present invention, the block diagram of Fig. 2 according to operating arrangement is shown in Fig. 3. The memory array S is designed for 2 ⁿ addresses, the row decoder D designed as 1- 2 ⁿ -NOR decoder. The address register A has n memory cells, where only the memory cell 9 for the first bit A 1 and the memory cell 10 are shown for the n th bit, for reasons of clarity.

The comparator K is designed in such a way that for one bit, e.g. B. the first bit A 1 of the address register A , an AND gate 15 and two NOR gates 13 and 14 are provided. The address bit A 1 acts on one input of the AND gate 15 and one of the NOR gate 13 , while the line 8 coming from the fault address memory F acts on the second input of the gate 15 and the gate 13 . The outputs of the gates 13 and 15 act on the NOR gate 14 , the output of which has an input of the multiple NOR gate 16 at the output of which the signal KA can be obtained. The other comparator cells are designed accordingly; in FIG. 3 only the nth comparator cell is shown for reasons of clarity.

The blocking device Sp consists of two OR gates 11 and 12 , one input of the gates 11 and 12 each being acted upon by the output signal KA of the comparator K. Address bit A 1 can be applied to the second input of gate 11 , while the complementary address bit can be applied to the second input of gate 12 . The row decoder D is then applied to the input side instead of the address bit A 1 from the output of the gate 11 signal A 1 ' and instead of the complementary address bit from the output of the gate 12 signal A 1'' applied. The further memory cells of the address register A are, as shown in the memory cell 10 , connected to the row decoder D via the bits An and leading lines.

The non-volatile, electrically reprogrammable error address memory F has n + 1 memory cells E 1 to E _{n + 1} and the associated control circuits. The error address memory F is advantageously designed as an EEPROM memory of the n- channel silicon gate type with a floating gate and tunnel programming, as described, for example, in the magazine Electonics, February 28, 1980, pages 113 to 117. In the first n EEPROM cells E 1 to En , the address information of the faulty memory word determined during testing can be stored. For reasons of clarity, only the first cell E 1 and the nth cell En are shown. Each address information in the address register A is compared in the comparator K with the error address stored in the error address memory F. If the comparator detects the faulty memory line in the case of address data equality, the output memory KA of the comparator K (KA = "1") is used to select the spare memory E in which the faulty memory line is stored. Furthermore, both input lines A 1 ' and A 1''of the row decoder D are switched to "1" via the signal KA , for example as shown in FIG. 3, for the address bit A 1 . Since all row lines have a "0", the row selection in the decoder D designed as a NOR decoder is prevented in this way and the memory field S is thus blocked, so that the data are read from the spare memory E and not from the defective memory row of the memory S. .

The erasing of an EEPROM floating gate cell (e.g. E 1 ) is carried out in a known manner, e.g. B. in the above-mentioned literature "Electronics", achieved by tunneling electrons from the substrate into the floating memory gate 20 . Due to the negatively charged floating gate 20 , the memory transistor E 1 is blocked during reading, a "1" appears at the output 22 .

At the beginning of the decoding, the error address memory is deleted into a defined "1" starting state. The erasing process is carried out simultaneously for all n + 1 EEPROM cells E 1 to E _{n + 1} . The tunnel window of the cells is on the side of the drain electrode 22 of the memory transistor. The potential difference between the control gate 21 and the drain electrode 22 of the memory transistor is decisive for reprogramming, erasing and writing. When erased, the common gate line 24 of all memory cells via the transistor T 0 is at the programming voltage U _pp , for. B. to about 20 V. With this voltage, all memory transistors E 1 to E _{n + 1 are} conductive and take the transistors T ₁₁ to T _{n + 1} acting as load elements, which are connected via transistor T 6 to the supply voltage V _DD are flowing current. Since the source electrodes 23 are connected to ground, the drain electrode 22 of the memory cells is at 0 V and the voltage difference on both sides of the tunnel window required for erasing is given.

To write the memory cells E 1 to E _{n + 1} into the “0” state, electrons tunnel (back) into the substrate from the floating gate 20 . The memory cells change due to the positive charge on the floating gate 20 in the direction of the conductive state. During writing, the gate line 24 of all cells is at the voltage OV via the transistors T 8 and T 9 and the memory cells are securely blocked due to the previous erasure. Since the transistors T 21 to T 2 n conduct only during writing, the voltage at the drain electrode 22 of the memory transistors depends on the information A 1 to An in the address register A. If an address bit is in the "0" state, the associated transistor T 31 to T 3 n is blocked. The drain electrode 22 of the memory transistors floats through the transistors T ₁₁ to T _{1 n + 1} and the transistor T 4 to about 20 V. The voltage difference through the tunnel window is given and the writing process of the cell to the "0" state takes place. However, if the address information present on the bit lines A 1 to An is "1", z. B. in the case of bit A 1 via transistor T 31 and transistor T 21, the drain electrode 22 of the memory cell E 1 is connected to a low voltage. A write voltage is not effective, the line remains erased in the "1" state.

After writing, there is therefore a logical correspondence between the information in the address register A and the information in the error address memory F , ie the address of the memory word S found during testing as incorrect is stored in the error address memory F. Whenever this address is present during the later use of the memory, the re-decoding is carried out via the comparator K and not the faulty memory line of the memory field S , but in particular the information stored in the spare memory E is read out.

The error address memory F operates in three operating states: delete, write and read out, whereby delete and write are only carried out once. At least two bits of control information are therefore required for control. In order to avoid undesired incorrect programming of the fault address memory F , for example when the EEPROM memory is switched on, the programming voltage U _pp of approximately 20 V is itself advantageously used as control information which may only be in the "high" state when deleting or writing, but when reading out Must be "0". The high voltage is applied to the memory cells E 1 to E _{n + 1} via the transistor T 0 and T 4 , the enhancement transistors T 5 and T 6 are blocked. For U _pp = 0, however, the enhancer transistors T 0 and T 4 are blocked during the readout. The readout voltage of approximately 5 V at the gate 21 of the memory cells is supplied via the transistor T 5 , the drain current, however, via the transistor T 6 from the 5 volt operating voltage source V _DD .

The second control information S / (write / delete) decides whether to delete (S / = "0") or to write (S / = "1") and has no influence during the readout.

If the recoding of the defective memory address is carried out during the slice measurement, ie at a point in time at which the individual chips on which an arrangement according to FIG. 3 is integrated have not yet been separated from the slice assembly, the programming _voltage U _{pp is} expediently exceeded its own connection pad (pad) P which is not contacted (bonded) during the later chip assembly. Subsequent incorrect programming is therefore excluded. The voltage U _pp then always remains at 0 V via the depletion transistor T 7. Since the state of the line S / for U _pp is 0 V without influence, this line can operate without risk of malfunction with the control of the active EEPROM operation (Storage field S) .

The surplus memory cell E _{n + 1 of} the fault address memory F , the drain electrode of which also acts on an input of the multiple NOR gate 16 of the comparator K , serves to block the output of the comparator K when the redundant memory word of the spare memory E is not used (no faulty Memory line in memory field S) . The erasing of the error memory F in the "1" state takes place right at the start of the slice measurement and the comparator K is locked, it remains locked if a write operation does not take place because the regular memory field S is free from errors.

The control device for the fault address memory F does not have to be integrated with the memory field S and the fault address memory F on a chip; it can also be provided externally and used for control purposes in the disk measurement.

Claims (3)

1. Monolithically integrated circuit with subcircuits integrated on a chip, in which the linkage of at least two subcircuits can be changed after the subcircuits have been produced, characterized in that at least one EEPROM cell (E 1 ) is provided, depending on its programming state, different subcircuits ( T 2 , T 3 ) are linked to one another by means of a circuit arrangement ( 2, 3, 4 ). 2. Circuit according to claim 1, characterized in that as subcircuits (T 1 , T 2 , T 3 ) a memory field (S) and at least one redundant memory cell arrangement (E) corresponding to a number of memory cells (S) in the number of memory cells is provided, and that an error address memory (F) designed as an EEPROM memory is provided, depending on its programming state, the memory access is switched from the memory field (S) to the redundant memory cell arrangement (E) . 3. A circuit according to claim 1 or 2, characterized in that a controllable via a decoder (D) memory field (S) is provided, that an error address memory (F) designed as an EEPROM is provided, in which the address of an addressable memory area of the Storage field (S) can be stored,
That an address register (A) , in which the current memory address can be buffered and which is connected to the decoder (D) and the error address memory (F) , is provided,
that a redundant memory cell arrangement (E) is provided, the number of memory cells of which corresponds to an addressable memory area of the memory field (S) ,
that a comparator (K) is provided, the first input of which is connected to the address register (A) and the second input of which is connected to the fault address memory (F) and whose output (KA) is connected to the redundant memory cell arrangement (E) and
that a blocking device (Sp) is provided, by means of which access to the memory field (S) is blocked as a function of the output signal (KA) of the comparator (K) .