DE3218992A1 - Monolithically integrated circuit - Google Patents

Abstract

The invention relates to a monolithically integrated circuit with subcircuits integrated on a chip. In the circuit, the linking at least of two subcircuits can be altered after the subcircuits are fabricated in such a way that at least one EEPROM cell (E1) is provided. Depending on the programming state of the latter, various subcircuits (T2, T3) can be interlinked by means of a circuit arrangement (2, 3, 4). <IMAGE>

Description

Monolithic Integrated Circuit The invention relates to a monolithic integrated circuit with subcircuits integrated on a chip, in which the linking of at least two subcircuits after the subcircuits have been produced is changeable.

In the manufacture of monolithic integrated circuits is with fixed manufacturing technology, the electrical behavior of the circuits the structures of the photomasks clearly defined.

The function of the circuit can only be influenced to a limited extent afterwards. However, such a change in function is desirable for various reasons, e.g. to improve functionality (e.g. for comparison), to improve yield (Use of redundancy circuits) and to reduce the variety of types.

As an integrated circuit that makes the most of different Linking sub-circuits are known as gate arrays, in which subcircuits having predetermined gate structures by changes of the metallic conductor tracks connecting them, depending on the customer's wishes we can be linked. However, this link must be made by the semiconductor manufacturer and cannot be carried out by the customer himself.

Nte 1 vi / 13.05.1982 It is also known for programming a PROM (Programmable Read Only Memory) and to replace defective memory parts in dynamic RAM's (Random Access Memory), i.e. to replace a faulty one Address through a redundant address to use the melting of fusible links. The use of corresponding fusible links is e.g. from W.Söll and J. -H. Kirchner, Digital memory, Vogel-Verlag, Würzburg, 1978, pages 156 to 159, known. Fusible However, links in MOS circuits require additional circuits and additional arrangements such as drivers, protective rings, windows in the passivation layer and power supply lines, which are chip area-consuming and also have a reliability risk, because, for example, the evaporation of metal associated with melting away is disadvantageous Can have an impact and such memory at the manufacturer is not complete are verifiable.

Subsequent influencing of the function of an integrated circuit is also through the software definition of a microprocessor, which acts as a program memory an EPROM (Erasable PROM) or EEPROM (Electrically Erasable PROM) technology Has memory, possible by describing its program memory. Disadvantageous In many applications, however, the processing speed is lower than that of hardware wiring and the high cost of a processor for small systems.

The object of the present invention is to provide a remedy here and to provide a monolithic integrated circuit whose electrical function Even after the product has been completed, it is still defined in terms of hardware and permanently influenced can be.

In the case of an integrated circuit, this task is described in the introduction mentioned type solved according to the invention in that at least one ESPROM cell is provided is different subcircuits depending on their programming status can be linked to one another by means of a circuit arrangement. In this way succeeds in designing monolithically integrated circuits so that their electrical Function via the hardware remains even after the product has been completed is changeable, since the change in the hardware properties is achieved thereby is that individual subcircuits of the integrated circuits by using of EEPROM cells are linked together in such a way that by deletion or Writing of the EEPROM's can be switched on or off afterwards. This reduction can for example be carried out during testing and corresponds hardware programming of circuit properties and functions.

EEPROM cells in the sense of the invention are all memory cells understood that are electrically programmable and electrically erasable.

As SEPROM memory cells that are integrated with the integrated circuit in the Are linked in a way that their programming state determines the Arboitsweise of the circuit permanently changed, e.g. EEPROM cells of the floating gate type can be used, as known from Electronics, February 28, 1980, pages 113-117.

The data retention of corresponding memory cells is with 1O or 100 Years longer than the expected product life of the integrated circuit, So there is a corresponding technique: especially for realizing circuits according to the invention suitable is.

With the help of the EEPROM cells, according to the invention, very generally on a chip circuit parts subsequently, i.e. after the production of the integrated Switching, switched on or off. The inventive implementation of a Circuitry is particularly simple when the integrated circuit is in the context of its Function anyway requires an EEPROM memory and no additional process steps required are.

On the other hand, there are also those compared to standard MOS technology EEPROM's necessary additional process steps are economical in many applications justifiable.

Integrated circuits can then be produced, for example when testing by programming the EEPROM cells to special customer requests or Customer specifications can be adapted, for example to invert signal levels or for coding, ie z.3. by programming addresses.

In the general case, subcircuits are implemented on the chip linked to one another in the desired manner by freely programming the EEPROM cells, whereas, in contrast to gate arrays, the desired VerlKnUDfunx is carried out by the person himself can be.

The EEPROM cells used according to the invention can finally used to adjust analog functions. The comparison itself is on the one hand digital, e.g. 3. via the connection of resistors, and on the other hand analogously, e.g. 3. can be implemented via the controlled shifting of the threshold voltage in an EEPROM cell The controlled shifting of the threshold voltage of EEPROM memory cells by means of Time control is described in DE-OS 28 28 855.

It is within the framework of the invention that a memory field and at least one redundant sub-area in the number of memory cells the memory cell arrangement corresponding to the memory field is provided, and that an error address memory designed as an EEPROM memory is provided, depending on from its programming status the memory access from the memory field to the redundant one Memory cell arrangement is switchable.

A corresponding circuit is advantageously designed in such a way that that a controllable via a decoder memory field is provided that a designed as an EEPROM error address memory is provided in which the address of a can be stored for an addressable secure area of the memory field, that an address register in which the current memory address can be temporarily stored and which is connected to the decoder and the fault address memory is provided, since a redundant memory cell arrangement is provided, the number of memory cells corresponds to an addressable memory area of the memory field that a comparator is provided, the first wingang with the address register and its second input is connected to the error address memory and its output with the redundant memory cell arrangement is connected and that a blocking device is provided, by means of which depending on the output signal of the comparator access to the memory field can be blocked.

The invention is explained in more detail below with reference to the figures.

They show: FIG. 1 the circuit diagram of a circuit arrangement two sub-circuits depending on the programmed state of an EEPROM cell alternatively connects to a third subcircuit, which FIG. 2 is a block diagram of an embodiment for re-decoding defective memory areas in EEPROMs to redundant memory cells and FIG. 3 shows the circuit diagram of an inventive Arrangement according to FIG. 2.

In the figures, the same elements are denoted by the same reference symbols.

Fig. 1 shows the circuit diagram of a circuit arrangement shown in Two sub-circuits depending on the programmed state of an EEPROM cell T2 and T3 alternatively connects to a third subcircuit T1, the EEPROM cell with their peripheral circuits not shown for reasons of clarity is.

The subcircuit T2 is connected to the third subcircuit via a transfer gate 2 T1 connected, while the subcircuit T3 via a transfer gate 4 with the third Subcircuit T1 is connected. The programmed state of the EEPROM cell, i.e. either a "1" or an "O" is at point 1 and thus directly on the one side Control gate of the transfer gate 2 and, on the other hand, inverted via the inverter 3 on Control gate of transfer gate 4 on. Thus, the presence of a "1" means? Un: t 1 the transfer gate 2 is switched through and thus the subcircuit T2 with the partial sheath T1 connected while the transfer gate 4 blocks. If there is an "O" at the point 1, on the other hand, the transfer gate 2 is blocked and that which is triggered via the inverter 3 Transfer gate open, so that the subcircuit T3 is connected to the subcircuit T1 is. With a corresponding one-fold circuit arrangement are as a result of programming en of an EEPROM, different subcircuits can be connected to one another.

Fig. 2 shows a block diagram of an embodiment for Re-decoding; a defective memory area of the memory S to redundant memory cells E. The active memory field of the memory S, for example implemented in EEPROM technology, is e.g. addressable word by word, where naddress bits are required for 2n memory addresses (e.g. n = 11 for a 16 kbit memory with 8 bits per word) with at least one defective memory cell of the memory S should now be replaced by a redundant, The memory word stored in the substitute memory E can be replaced, i.e. in the illustrated Embodiment only one redundant memory cell s is provided. To this Purpose, the arrangement of Fig. 2 has an address register A, in de the current, for addressing the memory S Ventite memory address can be temporarily stored.

The address register A is connected to the row decoder D of the memory 5 connected. Other peripheral circuits belonging to the memory field 5, such as column decoders, Input and output circuit ect. are in Fig. 2 for the sake of clarity not shown and just like the line decoder (word decoder) D in itself feasible in a known manner (compare e.g. W. Söll and J. -d. Kirchner, Digitale Speicher, Vogel-Verlag-Würzburg, 1? 73, pages 128 to 131 and pages 152, 153).

The row decoder D, operating as a 1-out of 2n decoder, can as e.g. from A. Reiß, H. Liedl, W. Spichall, Integrated Digital Modules, Siemens AG, Berlin-Munich, 1970, page 235, 236 known to be designed as a NOR deconditioner.

For storing the address information determined during the testing of the memory field S. the faulty memory word of the memory S is a fault address memory F, the EEPROM cells and is connected to a control circuit 5, which is in on works in a known way and with the programming voltage Upp for programming connected to the EEPROM cells.

The content of the address register A is on the one hand via the line 6 the fault address memory F and on the other hand the first input of a comparator K can be fed in via line 7. The second input of the comparator K is Line s coming from the fault address memory F is applied. The output signal KA of the comparator K, which works as a commercially available comparator in such a way that it as an output signal if its signals applied to the inputs coincide KA issues a "1" on the output side. acts on one of the replacement memories r and on the other hand a storage device Sp. The blocking device Sp acts on the line decoder D or the memory field S in such a way that it depends on the output signal KA of the comparator K blocks access to the memory field S.

The circuit of Figure 2 operates as follows: Each in address register A standing address information is stored in the comparator K with that in the error address memory Z when the memory field S is tested, the address of the faulty memory area stored of the memory S compared. If the comparator K recognizes the same address data faulty memory line, the output signal KA of the comparator K (KA = "1") both the replacement line, which is the faulty memory area of the memory 8 replaced, i.e. replacement memory cher E, selected, as well as the regular one Memory field S blocked via the blocking device Sp.

The circuit diagram of an inventive, the block diagram of FIG. 2 shows the arrangement operating in accordance with FIG. 3. The memory field S is for Interprets 2n addresses, the row decoder D is designed as a 1- out of 2n NOR decoder. The address register A eist n memory cells, for reasons of clarity only the memory cell 9 for the first bit A1 and the memory cell 10 for the nth 3it are shown.

The coparator K is designed in such a way that for one bit, e.g. the first 3it Al of the address register A, an AND gate 15 and two NOR gates 13 and 14 are provided. The address bit A1 applies to one input of the AND gate 15 and the NOT gate 13, while the line coming from the fault address memory F 3 applied to the second input dos gate 15 and gate 13. The exits the gates 13 and 15 act on the NOR gate 14, the output of which has an input of the quadruple NOR gate 16, at the output of which the signal KA can be taken, is applied. The other comparator cells are designed accordingly, in the ig. 3 is off For the sake of clarity, only the nth comparator cell is shown.

The locking device Sp consists of two OR gates 11 and 12, wherein One input of each of the gates 11 and 12 has the output signal KA of the comparator K applied to it will.

The second input of the gate 11 can be acted upon with the address bit A1, while the second input of the gate 12 can be acted upon with the complementary address bit A1 is. The line decoder D is then used on the input side instead of the Admessbits A1 from the exit of the gate 11 removable signal A1 'and instead of the complementary address bit A1 from the signal which can be taken from the output of the gate 12 A1 applied. The other memory cells of the address register A are white Memory cell 10 shown, via the bits An and An lines leading to the row decoder D connected.

The non-volatile, electrically reprogrammable fault address memory F has n + 1 memory cells EI to En + 1 and the associated cutoff circuits on.

The fault address memory F is more advantageous than an EEPROM memory made of n-channel silicon gate type with floating gate and tunnel programming, as described, for example, in Electronics magazine, February 23, 1930, pages 113 to 117.

The one determined during testing is in the first n EEPROM cells E1 to En Address information of the faulty memory word can be stored. Because of Again, only the first cell EI and the nth cell En are shown for clarity. Each address information contained in the address register is compared in the comparator K with the im Error address memory F compared to stored error address. Detects the comparator in the case of address data energy the faulty memory line, .so is via the output signal KA of the comparator K (KA = "1't) the spare memory - in which the faulty memory line is saved, selected. Furthermore, via the signal KA, for example how shown in Fig. 3, for the address bit A1, both input lines A1 'and A1 "of the row decoder D is switched to" 1 ". Since all row lines carry an" O ", is in this way the line selection in the decoder designed as a NOR decoder D prevented and thus the memory field S blocked, so that the data from the replacement memory E and not read from the defective memory line of the memory.

Erasing an EEPROM floating gate cell (e.g. E1) is known in the art Manner, as described, for example, in the above-mentioned reference "Electronics", achieved in that electrons from the substrate into the floating Sceichergate 20 tunnel in. The memory transistor is due to the negatively charged floating gate 20 EI blocked when reading, a "1" appears at output 22.

At the beginning of the decoding, the error address memory is converted into a defined "1" initial state deleted.

The erasing process is carried out simultaneously for all n + 1 EEPROM cells E1 to En + 1 The tunnel window of the cells is on the side of the drain electrode 22 of the memory transistor. For reprogramming, erasing like writing, is the potential difference between the control gate 21 and the drain electrode 22 of the Decutting memory transistor. The common gate line is used when erasing 24 of all memory cells via the transistor TO on the programming voltage U ?, .3. to about 20 V. With this voltage, all memory transistors E1 to En + 1 are conductive and take the through the acting as load elements transistors T11 to T1n + 1, which are connected to the supply voltage VDD via the transistor T6, flowing stream on. The drain electrodes 22 of the memory cells are because the Source electrodes 23 are connected to ground, on O V and the one required for erasing There is a voltage difference on both sides of the tunnel window.

For writing the memory cells EI to En + 1 in the "O" state electrons tunnel from the floating gate 20 (back) into the substrate. The memory cells change due to the positive charge on Floatinggete 20 in the direction of the conductive state. During the writing, the gate line 24 of all cells is present above the transistors T3 and T9 nu the voltage O V and the memory cells are due the previous deletion securely blocked. Since only while writing the transistors Conduct T21 to T2n, the voltage depends on the drain electrode 22 of the memory transistors from the information A1 to An in the address register A. Is an address bit in state "O", the associated transistor T31 to T3n is blocked.

The drain electrode 22 of the memory transistors floats over the transistors T11 to T1n + 1 and transistor T4 to about 20V high. The voltage difference through the tunnel window is given and the cell is in the "O" state takes place. Is the address information present on the bit lines Al to Mn but "1", for example, in the case of the Dits, Al becomes through the transistor T31 and the transistor T21, the drain electrode 22 of the memory row E1 is set to low voltage. One Write voltage is not effective, the line remains erased in the "1" state.

So after writing there is a logical correspondence between the Information in address register A and the information in error address memory F established, i.e. the address of the memory word of the Memory word 8 is stored in the fault address memory F. Whenever in the course the later use of the memory this address is present, is thus via the comparator K carried out the decoding and not the faulty memory line of the memory field 5, but read out the information stored in the spare memory S.

The fault address memory F works in a total of three operating states: Erasing, writing and laying out, erasing and writing only one each Times is made. There are therefore at least two bits of control information for control necessary. For avoidance of unwanted programming errors of the error address memory F, for example when switching on the EEPRROM memory, the programming voltage Upp of about 20 V is advantageously used as one itself Control information is used that is only used when deleting or writing in the "high" state may lie, but must be "O" when reading out. The high voltage is across the transistor TO or T4 brought up to the memory cells EI to En + 1, the enhancement transistors T5 and T6 are blocked. For Upp = 0, on the other hand, the enhancement transistors are during the readout T0 and T4 blocked. The read-out voltage of about 5 V at gate 21 of the memory cells is switched off via the transistor TS, while the drain current is switched off via the transistor T6 the 5 volt operating voltage source VDD.

The second control information S / L (write / release) decides whether is deleted (S / L = "O") or should be written (S / L = "1") and has during the readout has no effect.

If the recoding of the incorrect memory address is carried out during the Slice measurement, i.e. at a point in time when the individual chips on which an arrangement according to FIG. 3 is integrated, not yet separated from the pane association are carried out, the programming voltage Upp is expediently via a own connection pads (pad) P supplied to the later chip assembly is not contacted (bonded). This is a subsequent incorrect programming locked out. The voltage Upp then always remains through the depletion transistor T7 to 0 V.

Since the state of the line S / L for Upp is 0 V without influence, can use this line without risk of malfunction with the control of the active EEPROM area (memory @ field @) γ @ can be accessed.

The surplus memory cell En + 1 of the fault address memory F, whose Drain electrode also an input of the multiple NOR gate 16 of the comparator K applied, is used to block the output of the comparator, if the redundant Memory word of spare memory E is not used (no faulty memory line in memory field S). The error address memory F is erased to the '1 "state right at the beginning of the target measurement and the comparator K is blocked, it remains then blocked if a write process is carried out because the regular memory field S is free from errors not happened.

The control device for the fault address memory F does not have to be included Memory field 3 and fault wire memory F are integrated on one chip, it can can also be provided externally and used for control when measuring the target will.

3 figures 3 claims

Claims (3)

Claims 1. Monolithic integrated circuit with on one Chip integrated subcircuits in which the linking of at least two parts circuits can be changed after production of the subcircuits, characterized in that that at least one EEPROM cell (E1) is provided, depending on their Programming state different subcircuits (T2, T3) by means of a circuit arrangement (2,3,4) can be linked to one another. 2. Circuit according to claim 1, characterized in that as sub-circuits (T1, T2, T3) a memory field (S) and at least one redundant, in the number of Memory cells a memory cell arrangement corresponding to a sub-area of the memory field (S) (E) is provided, and that a controller address memory designed as an EEPROM memory (F) is provided, depending on the programming state of the memory access switchable from the memory field (S) to the redundant memory cell arrangement (E) is. 3. A circuit according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that a memory field (S) which can be controlled via a decoder (D) it is provided that a fault address memory (r) designed as an EEPROM can be seen is, in which the address of an addressable memory area of the memory field (S) can be saved, that an address register (A) in which the current Memory address can be temporarily stored and that with the decoder (D) and the error address memory (F) is connected, it is provided that a redundant memory cell arrangement (E) is provided, the number of memory cells of which is a memory area that can be addressed by itself of the memory field (S) corresponds to the fact that a comparator (K) is provided whose first input with the address register (A) and its second input with the error address memory (-) is connected and its output (KA) with the redundant memory cell arrangement (E) is connected and that a locking device (Sp) is provided by means of which depending on the output signal (KA) of the comparator (IC) the access to the Storage field (s) is lockable.