DE3038088A1 - Data receiver for video signal processing appts. - has capacity for handling digital data of varying length and code format - Google Patents

Abstract

The digital data receiver for video signal processors has the capability to handle various data formats e.g. code and length. The video signal is applied to a video analogue processor that operates with a timed gate to separate the video and data signals. The data is transmitted to a serial memory with the output converted into parallel form for processing by a computer. The computer responds to horizontal and vertical synchronising pulses to generate pulses for a clock circuit that controls the operation of the serial memory, that is of a shift register format.

Description

DATA RECEIVER FOR A INTO A VIDEO SIGNAL

KEYED DATA 1 GNAL The invention relates to a data receiver of the type specified in the preamble of claim 1. Such a recipient is from the magazine - "Rundfunk-Technische Mitteilunge", Issue 2, 1972, page 90 known.

In the known data receiver for the one in the blanking interval A video analog processor extracts data line signals that have been keyed in the video signal data information, which in a data comparison stage with a 1 in the circuit preprogrammed bit sequence is compared. Will start or a bit sequence is recognized during a data transmission that has been preprogrammed in the receiver Sequence (start code), then the data that are received after this bit sequence are subjected to real-time data processing. This processing provides that immediately after receiving a bit sequence; which can be checked for errors, a Plausibility check of the data is carried out. Then takes place most of time storing the information in data memories. The circuit design of the known Due to the real-time data processing, the data receiver is mostly for fixed data formats with a defined word length and predefined, user-specific signal outputs. As a result, the data receiver can only be used for discrete tasks generally does not allow the evaluation of different data formats.

The object of the invention consists in a data receiver of the type mentioned at the beginning, a simple adaptation to different data formats, such as start codes different in code and length and different data words, can also be achieved during data transmission of varying lengths.

The object is achieved according to the invention by the features of the claim 1 solved.

The idea of the invention is based on the following consideration.

In order to achieve real-time data processing within the data receiver Avoid, the data will be considered for the transfer during the period Time segment via a microcomputer controlled time gate to a serial Memory switched and cached there unchecked. the The timing gate is controlled by the vertical sync pulse and the sync pulse of the television signal derived. The opening time of the time gate is chosen so long that it can be assumed that the relevant data transfer is completed within the opening hours is.

Finally, after the time gate is blocked, it will be switched over the clock switching device sends a clock generated by the microcomputer to the shift register switched, the dimensioning of which was chosen so that the during opening hours the amount of data arising from the time gate can be temporarily stored.

The subsequent reading out of the data in a serial / parallel converter if necessary. are parallelized, is controlled by the microcomputer, which the data takes over, checks for validity and processes it in a user-oriented manner.

The invention is explained in more detail with reference to the drawing, which a Reproduces the block diagram of the data receiver according to the invention.

The data receiver shown is intended for data signals that keyed into a video signal. Such data signals can for example for the transmission of teletext information, which with the help an additional device (teletext decoder) from the television audience on their home television receivers can be reproduced. Furthermore, the mentioned data signals can also broadcast-internal information, for example control information for the automatic Control of converters or the like. Included. The length of such a data signal may correspond to the length of one or more television lines, the data shown receiver is so flexible in terms of its design that it can accept the above Differences in terms of the data signal length can be easily adapted.

The data signal arriving at the input of the data receiver shown containing video signal is the signal input ll of a video-analog processor 1, which together with a downstream time gate 2 from the video signal separates the data signal. Of course, the time gate 2 can also be in the processor 1 be integrated; the illustrated division into two circuit blocks is only used for a better understanding of how the data signal is disconnected.

The processor 1 has a data output 14, which is connected to a data input 21 of the time gate 2 is connected and acted upon with the data entered in the video signal is. The time gate 2 is controlled by a computer in a manner which will be explained in more detail below 6, in the example shown by a microcomputer, controlled on its For this purpose, control output 65 generates a time control signal which is sent to the control input 22 of the time gate 2 is supplied.

That of the timing signal in time relation to the time format of the video signal defined time window determines which of the data input 21 of the time gate 2 are transmitted to the data output 22 of the time gate 2 and are thus cached from there in a serial memory 4. By definition, this buffered signal is the data signal keyed into the video signal.

The serial memory 4, for example a shift register, is loaded via its loading input 41 with the output signal of the timer 2, namely under the control of the processor 1, which has a data signal at its output 13 derived clock signal generated.

This clock signal is applied to the clock input via a clock switching device 3 of the serial memory 4 is supplied.

The clock switching device 3 is used to switch the clock input 42 of serial memory 4 the read-in clock from processor 1 and the read-out clock from the computer 6 to connect. For this purpose, the clock switching device 3 is via a control input 32 is connected to a control output 64 of the computer 6, on which the computer 6 Switching commands for device 3 generated. Furthermore, the clock switching device 3 with a first signal input 31 to the output 13 of the processor 1 and with a second signal input 34 is connected to a clock output 63 of the computer 6. Of the Signal input connected through to the signal output 33 of the switching device 3 31 or 34 is decisive for the clock control of the serial memory 4, namely the signal input 31 for the read-in cycle and the signal input 34 for the read-out cycle of the memory 4. To generate the start time point / readout clock at his Clock output 63 is the computer 6 via corresponding inputs 62 and 67 with outputs t2 or l5 of the processor connected to which the vertical sync pulse bmv.der the sync pulse of the video signal is present.

The data signal temporarily stored in the memory 4 remains there stored until the computer 6 calls it up. This retrieval takes place through generation a switchover command at the control output 64, which means that the signal input 31 connected signal output 33 of the switching device 3 now with the signal input 34 is connected and thus the clock input 42 of the memory 4 with the readout clock at the clock output 63 of the computer 6 is applied. This will the memory 4 is read out, the data being applied to the data output 43 of the memory 4 Data signal is first fed to a serial / parallel converter 5 to convert to the parallel format to be converted. For this purpose, the converter 5 with its data input 51 is connected to the Data output 43 of the memory 4 connected. The converter 5 is controlled via a clock input 52 which is connected in parallel with the clock input 42 of the memory 4 is. The parallelized data signal is from the output 53 of the converter 5 to the data input 61 of the computer 6 transmitted, which the data of the data signal for validity checks and processes it in a user-oriented manner, i.e. information via its data output 66 outputs which is desired or required by the user or users concerned will Blank page

Claims (2)

PATENT CLAIMS W Data receiver for a keyed into a video signal Data signal, with a device for separating the data signal and the synchronous information from the video signal and having means for storing the separated data signal in accordance with one obtained from the transmitted signal or from its components Clock information, the data of the stored data signal possibly. In parallel the memory device can be read out, that is to say t that the device (1,2) for separating the data signal has a time gate (2), which is controlled by a computer (6) fed with the synchronous information, in such a way that the data signal limited in time by the time gate (2) is unchecked in the storage device (4,5) is stored. 2. Data receiver according to claim 1, characterized in that the Computer (6) dateneingangsseii g is connected to the memory device (4,5) ud a read-out clock signal for the memory device (4, 5) is generated, the duration the readout process depending on the information content of the in the computer (6) given data signal is selected.