DE2719248C2 - Frequency-selective character receiver for telecommunications, in particular telephone systems - Google Patents

Description

The invention relates to a frequency-selective character receiver for telecommunications, in particular telephone systems, with provided at its input limiter circuits, in which the received Characters consist of several simultaneously occurring individual frequencies, each of which has a specific Frequency group is assigned, and in the case of the square-wave voltages derived from the individual frequencies detector circuits which determine the respective individual frequency by means of a counting circuit, which is controlled with a clock frequency that is high compared to the frequency to be determined.

With such character receivers it also occurs due to the different individual frequencies evaluation times of different lengths for the individual frequencies. Higher individual frequencies become faster evaluated as lower individual frequencies, regardless of whether only one or several periods the individual frequencies to be evaluated are used for the evaluation process. So it can If a constant evaluation time is not taken into account, significant character distortions occur This means that the character duration of the character output by the character receiver for further processing is correct does not match the character duration of the character queued at the input of the character receiver. However, the lowest possible character distortion

ίο specifically required when a character recipient of the type mentioned above is used in data transmission traffic.

The object of the invention is to provide a character receiver of the type mentioned above, which always has constant evaluation times for all occurring frequency combinations

According to the invention, this object is achieved by initially having a small number per frequency group of periods of the square-wave voltages through broadband monitoring of their half-periods Affiliation to the respective frequency group is checked that after recognizing the affiliation of the square-wave voltages for the individual frequency groups during a certain number of

Periods by means of the counting circuits, the frequency channels concerned are determined and that after the Determination of the frequency channels the counter circuits during an individually assigned to each frequency channel Continue counting the number of periods, where

the monitoring of the half-periods per frequency channel is carried out in a narrow-band manner.

From DE-AS 23 41 224 it is known to the Split the character recognition process into two parts, with a preliminary test with a larger bandwidth first and then a main test with a smaller bandwidth is carried out. With this well-known However, it is only a matter of giving as much time as possible for the actual procedure through the preliminary test To have character recognition process available.

In the character receiver according to the invention, a small number of period durations are first implemented Half-period control monitored for membership of a frequency group. This allows for falsifications by DC crackling, such as. B. by switching the keypad from speech to Eliminate the dial state, transients of the dial oscillator and the filters in the receiver. Thereupon is determined over a certain number of pulse periods by comparison with a high-frequency clock frequency the relevant frequency channel is determined. The further counting process is dependent on the channel detection controlled that a number of periods individually assigned to the channel is counted. The assignment the number of periods for the channels is chosen so that for the individual frequencies and thus for all occurring Frequency combinations result in almost constant evaluation times. That way you can take into account With a constant evaluation time for all frequency combinations, distortion of characters can be avoided. By programming the individual counting circuits, according to the recognized individual frequency, it is achieved that in the case of a voice-protected character receiver for additional voice-securing Measures, a constant time range is always available.

A further development of the character receiver according to the invention is characterized in that the Counting circuits after missing the character on

Pay back the input of the character receiver and emit a signal when the counter reading O is reached, which delete the evaluated character stored in the main memory. This measure represents a represents drop-delayed signal output. The drop-out delay corresponds exactly to the evaluation time

Another expedient development of the character receiver according to the invention is characterized in that that the counting circuits after evaluating a character and simultaneously setting the main memory are reset and after the completion of a character bii to one of the constant evaluation time count the corresponding counter reading, a signal derived therefrom being the one stored in the main memory deletes evaluated characters. By using them as delay circuits, the counting circuits used twice at the same time, so that there is a saving of further assemblies.

An embodiment of the invention is shown in the drawing and will be described in more detail below described.

In the illustrated embodiment, only the assemblies essential for understanding the invention are shown shown. A character receiver for a 2 * (1 out of 4) code was chosen as an exemplary embodiment and therefore only the evaluation circuit for the lower frequency group shown in more detail, since the evaluation circuit for the upper frequency group is identical to that of the lower frequency group.

The signal input of the character receiver is marked with 5. The received character first reaches group filters F via input 5, in which it is amplified and separated according to groups. The output signal of the group filter F is fed to the limiter circuits B. In the limiter circuits B , the respective symbol voltage is converted into a square-wave voltage of constant amplitude. This square wave voltage is then fed to the actual evaluation part.

For each frequency group, the square-wave voltages are fed to both a control counter ZS and a counter for the half-cycle control ZHK. The control counter ZS counts the number of periods and, after a certain number of η 1 periods, releases the gate circuit 1 for the high-frequency clock supplied by the clock generator TG. If the received character is audio-frequency signals according to CCITT Q 23, that is, the individual frequencies of the lower frequency group are between 697 Hz and 941 Hz and those of the upper frequency group between 1209 Hz and 1633 Hz. B. η 1 for the lower frequency group 3 and 5 for the upper frequency group.

During the first η 1 periods, the counter for the half-period control ZHK monitors the frequencies received per group broadband, ie a certain maximum value is specified for each of the individual frequencies occurring within the frequency group, which the individual half-periods must not exceed. If this maximum value is exceeded, the control counter ZS is reset by the counter for the half-period control ZHK .

After the gate circuit 1 has been released, ie after it has been recognized that the received individual frequencies belong to the respective frequency group, the evaluation counter ZA W is started. The evaluation counter ZA W counts the clock pulses supplied by the clock generator TG for a certain number of periods specified by the control counter ZS. Corresponds to the Auszählergebnis according nl periods eii ^ he occurring in this frequency group individual frequencies, so the Auswertezähler ZAW outputs a corresponding to the detected single frequency signal to the taxpayer ZS, the counter for the half period control MAC and the OR gate N2 to the gate circuit. 2

If a signal is present at the output of the gate circuit 2, that is, if an individual frequency has been recognized in both the lower a! S as well as in the upper frequency group, this signal can be fed to a splitting memory 55, which emits a signal at its output Ag which z. B. can be used to separate the continuing speech path. Afforded the Auswertezähler ZAW by counting the specified by the control counter ZS number of η 2 periods a result - as described above - so this will continue to be used to program the control counter ZS and the counter for the half period control ZHK sensitive to control that is narrowband. The control counter ZS is programmed depending on the identified individual frequency. This means that a certain number of periods is specified for each identified frequency, during which the evaluation counter ZAW continues to count. At the same time, the counter for the half-period control ZHK is set in such a way that the half-period control is no longer carried out individually for each frequency group, but rather individually for each detected frequency. This happens e.g. B. in that certain gates, which correspond to certain counter readings and thus certain values for the individual half periods, are connected in preparation via a gate network connected downstream of the actual counter for the half-cycle control ZHK.

When the final value specified by the control counter ZS is reached, the evaluation counter ZA W, if its counting result can be assigned to one of the four individual frequencies, emits an output signal which is fed to the OR gate N3 and at the same time fed to a main memory HS via gate circuits. At the same time, these output signals from both frequency groups are fed via the OR gates Λ / 3 to a decision circuit E , which ensures that a result in the upper frequency group is also available at the time the lower frequency group is queried. If this is not the case, the evaluation counters ZA W, the control counters ZS and the splitting memory SS are reset via the output /? £.

For this purpose, it should be noted that the output of the decision circuit Re E is identical to the shown in the drawing OR gate inputs R _E, ie is electrically connected which is not shown in the drawing for reasons of clarity. The same applies to the output Rzhk- described later.

The decision circuit £ thus guarantees, in addition to a temporal parallel evaluation, in both frequency groups a coincidence control.

At the beginning of the signal pause, the counter for the half-cycle control ZHK emits a pulse which, via the gate circuit 4, causes the evaluation counter ZAW to count down. When the counter reading is 0, the main memory HS is deleted via the gate circuit 5. This measure represents a delayed signal output and at the same time ensures that the recognized character is retained in the main memory HS ,

regardless of brief signal interference.

If, during the evaluation process, the counter for the half-penodic control ZHK detects a pulse duty factor which deviates from the specified values, the control counters ZS, the evaluation counters ZA W and the split memory SS are reset or deleted via the output Rzhk. The same applies if the end of a character is recognized by the counter for the half-penodic control ZHK before the evaluation process is completed.

1 sheet of drawings

Claims (3)

Patent claims: '. Frequency-selective character receiver for telecommunications, in particular telephone systems, with provided at its input limiter circuits, in which the received characters from consist of several simultaneously occurring individual frequencies, each of which is a specific one Frequency group is assigned, and in which square-wave voltages derived from the individual frequencies Detector circuits are supplied, which the respective individual frequency by means of a counting circuit determine which clock frequency is higher than the frequency to be determined is controlled, characterized in that initially one per frequency group small number of periods of square wave voltages through broadband monitoring of their Half-periods are checked for membership of the respective frequency group that after detection the affiliation of the square-wave voltages to the individual frequency groups during a certain number of periods by means of the counting circuits the relevant frequency channels be determined and that after the determination of the frequency channels, the counting circuits during a continue to count the number of periods individually assigned to each frequency channel, the Monitoring of the half-periods per frequency channel is carried out in a narrow-band manner. 2. Frequency-selective character receiver according to claim 1, characterized in that the counting circuits count down after no character at the input of the character receiver and a signal when the count reaches 0 which deletes the evaluated character stored in the main memory. 3. Frequency-selective character receiver according to claim 1, characterized in that the counting circuits after evaluating a character and simultaneously setting the main memory is reset and after the completion of a character up to one of the constant evaluation time count the corresponding counter reading, a signal derived therefrom being stored in the main memory Deletes saved, evaluated characters.