DE2434386A1 - PROCEDURE AND CIRCUIT ARRANGEMENT FOR CYCLICALLY NEW DISPLAY OF INFORMATION SIGNS ON A DISPLAY DEVICE - Google Patents

Description

Method and circuit arrangement for the cyclically renewed display of information signs on a display device (Addition to "Patent 2 226 312)

The subject of the main patent is a method and a circuit arrangement for cyclically renewed displays of Information characters on a multiple scan jumps for a display line generating display device selectively indentering the visible state of M-bits on N-scan jumps for each character, with the display wanders in fractions of the scanning jump increments.

There is one in the main patent and also in US Pat Technique for moving characters across the screen of a display device such as a cathode ray tube in FIG Increments of one or more character scan jumps are described, with a scan jump here as a column of a matrix forming the character. This possibility of advancing the ad by a fraction one character for each frame return of the cathode

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ray tube, being the fraction of a character to add the the display advances, which is a function of the number of buffered characters waiting to be displayed theoretically a display that is placed on a viewer as an approximately steadily moving display a display that moves with incremental jumps is effective. In practice, however, it has been found that even if the display advances in increments of a single scan jump, a specific one still appears jumping appearance of the display results, which is not satisfactory from the aesthetic point of view. It is therefore to seek a technique for controlling the display on a display device such as a cathode ray tube; which allows the display to advance in increments of less than one scan jump.

Another feature of the subject matter of the main patent is the ability to display different information Types, e.g. of stock exchange names and associated prices, which are below each other by half a line are offset, the information is to be displayed one after the other on a single line. For this purpose, the The subject of the main patent is the information of different types in different parts of a memory stored, the information from a part of the memory for rewriting one line and the information from the other part of the memory for Ife writing which is read out by a line shifted down by half a line. This technique requires a large amount of memory, because two parts of a memory are required to * store the information that would otherwise be in a single one Part of the memory could be stored. It would therefore be desirable, using the display technology of the Main patent to be able to store this information only in a single part of a memory.

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The object of the invention is therefore to develop the method and the circuit arrangement specified in the main patent in such a way that that a continuously moving display for the viewer is made possible and the necessary Memory for the circuit arrangement can be reduced.

In a method of the type mentioned, this object is achieved according to the invention in that the number of fractions the scan jump increments is determined and displayed to increase the display that a first The counter continues to count depending on the number displayed, with each increment of the first counter being a specific Partial scan jump increment corresponds to the indication that a second counter depending on an overflow of the first counter is counted further, each increment of the second counter being a complete sampling jump increment corresponds to that consecutive characters for display on the display device and that the output signals of the first and second counters for controlling both the scan jump and the bit of this scan jump at which the display of the first of the consecutive characters begins.

According to a development of the invention, a circuit arrangement created to carry out this method, which is characterized by a first counter, each of which Increment a certain partial scanning jump increment of the Display corresponds to, by a second counter, each increment of which corresponds to a complete sampling jump increment and which is connected to the first counter in such a way that it can be further counted by a carry signal of the first counter is, by a first circuit for determining and displaying the number of predetermined partial scan jump increments, around which the ad has to grow by one on

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the number indicated by the first circuit responding and the first counter by this number further counting the second Circuit, by a successive character for the display feeding third circuit and by one to the Fourth circuit responsive to output signals of the first and second counters for controlling both the sampling jump also of the bit of this sampling jump in which the first of the consecutive characters can be displayed.

If the display device is a cathode ray tube, the circuit arrangement has a fifth circuit aif, which causes the return of the cathode writing beam at each end of a display line, as well as a sixth Circuit for blanking the write beam during a certain time interval after the return has been initiated. The fourth circuit then controls both the scan jump as well as the bit of this scan jump of the last of the successive characters which are given to the display device in which the fifth circuit for the return is activated.

A line of characters to be displayed can have different characters Types, the characters of one type being a fraction of a line below the characters of are to be displayed in a different manner. To spit on one Line to be displayed characters in successive address positions is provided a memory. The signs of the one Type have a specific identifier that starts with them are stored together in memory. A seventh circuit is then provided which, when reading out the Memory is effective to determine the type of character from the stored identifier and to control this the character position on the display device.

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Lie invention is explained in more detail with reference to an embodiment shown in the drawing. In detail demonstrate:

1 shows a schematic block diagram of the new circuit arrangement,

Pig. FIG. 2 is an explanatory view of the contents of a memory for characters similar to that shown in FIG Circuit arrangement is used,

Fig. 3A showing a line of the display device according to a preferred embodiment of the invention,

Fig. 3B by one line of the display shown in Fig. 3A a frame time later for a first group of accepted. Conditions and

Fig. 3C shows one line of the display shown in Fig. 3A one or more frame times later for a second group of assumed conditions.

Although the new method and circuit arrangement work with any walking display device in which Characters by selectively inducing the visible state of M bits in each of H columns or scan jumps for each Characters can be formed, can be used in the preferred embodiment described here is a cathode ray tube used as a display device. This display device has the ones described in more detail in the main patent Properties and is described, for example, in U.S. Patents 3,4-28,851 and 3 500 327 explained in more detail. The ones in these Paent scripts The display used is formed by generating multiple scan jumps for each line of the display, where

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a character by selectively lighting seven out of nine bit positions on each of five sample jumps is formed. Two additional sampling jumps are for each character is intended for the space between two characters. Such a display is shown in FIG. 3A for a single example line of the ad shown, the ad being for ad the Few Yorker Stock Exchange is used.

For the aesthetic reasons described in the main patent, there is a half-line spacing between the alphabetical Share ader stock market names of the ad and the numbers or price information provided.

The circuit shown in Fig. 1 for a preferred Embodiment of the new circuit arrangement has a memory 10 with random access in which Characters to be displayed on the display device and selected numbers waiting to be displayed, buffered Characters are stored. In Pig. 2 shows the contents of the memory 10 for an exemplary embodiment which has been explained. For this embodiment it is assumed that 48 characters are displayed in a moving line and 16 buffered character positions are provided. As indicated in the main patent, a character counter 12 is seen before which indicates the character position in the memory 10 at which read out under the control of a readout circuit 14 to start the line of characters to be displayed. Only for the following explanation it is assumed that that the character position Ϊ1 is the character address contained in the counter 12 is. The circuit also has an input address counter 16 which shows the address position indicates in memory 10 at which the next received character is stored. It is assumed that this

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Counter indicates the character address 4 ·. In Fig. 2 are Arrows entered to indicate these two accepted addresses.

As best seen in FIG. 3A, the indicated Information for a stock market ticker has two types of information, namely an alphabetical one Exchange identification code and prices given in figures or, in some cases, quantities. It is also to recognize that the price or quantity information is a half line below the stock exchange information. Thus the two different types of information can be recognized and differentiated, is an additional bit, the bit 8, for each character in the memory 10 provided that-is marked for the numerical price and quantity information. At this point it should be noted that that although the memory 10 is considered to contain only the traveling message for display in a given line Memory is specified, this information can only be contained in part of a larger memory the information to be displayed on an entire frame or picture for a given display device and others Information on the given display device or other display devices also included can.

As shown in FIG. 1, the data bits received on an input line 18 are stored in an input buffer register 20 is stored until a complete character is detected by a detector 22. If this is the case, so * the detector 22 generates an output signal on a line 24-, which is connected to an input of an AND gate 26 is. At the next memory cycle time, a signal appears on line 28, whereby the AND gate 26 through-

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-3-

is switched, which is an output signal on a line 30, which actuates a write control circuit 32 and activates the numerical detector 34- so that this determines whether the character in the buffer register 20 is a stock exchange identification character or a numeric one Is price or quantity symbol. Switching on the write control circuit 32 has the effect that the buffer register 20 stored characters is written into the memory 10 at the address indicated by the counter 16. Provides the Detector 34 - determines that the stored in buffer register 20 Symbol is a price or quantity symbol, it generates a signal on a line 36, whereby bit 8 of the saved character is highlighted. The signal on line 30 is also applied to input address counter 16 given to continue counting this to the address at which the next received character is to be stored.

As previously indicated, a character counter 12 is provided for indicating the character position in memory 10 from which the The first characters to be displayed on the moving line are read out. In addition to the character counter 12, there is a si.eben Scan jump counters 38 indicating states and a three Bit counter 40 indicating states is provided. The operation of these counters is briefly explained.

For the purposes of the following explanation it is assumed that the counter 12 points to the character position 11 initially and counters 38 and 40 are both set to EuIl. Therefore, while a frame is displayed, the line reached on which the scrolling display is to appear, the readout control circuit 14 causes the on The characters to be displayed in the line are read out one after the other on a line 42 starting with the character position 11 will. Bit 8 of each read out on line 42

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Character is given to a bit 8 detector 44 · which determines whether bit 8 is present or not. Since the character at character position 11 is part of a stock exchange identification is, bit 8 for that character is not marked, causing an inverter 50 to provide an input signal an AND gate 52 gives * Assume that the display should appear on line 2 of the frame, a signal also appears on clock line 54- for line 2 at this time, whereby the AND gate 52 the given character on the line 4-2 via the OR gate 56 and a video character generator 58 to an AND gate 60 lets through. Assume that a video flip-flop is set at this point in time, the AND gate 60 is switched through to receive the video information from the generator 58 to let through to a display device 63.

A clock source 64- is of conventional construction and can contain various counters, the output signals for specifying the line, the character, the scan jump and the Specify bit position at which display device 63 is currently being written during each frame return cycle will. This clock source 64 · also generates clock pulses during the frame retrace, which will be used later described manner. The output signals of the clock source 64 are at various points in FIG Circuit shown and appropriately designated, the line 54- carries such an output signal.

From the above it is clear that only characters whose bit 8 position is not marked, i.e. stock exchange identification characters are given to the character generator 58 when the line 2 on the display device 63 appears in reverse. In this way, the line return for the line shown in Figure 3A appears on the Display device.

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When the return for line 2 is finished, the Memory 10 is read out again, this time with the appearance of a clock signal on the one assigned to line 3 Clock line 66. The signal on line 66 is given as an input to AND gate 68, wherein the other input signal for this AND gate, the output signal from the Bi t-8 detector 48 is. To this During the time of line 3, the characters with a marked bit 8, i.e. the characters for prices and Quantities given by the AND gate 68 and the OR gate 56 to the character generator 58, the video output signals be given via the AND gate 60 to the display device. In this way, as shown in Fig. 3A , the line 3 is written during the second reading of the memory 10. The generation of half the line spacing between the lines is, as stated above, described in more detail in the main patent and does not constitute a feature of the present invention.

At the end of the frame, certain frame return clocks are generated. The first of these clocks is one for the frame return (FR1 clock) on the line 70, which is used to set a buffer counter 72 to 16 and to switch through the gate 74 to read the contents of the input address counter 16 in the address To save counter 76. The address stored in counter 76 is compared in a comparator 78 with the address stored in character counter 12. If these two addresses are not the same, which is the case when there are any buffered characters waiting to be displayed in memory 10, comparator 78 generates an output on mismatch line 80 which gate 82 turns on to pass each subsequent FR clock on line 84- for counting down buffer counter 72 and for counting up address counter 76.

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If the counter 76 is counted to an address equal to the is in counter 12, the one stored in buffer counter 72 is Count equal to the number of characters that are buffered in memory 10. At this point a match output appears from the comparator 78, which is given to the gate 88 for switching, so that the Count of the counter 72 is let through to count detectors 90. The detectors 90 are actually decoders, which sends an output signal to a through the count im Buffer counter 72 give given line. In this way an output signal from the detectors 90 appears when the count in the buffer counter 72 was zero, another Output signal if the count was 1, a third output signal if the count is between 3 and 5, and finally.an additional output signal when the count is between 4 and 6 and the like. Between There is a certain overlap in the counter readings Shift points will change as the number of bits increases or decreases that the shift is for counting each frame.

The output signals from the detectors 90 are sent to a shift control circuit 92, which consists of a number of flip-flops, one for each possible shift increment, and gate circuits for controlling the setting of the respective flip-flop in dependence from the output signal of the detectors 90 and the current switching state of the flip-flops. The circuit 92 generates an output signal on one of seven lines 94- · Although circuits 90 and 92 not shown or described in detail are circuits of execution these functions are specified in the main patent, which can also be used here.

As shown in Figure 3-A- there are nine bits for each sample jump of a character provided, seven of these nine

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Bits are used for the display. In the preferred embodiment of the new circuit arrangement, the display is advanced by a third of the scanning jump increments. In this way, the display of a character scan jump can begin at bit position 1, the bit position more stupidly at bit position 7 on the scan jump. The output signals on lines ° A indicate the number of 1/3 scan jump increments the display advances between successive frames, with an output on line 94A indicating that the display advances three bits and an output on the Line 94B indicates that the display advances 6 bits and an output on line 94C indicates that the display has to advance 9 bits or a scan jump. An output signal on line 9 ² IE indicates that the display advances by two sample jumps, while an output signal on line 94-Gr indicates that the display advances by three and a third sample jumps, ie by 30 bits. As previously indicated, the smaller increments occur when there are a relatively small number of characters in the buffer portion of memory, while the larger increments occur when the buffer is nearly full.

Lines 94- are for the advance inputs connected to the three-stage bit counter 40. Each of the lines 94- causes the counter 40 to increase by the number is counted next, which is indicated next to them. In this way, a signal on line 94-A will cause the counter is incremented by 1, a signal on line 94D that the counter is incremented by 4 while a signal on line 94G causes the counter to increment by ten. A carry signal from the bit counter 40 on line 96 causes the seven incoming

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scan jump counter 38 is counted further. In the same way, a carry signal causes on line 98 from scan jump counter 38 that the character counter 12 is counted on. The counters 12, 38 and 4-0 continue to count at selected cycle times during the frame return (FR N-clock) if a Clock signal appears on line 100.

Two signals used in the circuit arrangement shown in Fig. 1 are a "Vander" signal on the line 102 and a "non-wandering" signal on line 104. A signal appears on line 102 when a line moving across the display area is written again. A signal appears on line 104 to all others Times. Lines 102 and 104 may, for example, carry output signals from a flip-flop, which may be from a suitable external device or depending on a selected clock is set, or can be set directly by derived from an external device or the output signals from gates controlled by suitable clocks to lead.

The three output lines from the scan jump counter 38 are either direct or inverted as input signals given to each of seven AND gates 106 A to 106 G, only three of which are shown in FIG. 1, the others Input signals to each of these AND gates a selected sampling jump clock, the signal on the line 102 and a synchronization signal on line 108. Line 108 is the output line from the OR gate 110, whose inputs are connected to output lines 112 and 114 of AND gates 116 and 118. The entrances of AND gate 116 are connected to a character clock line CM, line 104 and output line 120 from the OR

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Link 122 connected. The inputs of the OR gate 122 receive various selected line clocks (e.g. LA). The inputs of the UlTD element 118 are connected to a character clock line for the character CN, the line 102 and the output line 124- from the OR gate 126 connected. The entrances of the OR gate 126 receive various further selected line clocks (e.g. for lines 2 and 3 in the preferred embodiment). The line 108 for the synchronization and the line 104 · are also connected to inputs of the AND gate 130, the The last input of this AND element is connected to the clock line for the sampling jump 1. The outputs of the AND gates 106 and 130 are connected to the inputs of the OR gate 132. In this way, the Indication that should not wander, an input signal to the OR gate 132 at the time of the sample jump 1 one selected character time for the line, namely for the CM character. The CM sign is the sign after the last one Characters of the line to be displayed. For a wandering line an input signal is given to the OR gate 132 at the time of a selected sampling jump, depending on whether the gates 106 are turned on by the outputs of the counter 38 at the CN time of the line. At a preferred embodiment, the character N is the character 4-9 Since this 4-9th character, as will be described later, either partially displayed or not displayed at all, it can be considered the last character to display will.

In the same way, the line 104- is one input an AND gate 134 · connected, the other input is connected to a clock line B1, while the line 102 is connected to an input of each of three AND gates 136A to I36C, the other inputs of which are connected to Clock lines Bl, B4- and B7 are connected and an out-

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selected aggregation of direct or inverted output signals on the two output lines from the three states having bit counter 40 obtained. The output lines the AND gates 134 and 136 are connected to the inputs of a OR gate 138 connected. That way, that gets OR gate 138 receives an input signal at the time of bit 1 of each scan jump if the line is not moving Line is, or at times B1, B4 or B7 of a line depending on the count of the counter 40, if the line is a wandering line.

The output line 140 from the OR gate 132 is as a set input to the synchronization flip-flop 142 and above the inverter 144 is connected as a reset input to this flip-flop. -The signal on line 140 is also over a 6 character delay 146 as an input signal given to dis AND element 148. If a signal appears on the line 150, which is the case in the idle state, then the AND gate 148 is switched through to the output signal from the delay 146 to the set input of the video flip-flop 62 to let through. An output line 152 from the OR gate 138 is with the clock inputs of both the Video flip-flops 62 as well as the synchronization flip-flop 142 connected. The output line 154 from the set side of the flip-flop 142 is to the input for the line return or the line synchronization of the display device 63 connected. An output line 156 from the reset side of flip-flop 142 is connected to the inverting reset input of video flip-flop 62. on in this way, the video flip-flop 62 is reset when the sync flip-flop 142 is set. A shutdown input for the reset side of the video flip-flop is also provided, although this input is not used in the present invention.

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From the above it follows that for a non-moving line on the display device, an output signal is generated on line 140 by OR gate 132 at the time of scan jump 1 of the character, which follows the last character appearing in the line, whereby the synchronization plip-plop 142 is set, and at the bit 1 time of the sample jump before any To indicate which character can be generated, a clock signal appears on output line 152 from the OR gate 138, which sets flip-flop 142 to a line retrace sync signal to be generated, which is given via the line 154 to the display device 63. That Setting the sync flip-flop 142 terminates the signal on line 156, causing the video flip-flop 62 is reset. This disables gate 60 so that there is no video display during the return line can.

At the end of. The AND element is the time for the sampling jump 1 (S1) 130 locked, putting the signal on the line disappears. As a result, the inverter 144 generates an output signal that resets the flip-flop 142. It will assumed that the line return takes exactly 6 characters. If the line return has ended, so the delay 146 produces an output which again sets the flip-flop 62, thereby canceling the video display can occur again.

For a moving line, generating a return line signal is more complicated. At the time for the 49th character of the line which precedes a moving line, the gate 118 is switched through so that a synchronization signal may appear on line 108. Depending on the count of the scan jump counter 38 one of the AND gates 106 is switched through.

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Purely the state of the counters, which was previously assumed, namely for those in Pig. 3A, the gate connected is AND gate 106A. In this Pail becomes a set input to flip-flop 142 given at the time of the sampling jump 1. In the same way, it depends on the count of the counter 40, which of the AND gate 136 is switched through. For the in Fig. 3A The AND gate 136A is switched through, whereby the OR gate 138 is an output signal for clocking of flip-flops 62 and 142 are generated at time B1. In these switching states, the circuit arrangement causes a Return lines in the same way as explained above for a non-moving line.

It is now assumed that a relatively small number of Character is stored in the memory 10 at the end of the frame, the shift control circuit 92 generates an output signal on the line 94A, whereby the counter 40 is counted by 1 to a count of 1. The next Time at which the letter N of line 1 is reached causes gate 118 to become conductive to a sync signal to generate on the line 108 and to keep the count of the sample jump counter 38 unchanged, while the AND gate 106A is turned on at the time S1 of this character to thereby produce a set signal to the synchronization flip-flop 142. However, since the AND gate 136B instead of the AND gate 136A is switched through by the output signals of the counter 40, the OR gate 138 generates no clock signal for the Flip-flops 62 and 142 ahead of the time for bit 4 of the scan jump. During time S1, 6 character times later, when the beam starts to write the first character of the next line, i.e. line 2, it creates the delay 146 a set signal for the Vi & eo flip-flop 62. A clock signal however, on line 152 for flip-flop 62

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generated no sooner than three bit times later. As a video ad during the first two bits of the first If the scan jump is not enabled for the character, these bits are not visible. This result is in 3B. At the end of line 2 appears again a signal on line 140 at time S1, the character 49 · However, since neither the synchronization flip-flop, nor the video flip-flop is keyed up to the time of bit 4 of the scan jump is a video display for three Bit times possible, which results in a possible display of the first two bits of the 4-9th character. During this Condition for line 2 in Fig. 3B does not occur, it occurs for line 3 -

It is now assumed that either (1) at the end of the first frame the number of those buffered in memory 10 Character is sufficient to produce an output on line 94D, or that (2) at the end of the second frame the number of characters buffered has increased to a point where the shift control circuit 92 an output on line 940 is generated. In each In this case, the counter 40 continues to count over a complete cycle, creating a carry signal on the line 96 appears and it is counted again to the counter reading of 1. The carry signal on line 96 causes the further-counting of the sample jump counter 38 to a count of 2, whereby the AND gate 106B during the next Li time is switched through, so that a Signal on line 108 appears. The switching through of the AND gate 106B means that a full scan jump of character 49 is complete before the signal appears on line 140 to set flip-flop 142. Since the bit counter 40 is also counted to 1, the AND gate 136B is not switched through until the bit 4 time occurs to a clocking output signal on the

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Line "152 to generate. The line return therefore begins not before sample jump 2 and bit 4 of character 49. Because delay 146 lasts for six full character times occurs, the walking beam is not before the scan jump 2 of the first character of line 2 ready to write characters on a new line and a set input signal to the video flip-flop 62. The character generator 58 however, still operates in synchronism with clock wave 64. This is the generation of the output signals for the first Scan jump of the first character terminated at this time and bits for the second scan jump of the character are added generated. At time B4 of the second sampling jump of the first character, a clock signal finally appears on the Line 152, which sets the flip-flop 62 and thus the Display enables'. Fig. 3C shows the appearance of the first Character as a result of the previously described mode of operation.

The same sequence of events as described above appears at the end of line 2 and at the beginning of line 3 At the end of line 3, the first scan jump of the character 49 and the first three bits of the second scan jump this character is generated before the return line occurs and the video flip-flop 62 is reset. In this way, as shown in Fig. 3C, the 49th character is partially displayed.

As described in the main patent, there is one line between the last migratory line and the first non-migratory line Line required to re-establish suitable synchronization between the character generator and the display.

From the foregoing it can be seen that a relatively simple technique for generating a scrolling display on your Screen of a display device, such as. B. a cathode

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ray tube, this display being in Increments of a selected fraction of a scan jump and move at a speed that is a function of some specific criteria, such as E.g. the number of characters waiting to be displayed and buffered in a buffer memory. Although with the preferred Embodiment of the invention the display is moved in increments of a third of the scan jump, the display can of course also be moved in increments as small as one bit. Although a Certain circuit arrangement for carrying out the new method has been specified and described, of course Components and assemblies of the same type can also be used. The invention is therefore not limited to these details Rather, all features of the description can be used individually or in any combination Combination be essential to the invention.

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Claims (10)

Claims Method for the cyclically renewed display of information signs on a display device generating multiple scan jumps for a display line, by selective Indication of the visible state of M-bits in the case of N-sample jumps for each character, with the display moving in fractions of the scanning jump increments U.S. Patent 2,226,312, characterized in that the number of fractions of the scan jump increments is determined and displayed, by which the display has to move on, that a first counter as a function of the displayed Number, is counted further, with each increment of the first counter being a specific partial scanning jump increment the display corresponds to the fact that a second counter continues to count depending on an overflow of the first counter where each increment of the second counter corresponds to a complete sample jump increment that consecutive Characters for display on the display device are supplied and that the output signals of the first and second counter can be used to control both the sample jump and the bit of that sample jump at which the display of the first of the consecutive characters begins. 2. The method according to claim 1, characterized net that as a display device a cathode ray tube is used with a write beam that the beam return is started at the end of each display line, that during a predetermined time interval after the beginning of each beam return, the beam is scanned dark and that the scan jump as well as the respective 509807/0760 Bit of this scan jump is controlled, at which beam return begins. 3. Circuit arrangement for cyclically renewed displays of information characters on a display device generating several scanning jumps for a display line by selectively changing the visible state of M bits at W sample jumps for each character, the The display moves in fractions of the scanning jump increments, in particular for carrying out the method according to claim 1 or 2, characterized by a first counter (40), each increment of which is one certain partial sample jump increment of the display, by a second counter (38), each of which Increment corresponds to a complete sampling jump increment and which is connected to the first counter in such a way that that it can be further counted by a carry signal of the first counter, by a first circuit (72,90) for Determining and displaying the number of predetermined partial scan jump increments, around which the ad has to move on, by one on the one specified by the first circuit Number of responding and the first counter by this number further counting second circuit (92), by a successive Characters for the display (63) feeding third circuit (58) and by a on the output signals of the fourth circuit (136), responsive to first and second counters, for controlling both the scan jump and the Bit of this scan jump, in which the first of the consecutive characters can be displayed. 4-. Circuit arrangement according to Claim 3, characterized in that several lines of information can be displayed on the display device (63), 509807/0760 however, only one or more selected rows the display wander while the remaining characters stand still, and that the fourth circuit (156) comprises circuit parts (136A, 136B, 136C) which the output signals the counter (38,40) to control the scan jump and use bits in which a display of the first character only for the moving lines of the display begins. 5 · circuit arrangement according to claim 3 »characterized in that the third circuit during every display renewal cycle of the display device (63) is effective and that the display continues to wander by the number of predetermined partial scan jumps during occurs every renewal cycle. 6. Circuit arrangement according to claim 3 »characterized · by a memory (10) for storing the characters successively given to the display, the also serves as a buffer memory for characters waiting to be displayed, and that the first circuit (72, 90) has a first Circuit part (72) for determining the number of those waiting to be displayed and stored in the buffer memory Character and a second circuit part (90) which is responsive to the specific number of characters to there after to determine the number of predetermined partial sampling jumps. 7. Circuit arrangement according to one of claims 3 to 6, characterized in that one to be displayed Line of characters can have characters of different types, with the characters of one type on one Part of a line below the characters of the other type are to be displayed, and that one is to be displayed in the memory (10) Line in consecutive address positions 509807/0760 can be stored, the characters of one type being one have predetermined identifier stored in the memory that one when reading out the memory effective further circuit (44 ·) is provided with which the type of character after the input of the stored identifier can be seen, and that a circuit (52,68) using the identification of the character type for controlling the character position is provided on the display device (63). 8. Circuit arrangement according to claim 7, characterized in that the memory (10) for each line containing characters of different types must be read out twice and that the circuit (52,68) for controlling the character position, a first circuit part for forwarding characters of one type to the display device (63) during the first readout for displaying on a given line and a second circuit part to pass on characters of the other type to the display device during the second readout to display the Character by a fraction of a line below the characters of the first type. 9. Circuit arrangement according to one of claims 3 to 8, characterized in that the display device (30) a cathode ray tube with a write beam is that a fifth circuit (14-2) is provided is effective at the end of each display line to initiate the retrace of the write beam is that a sixth circuit (62) for blanking the rubbing beam for a predetermined period of time the initiation of the beam return is provided as a function of the fifth circuit and that with the fourth Circuit (136) both the sampling jump and the bit of this sampling jump at which the fifth Circuit is actuatable. 509807/0760 10. Circuit arrangement according to one of claims 3 to 9 » characterized in that the display moves by a third of the scanning jump increment and the first Counter (40) is a three-stage counter. 5 09807/0760