DE2162095A1 - Multiple operation counter - Google Patents

Description

The invention relates to a multi-mode counter and number storage device using number change signals, to change the value of a stored number «,

Multi-mode counters are known. A device which can use number increment signals and number decrement signals to change the value of a stored number, which may have either positive or negative polarity, must be designed to operate in two modes. This means that a number increment signal or a signal that increases the actual value of the stored number must increase the size or the absolute value of the stored number if the stored number has a positive polarity, but that it must decrease the size of the stored number, if this number has a negative polarity _β on similar; Way must be a number decrement signal or a signal that decreases the actual value of the stored number, the

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Decrease the size of the number if the stored number has a positive polarity, and increase the size of the number if the stored number has a negative polarity, _etc.

Conventional multimode counters have a storage register, means for transferring the number change signals to the storage register and means for switching the mode of the counter from one mode to the other on _o The storage register is constructed so that it produces an output of the value of the stored number When the value of the stored number equals zero, the storage register provides an output which enables the mode switch to respond to the next number change signal received from the counter and to change the mode of operation of the device accordingly . If the next received number change signal is an incremental signal, the stored number has positive polarity and the mode determination device provides an output which causes the counter to operate in a first mode to change the numbers with positive polarity «In a similar manner has, if the next number change signal received is a decrement signal, the stored number has a negative polarity and the mode determining means provides an output which causes the counter to operate in a second mode for changing numbers with negative polarity

When laying out the meter and the memory, it is 209827/0939

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It is desirable to maximize the speed at which the device can accept number change signals. The speed at which signals can be picked up by the means described above is limited by the fact that a first signal must pass to the storage register that the value of the number stored in the storage register must be changed in response to this recorded number change signal, that the storage register must generate an output which indicates the value of the stored number, and that this output must pass through ^{to the operating mode TJmsGhalteinrich 1 -tung before} a second number change signal can be received by the counter and number storage device. If signals are picked up at a high rate, the mode determiner would be unwilling to respond to a signal picked up by the counter immediately after the number change signal which zeros the value of the stored number so that an error would occur.

In contrast, the present invention creates a Counter and number storage device capable of receiving number change signals in a faster sequence than conventional ones Counter, because it is designed to generate a signal which the mode determiner is capable of displaced to switch the mode of operation at a time when It is known that the stored number has a value equal to zero will have; but before their Uullwert actually set is * In addition to the operating mode determination device,

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the device a number storage device, a device for receiving number change signals and transmitting these signals to the number storage device and a device for generating a counting direction signal which indicates whether a cumulative change signal is in the transmission to the number storage device will cause an increase or decrease in the size of the stored number »

The number storage device has a gate

λ which is responsive to the value of the stored number and the counting direction signal to generate an output signal which enables the operating mode determination _{device to change the operating mode of the counter and number storage device o} The gate is further connected to receive number change signals in of transmission to the number storage device o A watchdog output is generated when the gate receives signals indicating that the size of the stored number is one and that the next number change signal to be received by the number storage device will decrease the size of the stored number "This watchdog signal is set. the operating mode determiner in a position to receive and respond to the next number change signal, which is received by the counter and number storage device" lt, which is the signal that caused the transmission of the intrusion signal to the operating mode determining device, this next number change signal, which is sent by the device

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processing is recorded, the signal which the size of the stored number will change from zero to either plus or minus one «, the mode determiner takes this Signal, responds to it and generates an output that acts to cause the device to operate in a first mode of operation to change a number with positive polarity when it does is an incremental signal, and produces an output that causes that the device operates in a second mode of operation to change a number with a negative polarity when there is a Decrement signal is c

Since a control signal is fed to the operating mode determination device before the value of the stored When the number reaches zero, number change signals can be picked up by the counter according to the invention with a faster sequence than they can be picked up by known meters. There is no need for a first number change signal received by the number storage device and the value of the stored number is changed before a second Number change signal can be received by the counter and number storage device according to the invention. It just has to it is determined that a number change signal has been received by the counter and number storage means; that causes the stored number to have the value zero; takes when the number storage device of the present input; direction picks up the signal and responds to it "

ι order to ensure that the number change _signal;

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which is received by the controlled s operating mode determination device and used to determine the operating mode of the counter to determine, in fact, the number change signal that will change the value of the stored number from zero ·. That Gate for transmitting an opening signal to the operating mode Determination device is connected so that there are number change signals which are supplied to the number storage device at a point downstream from the point at which the Operating mode determination device receives these signals <> The gate is constructed in such a way that it only emits an open signal when if the number change signal which the stored Sets the number to zero, passes this downstream point «, this causes a premature transmission of an opening signal prevents the operating mode determining device, whereby the mode determiner would be able to receive a number change signal representing the Will cause setting the stored number to zero, instead of such a number change signal that will cause that the stored number changes from zero either to plus P one or to minus one »

An exemplary embodiment of the invention will now be described with reference to the accompanying drawing, which shows a circuit diagram of the multiple operation counter and number storage device according to the invention shows"

■. - ι

The figure shows a multi-mode counter and '

Number storage device 10, which has a number memory 12, i

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a device 14- for receiving number change signals and for the transmission of these signals to the number memory 12 and means 16 to set the mode of operation of the means 10 to determine ,, The facility 10 also has a Gate and memory device 18, the counting direction signals which indicate whether each number change signal in the transmission to the number memory 12 exceeds the size of the stored Increase or decrease the number.

The number memory 12 has four conventional decade storage registers 20, 22, 24 and 26 _o Each register is constructed so that it stores a decimal number from 0 to 9 in a binary code "Each register has an input" CK "to receive signals which are hereinafter referred to as clock signals «, The value of the digit stored in a register is changed by each clock signal received by the register«, All clock signals which are transferred to the registers 20 to 26 are identical The direction , in which the stored digit is changed, is determined by a counting direction signal which is transmitted via a line 2b to the storage registers and received from these registers at the connections "MG". The gate and storage device 18 inputs either a first or a second counting direction signal, which depends on the type of the number change signal received by the device 10 and the polarity of the • stored Num more depends »A first counting direction signal causes the value of the stored digit to be increased by the next recorded clock pulse. A second count

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direction signal causes the stored by a decimal register Number will be decreased when the next clock signal is recorded «. It is a property of the decade registers to 26 that a counting direction signal must be received a predetermined time before a clock signal in order to enter the registers into the To enable them to respond properly to the clock signal »

Registers 20, 22, 24 and 26 - store progressively

k always more significant digits, d _o ho significant digit is the least stored in the register 20, which is therefore constructed so that it receives each clock pulse that is transferred to the memory 12th Signals which are transmitted to memory 12 via line 30 are brought into the correct form for recording by register 20 by an inverter 32. The registers 22, 24 and 26 do not receive every clock pulse transmitted to the memory because they store higher significant digits., AND gates 34, 36 and 38 control the transmission of a clock signal to these registers. Each of these AND gates transmits a signal to its associated decade register only when a clock signal and signals are received from the "U / D" terminals of each register memory of a less significant digit.

Each register has a gate which is responsive to the value of the stored digit and the counting direction signals, to control the transmission of signals from the "U / D" port «An output signal is taken from the" U / D "port

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of a register is only output if the digit 9 is stored in this register and a counting direction signal is received which causes the next clock signal to increase the value of the stored number, and if the digit O is stored in this register and a counting direction signal is received , which causes the 'next clock signal to decrease the value of the stored number _o

A gate, for example gate 36, which controls the transfer of clock signals to register 24, transfers a clock pulse to the register only when a clock signal and output signals from the "U / D" terminal of the register 20 and 22 are received «This will ensure that a clock signal only the corresponding. digits of a stored Number Changed Assume, for example, that the size of the stored number is 2798, with the digits 2, 7, 9 and 8 are stored in registers 26, 24, 22 and 20, respectively. When receiving a counting direction signal, which acts in the sense, that the size of the stored number is increased, and a Clock signal would only change the digit in register 20 and therefore change the size of the stored number to 2799 »Die Recording of a further counting direction signal, which acts in the sense that the size of the stored number is increased cause registers 20 and 22 to emit output signals from their "U / D" connections and to activate gates 34 and 36, respectively, so that the next clock signal would change the digits stored in registers 20, 22 and 24 so that the stored Number results in a size of 2800, if the stored

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. -assured number would have and the size of 1901, a ZählrichtungssigViaf ^s would receive that acts in the sense that the size of the ^ e * stored number is reduced, would the next clock signal only-the change in a similar fashion value of the digit in the register 20 so that the number stored is 1900. However, another signal acting to decrease the magnitude would cause registers 20 and 22 to provide outputs from their "U / D" terminals to gates 34 and 36 so that the next clock signal would be the would change the digits stored in registers 20, 22 and 24 so that the stored number is 1899 ο "

In addition to qualification sheets 34 to 38 are the output signals from the "U / B" terminals of the decimal register 22, 24 and 26 are still transmitted via lines 42, 44 and 46 'to a gate 40, the binary signals that are stored in the register 20 stored digits are sent to a "1" -Detek- " transmitted gate 50, which is a known gate circuit that responds to the binary code of the stored digit and is so executed is that they have an output on line 48 only! then outputs when the digit stored in the register 20 had a size equal to one. The gate 40 therefore receives signals over the lines 42, 44, 46 and 48 when the size of the j stored number is equal to one and a counting direction signal I has been received by the storage registers 20, 22, 24 and 26, which instructs these registers, the size of the stored Number to be decreased for the next recorded clock signal.

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set. In addition, a line 56 connects the gate 40 to the upstream side 58 of a delay device 88, while a line 54 connects the gate 40 to the downstream side of the delay device 88 «, the gate 40 emits an output signal via line 52 only when signals received on lines 42, 44, 46, 48 and 54, but no signal is received on line 56, by the fact that a signal on line 54 and no signal on line 56 is received, it is indicated that a clock signal is in the transfer to. the decimal memory register and that it at a predetermined point 58 on its way to these registers happened. The gate 40 therefore emits an output signal when it is established that a clock signal is in the transmission to the memory registers 20 to 26, which means that the size of the stored number will be zero, but before the stored number actually takes on the value zero.

The output signal of the gate 40 is transmitted to a flip-flop 60, which also has a clock signal via a line 62 from the downstream side of the delay device 88 picks up. The flip-flop 60 emits an output signal, which enables the operating mode determination device 16 to the number change signals picked up by the device 10 address and change the operating mode of the facility if this is OK.

It should be noted that gate 40 is also 209827/0938

could emit an output signal over the line 52 if the stored number has a size of 9991 and a counting direction signal is received from the registers 20 to 26, which acts in the direction that the size of the stored Fummer is increased by the next clock signal «, but since this value is at the outermost limit of the counting range, it can be used as illegal state to be considered and ignored <, For the It would be obvious to one skilled in the art to design counter registers using the "U / D" terminals of the registers shown

^ should be replaced by two output ports, the first for the delivery of signals that identify the gates that the Control the transmission of clock signals to the registers with higher significant digits, and a second one for the delivery of output signals to the gate 40 is used »An output signal would from This second connection only transmitted if the size of the stored digit is equal to one and a counting direction signal is recorded, which acts in the direction that the size of the stored digit by the next recorded clock signal is reduced »This modified version would hence the transmission of an erroneous signal from the gate Exclude 40 if the size of the stored number reaches 9991. However, this would only reduce the range of the counter extended to 9999 Because this enlargement of the area is so small the decade storage registers shown are used in the preferred embodiment of the invention because they are commercially available and can be obtained at lower costs than the modified registers described,

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The mode determining means 16 takes Number change signals from lines 64 and 66 of the recording and transmission device H and speaks to this Signals when receiving a suitable activation signal from the flip-flop 60 on. As described above, a signal transmitted to the mode determining means 16, which enables this means to respond to the first number change signal to address received by the device 10 after it receives a number change signal which causes that the stored number has the value zero »This Signal following the zeroing signal causes the value of the stored number to be either magnitude plus assumes one or minus one * If it is an incremental signal, which of the stored number will give a positive polarity is recorded by the mode determiner this signal in that it is an output signal to the Gate 18 outputs which controls the device 10 so that si'e works with positive polarity in a first mode of operation for changing a grief. When the number change signal, that follows the zero setting signal is a decrement signal, which therefore gives the stored number a negative one Gives polarity, the mode determining device 16 gives an output to gate 18 which causes the Einp direction 10 works in a second mode to change a number with negative polarity «. .

To set operation in the correct operating mode, generate AND gates 68 not only when receiving a j

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Number change signal and a control signal from the - '" Flip-flop 60 * one output The AND gates 68 give a * high. Output on line 70 and a low output via the line 72 when receiving a signal from the, ■ Flip-flop 60 and an incremental signal from «You give a low Output on line 70 and a high output on line 72 upon receipt of a signal from the. Flip-flop 60 and a decrement signal from "The outputs of the AND gates 68 are transferred to a pull-forward flip-flop 74" This flip-flop gives a high output signal via line 76 and a low output signal via line 78 Absorption of a high output signal via line 60. These output signals continue to exist on lines 76 and 78 until a high signal is received on line 72 and a low signal on line 70, whereupon it emits a low output on line 76 and a high output on line 78 »This initial state is retained by the flip-flop 74 until further signals are received that switch its output state *

The signals transmitted over lines 76 and 78 determine the type of counting direction signal generated by gate 18. The gate 18 is constructed so that it a first counting direction signal indicating an increase in the size of the stored number causes, and a second counting direction signal which causes a reduction in the size of the stored number. A special output signal generated by the gate 18 is provided by the number change signals and

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Counting direction signals "determined, which are received by the gate 18 * The gate 18 stores recorded signals, generates an output signal determined by the recorded signals and outputs this output signal until it receives either a subsequent counting direction signal or a subsequent number change signal which indicates a change When gate 18 receives a high signal on line 76, there is a first count direction signal for each received increment signal and a second count direction signal for each received decrement signal. A high signal received on line 76 therefore causes That the gate 18 was operating in a first mode of changing the size of a number with positive polarity. When the gate 18 receives a high signal on line 78, due to its design, it generates a second count direction signal for each incremental signal received and a First counting direction signal for each recorded decrement signal "A high signal transmitted via line 78 therefore causes the gate to operate in a second operating mode for changing the size of a number with negative polarity"

Increment signals and decrement signals are from the Counting and number storage device 10 via lines 64 or «, 66 recorded. These signals are transmitted through the transmission facility 14, which generates a clock signal for each recorded increment and decrement signal «The recording and Transmission device 14 has delay devices 80 and S2 for receiving increment signals or * decrement signals

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len on ο These delay devices delay the transmission of the number change signals to the gate 16 to a sufficient extent so that the operating mode determining means 16 Has time to record each number change signal and the operating mode of the device 10 in the appropriate case to change before the number change signal indicating a shift of the operating mode, is received by the gate 18 »The delay devices 80 and 82 therefore prevent generation an erroneous counting direction indication signal for the number change signal, which causes the device 10 of one mode of operation is transferred to another »The signals from the delay devices 80 and 82 are sent to an OR gate 84 transferred. The OR gate 84 gives an output signal when receiving a signal from either the delay device 80 or the delay device 82 from “The output signals of the OR gate 84 are all identical and are hereinafter referred to as clock signals «Das for an incremental signal generated clock signal is indistinguishable from the one generated for a decrement signal »

The clock signals are transmitted from the OR gate 84 to the delay devices 86 and 88. In their combination these delay devices delay the transmission of a clock signal so that the storage registers 20 to 26 are sufficient Have time to pick up a counting direction signal belonging to the clock signal that has just been delayed and to respond to it, so that the clock signal the size of the stored number in the correct direction when receiving the delayed clock signal

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The delay devices 86 and 88 also delay the transmission of a clock signal to a sufficient extent so that the gate 40 sends a clock signal over the line 56 and signals from the registers 20 to 26, which indicate the state that the memory registers essentially when the clock signal was received will have at the same time. This ensures that no clock signal except the signal which actually brings the stored number to the value one satisfies the gate and will cause the transmission of an opening signal to the operating mode determining device 16 o

To prevent a long number change signal from generating an up control signal and then taking itself the next following number change signal into the mode determining means gates, it must be determined that the zero causing clock signal passed the point is, at which the operating mode determination device 16 receives the number change signals receives before an on control signal is transmitted to the operating mode determiner «The gate 40 therefore only emits an output signal via line 52 when when a clock signal is received over the line 54, the daa, Gate 40 connects to the downstream side of the delay device 88, and if no signal over the line 56 which connects the gate 40 to the upstream side of the delay device 88. The delay device 88 separates the leading edge and the trailing edge of one: Clock signal, so that from the gate 40 via the line 56 a Signal is received for a sufficient period of time while

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the no signal is picked up on the line 54, so that the ^ Gate 40 can respond to this condition. \ '? ■

During operation, the counter and number storage device 10 receives increment signals and decrement signals via lines 64 and 66, respectively. The recording and transmission device 40 generates an identical clock signal for each recorded number change signal _o Each number change signal is transmitted to the gate 18, which generates a counting direction signal according to the type of number change signal and the polarity of the stored number «A counting direction signal determines whether the clock signal assigned to it the size of the stored number increases or decreases »Both the counting direction signal and the associated clock signal are transmitted to the number memory 12. The clock signal is delayed in the transmission in order to give the number memory 12 enough time to receive the counting direction signal and respond to it, so that the size of the stored number will be changed by the clock signal in the right direction *

The gate 40 emits an output signal when it is determined that the stored number has a size equal to one and a clock signal is in the transmission to the storage registers 20 to 26 of the number memory 12, which sets the stored number to one. In other words, the storage registers 20 to 26 generate via the lines 42 to 48 ^: Output signals for the gate 40 if the size of the stored number is equal to one and if a counting direction signal

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is received, which causes the register to increase the size of the stored Decrease number when recording the next clock signal. The gate 40 also receives clock signals that lead to the Number memory 12 are transmitted »The transmission of clock signals to gate 40 is delayed long enough for that to be received next from storage registers 20-26 Clock signal from gate 40 is received over line 54 at substantially the same time that gate 40 also receives signals that indicate the size of the stored number and the direction in which the size is next recorded clock signal will be changed. Gate 40 provides an output on line 52 when there are signals is picked up via lines 42 to 48 and 54 and no signal is received via line 56o

The clock signal, which brings the stored number to the value one, controls the gate 40 in such a way that an output signal is output, which enables the operating mode determination device 16 to proceed to the next, from the device 10 address the recorded number change signal »This next signal is the signal that changes the value of the stored number from Zero will change to either plus one or minus one o This signal therefore determines the polarity of the stored number and the operating mode of the device 10. In order to bring about a change in the operating mode, the output signal of the gate 40 transmitted to the flip-flop 60, which sends a control signal to the AND gate 68 when receiving this signal and a clock signal via line 62 delivers. The AND gates 68 determine in

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Cooperation with the flip-flop 74 - the mode of operation of the device 1Oo The AND gates 68 only emit an output when they receive both a number change signal and a control signal from the flip-flop 60 _o Number change signals can therefore from the device 10 are picked up at a rate selected so that an up signal generated from a number change signal is picked up by the AND gates 6ö at substantially the same time that the gates pick up the next number change signal.

The counter and number storage device can therefore number change signals in a faster order than record known facilities because a first number change signal are not recorded in memory registers 20-26 and have changed the size of the stored number must be recorded before the second number by the counter device can be, as is the case with the known devices. "A first signal only needs to pass point 58 before a second number change signal can be received by the counter and number storage device 10, wherein then no error can occur with the sign.

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Claims (2)

2162090 ! Patent claims s '\ oj Method for determining the correct counter mode of operation of a multi-mode counter which uses number increment signals and number decrement signals for changing a stored number of a "certain polarity as a function of number change signals, characterized in that the number change signals are transmitted in a sequence to a number memory which has the The value of the stored number changes depending on the number change signals received, that signals are generated which indicate the size of the stored number, that a counting direction signal is generated for each number change signal in the transmission to the memory, which indicates whether the number change signal is the size of the stored number will increase or decrease that the generation of a mode designation signal is initiated when the size of the stored number is equal to one and a number change signal is in the transmission to the memory, i as will bring the size of the stored number to zero, and that the mode designating signal is generated in accordance with the number change signal immediately following the number change signal which will set the value of the stored number to Hull, the mode designating signal causing the counting in a first mode for changing a number with positive polarity when the following signal is an incremental signal, and counting is carried out in a second mode for changing a number with negative polarity when the following signal is a decrement signal, 20982 7/093 8 2. Procedure according to. Claim 1, characterized in that that the generation of the mode designation signal at the time is initiated when it is determined that the stored number will have a value equal to RuIl, and before the stored number Number actually, takes the value zero " 3 »Multiple operation counter and number storage facility for carrying out the method according to claim. 1 or 2, the number change signals for changing the value of a stored cherten number used and a number memory with a device for generating size signals that the size of the stored Display number, means for transmitting the number change signals to the number memory and means for generating a counting direction signal indicating whether a number change signal is in the transmission to the Number memory causes the size of the stored number to be increased or decreased, indicated by a Trigger device (50, 4-0, 60, 16, 13), which depends on the size of the stored number and on signals in the transmission to the Number memory (12) responds to initiate a change in the mode of operation of the device when receiving signals that indicate that the stored number has a size equal to one, and that a signal that the stored number on a Will bring value equal to zero, in the transmission to the number memory (12), wherein the triggering device is a mode determining device (16) for switching the operating mode of the device between a first operating mode for Change of numbers with positive polarity and a second 2 09827/0938 Operating mode for changing numbers with a negative polarity una has a control device (40-60) which on the count direction signal and the size signal are responsive to a To generate an output signal (52) which enables the operating mode determining means (16) to determine the operating mode of the device to change ο 4. Device according to claim 3 »characterized in that the operating mode determining device (16) is a group of AND gates (68), each with an input to the output of the on st your devices (40, 60), through a second input with a conductor (64, 66), the number change signals transmits, and through their outputs (70, 72) are connected to a sign flip-flop (74) « 5 ο device according to claim 4, characterized in that that the outputs (76, 78) of the preferential flip-flop (74) are connected to a gate and memory device (18), which are also connected to the conductors (64, 66) through other inputs is connected, which transmit the number change signals through delay devices (80, 82), and that the output (28) of the Gate and storage device (18) a counting direction signal for the storage registers (20 - 26) of the number memory (12) leads. 6. Device according to one of claims 3 to 5, characterized in that the control device (40, 60) a gate (40) which is connected to the u / D connections (42, 44, 209827/0938 ■ - 24-216209S 46) of storage registers (22, 24, 26) of the number memory (12) except for the storage register (20), which belongs to the one, with a ""! " is connected to the input (58, 56) and the output (54-) of a delay device (88) which is arranged on the conductors (64, 66) transmitting the number change signals. 7. Device according to claim 3 and 6, characterized in that | f indicates that the output of the gate (4-.0) at (52) with a Input of the operating mode determination device (16) through a. Flip-flop (60) is connected, which through a second input (62) to the input of the number change signals transmitted Conductor (64, 66) is connected. 8. Device according to one of claims 4 to 7, characterized in that the conductors (64, 66) which the number change signals transmitted to the number memory (12) by a series connection of a first delay device (80, 82), an OR gate (84), a second delay device (86) and a third delay device (88) is connected ο 9. Device according to claim 6 and b, characterized in that that the delay devices are designed so that when a first number change signal is on the downstream of the delay devices, a second number change signal is received by the device. 209827/0938 can be taken 2 0 9 8 2 7/0938 Blank page