CN112787660B - Up-down counting circuit and counter - Google Patents
Up-down counting circuit and counter Download PDFInfo
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- CN112787660B CN112787660B CN202011623452.7A CN202011623452A CN112787660B CN 112787660 B CN112787660 B CN 112787660B CN 202011623452 A CN202011623452 A CN 202011623452A CN 112787660 B CN112787660 B CN 112787660B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
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Abstract
The invention provides a positive and negative counting circuit and a counter, wherein the positive and negative counting circuit comprises a first signal processing circuit, a second signal processing circuit and a plurality of trigger circuits, the first signal processing circuit is used for receiving a positive counting control signal or a negative counting control signal and outputting a corresponding positive counting trigger signal and a corresponding negative counting trigger signal, the second signal processing circuit is used for providing clock signals for the trigger circuits, the trigger circuits are used for switching output levels in the positive direction or the negative direction according to the clock signals and the corresponding trigger signals, and the positive counting and the negative counting can be completed only by setting one set of counting circuits, so that the circuit structure and the design cost are simplified.
Description
Technical Field
The invention belongs to the technical field of counters, and particularly relates to a positive and negative counting circuit and a counter.
Background
The counting circuit or counter is applied to various occasions, in a general IC circuit, the single realization of the up-counting or down-counting can be realized by using a D trigger or a T trigger through simple connection, but if the up-counting and the down-counting are required to be switched seamlessly, two sets of circuits or other circuit structures such as a signal detection circuit are required to be designed, the circuit structure is complex, and the cost is increased.
Therefore, the conventional technical scheme has the problems of complex circuit structure and high cost.
Disclosure of Invention
The invention aims to provide a positive and negative counting circuit, which aims to solve the problems of complex circuit structure and high cost of the traditional counting circuit.
The first aspect of the embodiment of the invention provides a positive and negative counting circuit, which comprises a first signal processing circuit, a second signal processing circuit and a plurality of trigger circuits, wherein the trigger circuits comprise first to N trigger circuits, and the output ends of the first to N trigger circuits are respectively from zero to N-1 bits;
the first signal processing circuit is electrically connected with the second trigger circuit to the Nth trigger circuit respectively, and the second signal processing circuit is electrically connected with each trigger circuit respectively;
the first signal processing circuit is used for converting the received up-counting control signal and the received down-counting control signal into up-counting trigger signals and down-counting trigger signals respectively and outputting the up-counting trigger signals and the down-counting trigger signals to the second trigger circuit to the Nth trigger circuit, wherein the up-counting control signal and the down-counting control signal are both in low level and effective;
The second signal processing circuit is configured to convert the up-count control signal and the down-count control signal into first clock signals and output the first clock signals to each of the flip-flop circuits;
the first trigger circuit is used for circularly outputting a high-low level signal when receiving the first clock signal;
the second to nth trigger circuits are configured to output N-1 corresponding inverted high-low level signals according to the first clock signal, the up-count trigger signal, and the high-low level signals output by the previous plurality of trigger circuits, where the N-1 corresponding inverted high-low level signals and the high-low level signals output by the first trigger circuit correspond to N-bit up-count binary numbers; and
and outputting N-1 corresponding inverted high-low level signals according to the first clock signal, the countdown trigger signal and the high-low level signals output by the first trigger circuits, wherein the N-1 corresponding inverted high-low level signals and the high-low level signals output by the first trigger circuits correspond to N-bit countdown binary values.
In one embodiment, the up-down counting circuit further comprises a reset circuit and a clock circuit;
The reset circuit is used for outputting a reset signal to control the first signal processing circuit, the second signal processing circuit and the plurality of trigger circuits to be powered on and reset;
the clock circuit is used for outputting a second clock signal to the first signal processing circuit, the second signal processing circuit and the plurality of trigger circuits.
In one embodiment, the first signal processing circuit includes a pulse signal conversion circuit and a trigger signal conversion circuit;
the pulse signal conversion circuit is connected with the trigger signal conversion circuit;
the pulse signal conversion circuit is used for converting the up-counting control signal and the down-counting control signal into an up-counting pulse signal and a down-counting pulse signal respectively and outputting the up-counting pulse signal and the down-counting pulse signal;
the trigger signal conversion circuit is used for converting and outputting the up-count trigger signal when the up-count pulse signal is received and switching and outputting the down-count trigger signal when the down-count pulse signal is received.
In one embodiment, the pulse signal conversion circuit includes a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a first nor gate, a second nor gate, a first D flip-flop, and a second D flip-flop;
The input end of the first NOT gate is used for inputting the positive count control signal, the output end of the first NOT gate, the input end of the second NOT gate and the trigger signal end of the first NOR gate are connected with each other, the input end of the third NOT gate and the positive clock signal end of the first NOR gate are commonly connected and used for receiving the second clock signal, the output end of the third NOT gate is connected with the negative clock signal end of the first D trigger, the reset signal end of the first D trigger is used for receiving the reset signal, the same-phase output end of the first D trigger is connected with the first input end of the first NOR gate, the output end of the second NOT gate is connected with the second input end of the first NOR gate, and the output end of the first NOR gate is the first signal output end of the pulse signal conversion circuit;
the input end of the fourth NOT gate is used for inputting the countdown control signal, the output end of the fourth NOT gate, the input end of the fifth NOT gate and the trigger signal end of the second NOR gate are connected with each other, the input end of the sixth NOT gate and the normal phase clock signal end of the second NOR gate are commonly connected and used for receiving the second clock signal, the output end of the sixth NOT gate is connected with the reverse phase clock signal end of the second NOR gate, the reset signal end of the second D trigger is used for receiving the reset signal, the same-phase output end of the second D trigger is connected with the first input end of the second NOR gate, the output end of the fifth NOT gate is connected with the second input end of the second NOR gate, and the output end of the second NOR gate is the second signal output end of the pulse signal conversion circuit.
In one embodiment, the trigger signal conversion circuit includes a seventh not gate, an eighth not gate, a third nor gate, and a third D flip-flop;
the input end of the seventh NOT gate, the positive clock signal end of the third D trigger and the second signal output end of the pulse signal conversion circuit are connected, the output end of the seventh NOT gate is connected with the negative clock signal end of the third D trigger, the trigger signal end of the third D trigger is connected with a positive power supply, the first input end of the third NOT gate is connected with the first signal output end of the pulse signal conversion circuit, the second input end of the third NOT gate is used for receiving the reset signal, the output end of the third NOT gate is connected with the input end of the eighth NOT gate, the output end of the eighth NOT gate is connected with the reset signal end of the third D trigger, and the output end of the third D trigger is the signal output end of the trigger signal conversion circuit; or alternatively
The trigger signal conversion circuit comprises a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a third NOR gate and a third D trigger;
the input end of the seventh NOT gate, the positive clock signal end of the third D trigger and the first signal output end of the pulse signal conversion circuit are connected, the output end of the seventh NOT gate is connected with the negative clock signal end of the third D trigger, the trigger signal end of the third D trigger is connected with a positive power supply, the first input end of the third NOT gate is connected with the second signal output end of the pulse signal conversion circuit, the second input end of the third NOT gate is used for receiving the reset signal, the output end of the third NOT gate is connected with the input end of the eighth NOT gate, the output end of the eighth NOT gate is connected with the reset signal end of the third D trigger, the output end of the third D trigger is connected with the input end of the ninth NOT gate, and the output end of the ninth NOT gate is the signal output end of the trigger signal conversion circuit.
In one embodiment, the second signal processing circuit includes a tenth NOT gate and a fourth D flip-flop;
the input end of the tenth NOT gate is commonly connected with the normal phase clock signal end of the fourth D trigger and is used for receiving the second clock signal, the output end of the tenth NOT gate is connected with the reverse phase clock signal end of the fourth D trigger, the trigger signal end of the fourth D trigger is the signal input end of the second signal processing circuit, and the same-phase output end and the reverse phase output end of the fourth D trigger are the signal output end of the second signal processing circuit.
In one embodiment, the up-down counting circuit further comprises a count lock circuit electrically connected to the plurality of flip-flop circuits and the second signal processing circuit, respectively;
the count lock circuit is used for stopping outputting the up-count control signal or the down-count control signal when the up-count binary number or the down-count binary number corresponding to the high-low level signals output by the trigger circuits is counted to a set value.
In one embodiment, the count lock circuit includes a first NAND gate, a second NAND gate, a fourth NOR gate, an eleventh NAND gate, a twelfth NAND gate, a first selector, and a second selector;
The input end of the first NAND gate is connected with high-low level signals output by the trigger circuits, the output end of the first NAND gate is connected with the selection signal end of the selector, the first signal end of the first selector is connected with a positive power supply, the second signal end of the first selector is connected with the positive counting control signal, the output end of the first selector is connected with the first input end of the second NAND gate, the input end of the fourth NAND gate is connected with high-low level signals output by the trigger circuits, the output end of the fourth NAND gate is connected with the input end of the eleventh NAND gate, the output end of the eleventh NAND gate is connected with the selection signal end of the second selector, the first signal end of the second selector is connected with the positive power supply, the second signal end of the second selector is connected with the counting control signal, the output end of the second selector is connected with the second input end of the second NAND gate, and the output end of the fourth NAND gate is connected with the output end of the twelfth NAND gate.
In one embodiment, the plurality of flip-flop circuits includes a first flip-flop circuit, a second flip-flop circuit, and a third flip-flop circuit, a signal output terminal of the first flip-flop circuit is connected to a signal input terminal of the second flip-flop circuit and a signal input terminal of the third flip-flop circuit, respectively, and a signal output terminal of the second flip-flop circuit is also connected to a signal input terminal of the third flip-flop circuit.
A second aspect of an embodiment of the present invention provides a counter comprising a count-up circuit as described above.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: according to the up-down counting circuit, the first signal processing circuit is used for receiving the up-down counting control signal or the down counting control signal and outputting the corresponding up-down counting trigger signal and the corresponding down counting trigger signal, meanwhile, the second signal processing circuit is used for providing clock signals for all the trigger circuits, all the trigger circuits can switch the output level in the forward direction or the backward direction according to the clock signals and the corresponding trigger signals, and only one set of counting circuit is needed to finish up-counting and down counting, so that the circuit structure and the design cost are simplified.
Drawings
Fig. 1 is a schematic diagram of a first configuration of a back-up counting circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an exemplary circuit of the flip-flop circuit in the up-down counter circuit shown in FIG. 1;
FIG. 3 is a schematic diagram of the output waveforms of the flip-flop circuit in the up-down counter circuit shown in FIG. 2;
fig. 4 is a schematic diagram of a second structure of a back-up counting circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a third structure of a back-up counting circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an exemplary circuit of the pulse signal conversion circuit in the up-down counting circuit shown in FIG. 5;
FIG. 7 is a schematic waveform diagram of a pulse signal converting circuit in the up-down counting circuit shown in FIG. 6;
FIG. 8 is a schematic diagram of a first exemplary circuit of the trigger signal conversion circuit in the up-down counter circuit shown in FIG. 5;
FIG. 9 is a schematic diagram of a second exemplary circuit of the trigger signal conversion circuit in the up-down counter circuit shown in FIG. 5;
FIG. 10 is a schematic diagram of an exemplary circuit of a second signal processing circuit in the up-down counter circuit shown in FIG. 1;
FIG. 11 is a schematic diagram of a fourth configuration of a count-up/down circuit according to an embodiment of the present invention;
fig. 12 is a schematic circuit diagram of an example of a count lock circuit in the up-down counting circuit shown in fig. 11.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
A first aspect of an embodiment of the present invention provides a back-up counting circuit.
As shown in fig. 1, fig. 1 is a schematic diagram of a first structure of a back-up circuit provided in an embodiment of the present invention, where the back-up circuit includes a first signal processing circuit 10, a second signal processing circuit 20, and a plurality of flip-flop circuits, the plurality of flip-flop circuits includes a first flip-flop circuit 31 to an nth flip-flop circuit, and output ends of the first flip-flop circuit 31 to the nth flip-flop circuit are respectively from a zero bit to an N-1 bit;
the first signal processing circuit 10 is electrically connected with the second to nth trigger circuits 32 to 20, respectively;
a first signal processing circuit 10 for converting the received UP-count control signal UP and DOWN-count control signal DOWN into UP-count trigger signal and DOWN-count trigger signal respectively and outputting to the second trigger circuit 32 to the nth trigger circuit, wherein the UP-count control signal and the DOWN-count control signal are both active at low level;
a second signal processing circuit 20 for converting the UP-count control signal UP and the DOWN-count control signal DOWN into the first clock signals CLK1/CLK1B and outputting to each flip-flop circuit first flip-flop circuit 31 for cyclically outputting high-low level signals upon receiving the first clock signals CLK1/CLK 1B;
The second flip-flop circuits 32 to N-th flip-flop circuits are configured to output N-1 corresponding flipped high-low level signals according to the first clock signal CLK1/CLK1B, the count-up trigger signal, and the high-low level signals output from the first flip-flop circuits 31, the N-1 corresponding flipped high-low level signals and the high-low level signals output from the first flip-flop circuits 31 corresponding to N-bit count-up binary values; and
according to the first clock signal CLK1/CLK1B, the count-down trigger signal and the high-low level signals outputted from the first plurality of trigger circuits, N-1 corresponding flipped high-low level signals are outputted, and N-1 corresponding flipped high-low level signals and the high-low level signals outputted from the first trigger circuit 31 correspond to N-bit count-down binary values.
In this embodiment, the up-down counting circuit realizes binary counting, the output ends of the first flip-flop circuit 31 to the N-th flip-flop circuit are respectively the zero bit to the N-1 th bit, and up-counting or down-counting, for example, up-counting of 000 to 111, and down-counting of 111 to 000 are realized according to the control signal, wherein the corresponding clock signals are required when the flip-flop circuit counts and works, and in this embodiment, the second signal processing circuit 20 converts the received control signal into the corresponding first clock signal CLK1/CLK1B to provide the clock signals required by the work of each flip-flop circuit.
The external device, for example, a button or a touch module outputs a count-UP control signal UP or a count-DOWN control signal DOWN, and the count-UP control signal UP and the count-DOWN control signal DOWN are converted by the first signal processing circuit 10 and then output corresponding trigger signals, where the count-UP control signal UP and the count-DOWN control signal DOWN are both valid at a low level, the output end of the first trigger circuit 31 is used as a zero bit, the output level signal of the first trigger circuit is switched between a high level and a low level, and corresponds to binary numbers 1 and 0 of the zero bit, the rest trigger circuits perform count-UP according to the count-UP trigger signals, and perform count-DOWN according to the count-DOWN trigger signals, and the level signal output when each trigger circuit is initially powered UP may be at a high level or a low level.
For example, when three flip-flop circuits are included, each of the three flip-flop circuits initially has a level signal of a corresponding output of the first flip-flop circuit 31 as a high level, the corresponding binary value is 111, when a count-down trigger signal is received, the output of the first flip-flop circuit 31 is sequentially changed, while the second flip-flop circuit 32 outputs the changed level signal according to the previous timing and the output level of the first flip-flop circuit 31, the second flip-flop circuit 32 outputs the changed level signal according to the output level of the previous two flip-flop circuits or the previous flip-flop circuit, thereby realizing sequential counting between 111 to 000, and similarly, when a count-up trigger signal is received, the output of the first flip-flop circuit 31 is sequentially changed, while the second flip-flop circuit 32 outputs the changed level signal according to the previous timing and the output level of the first flip-flop circuit 31, the third flip-flop circuit 33 outputs the changed level signal according to the output level of the previous two flip-flop circuits, thereby realizing sequential counting between 000 to 111, and when a stop signal is not set, each flip-flop circuit can be counted in a single cycle direction.
The trigger circuits can be correspondingly provided with different circuits and numbers according to the counting requirement and the output change logic, and the specific structure is not limited.
In one embodiment, as shown in fig. 1, the plurality of flip-flop circuits includes a first flip-flop circuit 31, a second flip-flop circuit 32, and a third flip-flop circuit 33, and the signal output terminal of the first flip-flop circuit 31 is connected to the signal input terminal of the second flip-flop circuit 32 and the signal input terminal of the third flip-flop circuit 32, respectively, and the signal output terminal of the second flip-flop circuit 32 is also connected to the signal input terminal of the third flip-flop circuit 33.
In one embodiment, as shown in fig. 2, the first flip-flop circuit 31 includes a fifth D flip-flop ZDS1, wherein the trigger signal terminal D of the fifth D flip-flop ZDS1 is connected to the inverted phase output terminal QB thereof, while the clock signal terminal CK/CKB is connected to the first clock signal CLK1/CLK1B that is being inverted, the output level of the in-phase output terminal Q of the first flip-flop circuit 31 is cyclically switched, while the second flip-flop circuit 32 includes a sixth D flip-flop ZDS2, a third selector ZMUX3, a thirteenth inverter INV13, and a first exclusive or gate XOR1, the first exclusive or gate XOR1 is connected to the first signal terminal IO of the third selector ZMUX3, while the selection signal terminal S of the third selector ZMUX3 is connected to the trigger signal output from the first signal processing circuit 10 through the thirteenth inverter INV13, and the output level is switched according to the level state of the trigger signal, and the third flip-flop circuit 33 includes a seventh D flip-flop ZMUX3, a fourth selector ZMUX4, a sixteenth inverter ZMUX 15, a sixteenth inverter ZMUX4, a sixteenth inverter XOR 15, and a sixteenth inverter ZMUX 3.
In the positive counting mode, the trigger signal end D of the sixth D trigger ZDS2 is connected with the exclusive OR signals of SD0 and SD1, the trigger signal end D of the seventh D trigger ZDS3 is connected with the SD0 and SD1 for performing AND operation, and then the exclusive OR operation is performed with the SD2 signal, so that the counting in a single direction from 000 to 111 is realized under the condition that the initial level corresponds to the high level of 111 or corresponds to the low level of 000.
In the countdown mode, the trigger signal end D of the sixth D trigger ZDS2 is connected with the exclusive or non-signal of SD0 and SD1, the trigger signal end D of the seventh D trigger ZDS3 is connected with the non-signal of SD0 and the non-signal of SD1 for performing exclusive or operation, and then the signal is subjected to exclusive or operation with the SD2 signal to realize the counting in 111-000 directions.
As shown in fig. 3, fig. 3 shows waveforms of signals output from SD0, SD1, SD2, and SD1, and SD0 are all high-level, i.e., 111, and MODE is a changed trigger signal, including a DOWN-count trigger signal and a UP-count trigger signal, and assuming that the current MODE is the DOWN-count trigger signal and is high-level, in the DOWN-count MODE, with successive triggering of the DOWN-count signal, SD2, SD1, SD0 sequentially becomes 110, 101, 100, 011, 010, and then stops inputting the DOWN-count control signal DOWN at time t1, and changes to inputting the UP-count control signal UP, and switches to the UP-count MODE, at this time, the MODE becomes low-level, SD2, SD1, and SD0 sequentially becomes 011, 100, 101, 110, 111, and when the stop signal is set, and after the count reaches 111, the subsequent UP-count control signal UP becomes inactive at time t2, and when the DOWN-count control signal DOWN is input, the MODE becomes high-level, and the SD2, SD0 sequentially becomes 011, 100, 101, 110, 111, and then becomes inactive when the DOWN-count signal DOWN becomes active again at time t3, and reaches the DOWN-count MODE, and becomes active again when the DOWN-count signal becomes active at time t1, and becomes active at time 101, and becomes lower than 100, and becomes lower than 000.
The seamless switching between the up-counting and the down-counting is realized in this way, if the count value of other values is needed, the number of stages of the trigger circuits can be increased or decreased, and the input logic signals corresponding to the trigger signal ends of the D triggers can be changed, and different requirements correspond to different trigger circuits and different logic signals of the trigger signal ends, so that the method is not particularly limited.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: the UP-DOWN counting circuit receives the UP-DOWN counting control signal UP or DOWN counting control signal DOWN by adopting the first signal processing circuit 10 and outputs the corresponding UP-DOWN counting trigger signal and DOWN counting trigger signal, meanwhile, the second signal processing circuit 20 provides clock signals for the trigger circuits, the trigger circuits switch the output level forward or backward according to the clock signals and the corresponding trigger signals, and only one set of counting circuit is needed to complete UP-DOWN counting and DOWN counting, so that the circuit structure and design cost are simplified.
As shown in fig. 4, in one embodiment, the up-down counting circuit further includes a reset circuit 40 and a clock circuit 50;
a reset circuit 40 for outputting a reset signal POR to control the first signal processing circuit 10, the second signal processing circuit 20, and the plurality of flip-flop circuits to be reset on power;
The clock circuit 50 outputs the second clock signal CLK2 to the first signal processing circuit 10, the second signal processing circuit 20, and the plurality of flip-flop circuits.
In this embodiment, the reset circuit 40 is configured to provide a reset signal POR to enable the internal components of each flip-flop circuit to perform power-on reset, so as to re-count, and meanwhile, the clock circuit 50 provides the second clock signal CLK2 for each circuit, the second clock signal CLK2 is used as a reference clock signal, the reset circuit 40 may use a corresponding switching device and a power module, the clock circuit 50 may use a crystal oscillator unit or other circuits, and the frequency of the second clock signal CLK2 may be different values such as 100HZ, 1KHZ, etc., which are specifically set correspondingly according to the counting requirement.
As shown in fig. 5, in one embodiment, the first signal processing circuit 10 includes a pulse signal conversion circuit 11 and a trigger signal conversion circuit 12;
the pulse signal conversion circuit 11 is connected to the trigger signal conversion circuit 12;
a PULSE signal conversion circuit 11 for converting the UP-count control signal UP and the DOWN-count control signal DOWN into a UP-count PULSE signal up_pulse and a DOWN-count PULSE signal down_pulse, respectively, and outputting them;
the trigger signal conversion circuit 12 is configured to convert and output a count-UP trigger signal when a count-UP PULSE signal up_pulse is received, and to switch and output a count-DOWN trigger signal when a count-DOWN PULSE signal down_pulse is received.
In this embodiment, since the countdown control signal DOWN and the countdown control signal UP are square wave signals, as shown in fig. 7, in order to ensure that the back-end trigger circuit can receive stable trigger signals, it is necessary to perform level signal conversion through the pulse signal conversion circuit 11 and the trigger signal conversion circuit 12, and convert the square wave signals into count pulse signals and then into corresponding continuous high-low level trigger signals to the trigger circuits at the back-end, so that the trigger circuits perform countdown or countdown operations according to the trigger signals, wherein each pulse signal conversion circuit and each trigger signal conversion circuit 12 can adopt a corresponding trigger structure, and the specific structure is not limited.
As shown in fig. 6, in one embodiment, the pulse signal conversion circuit 11 includes a first NOR gate INV1, a second NOR gate INV2, a third NOR gate INV3, a fourth NOR gate INV4, a fifth NOR gate INV5, a sixth NOR gate INV6, a first NOR gate NOR1, a second NOR gate NOR2, a first D flip-flop ZDR1, and a second D flip-flop ZDR2;
the input end of the first NOT gate INV1 is used for inputting a positive count control signal UP, the output end of the first NOT gate INV1, the input end of the second NOT gate INV2 and the trigger signal end of the first D trigger ZDR1 are connected with each other, the input end of the third NOT gate INV3 and the positive clock signal end CK of the first D trigger ZDR1 are commonly connected and used for receiving a second clock signal CLK2, the output end of the third NOT gate INV3 is connected with the negative clock signal end CKB of the first D trigger ZDR1, the reset signal end R of the first D trigger ZDR1 is used for receiving a reset signal POR, the same-phase output end Q of the first D trigger ZDR1 is connected with the first input end of the first NOR gate NOR1, the output end of the second NOT gate INV2 is connected with the second input end of the first NOR gate NOR1, and the output end of the first NOR gate NOR1 is the first signal output end of the pulse signal conversion circuit 11;
The input end of the fourth not gate INV4 is used for inputting a countdown control signal DOWN, the output end of the fourth not gate INV4, the input end of the fifth not gate INV5 and the trigger signal end D of the second NOR gate ZDR2 are interconnected, the input end of the sixth not gate INV6 and the positive clock signal end CK of the second D flip-flop ZDR2 are commonly connected and used for receiving the second clock signal CLK2, the output end of the sixth not gate INV6 is connected with the negative clock signal end CKB of the second D flip-flop ZDR2, the reset signal end R of the second D flip-flop ZDR2 is used for receiving the reset signal POR, the same-phase output end Q of the second D flip-flop ZDR2 is connected with the first input end of the second NOR gate NOR2, the output end of the fifth not gate INV5 is connected with the second input end of the second NOR gate NOR2, and the output end of the second NOR gate NOR2 is the second signal output end of the pulse signal conversion circuit 11.
In this embodiment, the UP-count control signal UP is inverted and then connected to the trigger signal end D of the first D flip-flop ZDR1, the clock signal ends CK and CKB of the first D flip-flop ZDR1 are connected to the second clock signal CLK2 that is inverted, as shown in fig. 7, when the second clock signal CLK2 is a rising edge trigger, the level of the output end of the first D flip-flop ZDR1 is equal to the level of the signal at the trigger signal end at the moment, and during other time, the output end signal remains unchanged, so as to play a role in preventing false triggering or noise, and the signal generated after passing through the first D flip-flop ZDR1 is then combined with the signal with the same logic level of the UP-count control signal UP or not, so as to generate the UP-count PULSE signal up_pulse, so that the trigger signal conversion circuit 12 resets the state of the down-count mode, and switches to the UP-count mode.
Similarly, the inverse count control signal DOWN is connected to the trigger signal end of the second D flip-flop ZDR2 after being inverted, the clock signal ends CK and CKB of the second D flip-flop ZDR2 are connected to the second clock signal CLK2 with inverse phases, according to the same principle, as shown in fig. 7, when the second clock signal CLK2 is triggered by the rising edge, the level of the output end of the second D flip-flop ZDR2 is equal to the level of the signal at the trigger signal end at the moment, and in other time, the output end signal remains unchanged, so that the effect of preventing false triggering or noise can be achieved, and the signal generated after passing through the second D flip-flop ZDR2 is then combined with the signal with the same logic level of the inverse count control signal DOWN or not, so as to generate a inverse count PULSE signal down_pulse for the trigger signal conversion circuit 12 to reset the state of the positive count mode, and switch to the inverse count mode.
As shown in fig. 8, in one embodiment, the trigger signal converting circuit 12 includes a seventh non-gate INV7, an eighth non-gate INV8, a third NOR gate NOR3, and a third D flip-flop ZDR3;
the input end of the seventh NOT gate INV7, the positive phase clock signal end CK of the third D trigger ZDR3 and the second signal output end of the pulse signal conversion circuit 11 are connected, the output end of the seventh NOT gate INV7 is connected with the negative phase clock signal end CKB of the third D trigger ZDR3, the trigger signal end D of the third D trigger ZDR3 is connected with the positive power supply VDD, the first input end of the third NOT gate NOR3 is connected with the first signal output end of the pulse signal conversion circuit 11, the second input end of the third NOT gate NOR3 is used for receiving a reset signal POR, the output end of the third NOT gate NOR3 is connected with the input end of the eighth NOT gate INV8, the output end of the eighth NOT gate INV8 is connected with the reset signal end R of the third D trigger ZDR3, and the output end of the third D trigger ZDR3 is the signal output end of the trigger signal conversion circuit 12; or alternatively
As shown in fig. 9, the trigger signal conversion circuit 12 includes a seventh non-gate INV7, an eighth non-gate INV8, a ninth non-gate INV9, a third NOR gate NOR3, and a third D flip-flop ZDR3;
the input end of the seventh non-gate INV7, the positive clock signal end CK of the third D flip-flop ZDR3 and the first signal output end of the pulse signal conversion circuit 11 are connected, the output end of the seventh non-gate INV7 is connected with the negative clock signal end CKB of the third D flip-flop ZDR3, the trigger signal end D of the third D flip-flop ZDR3 is connected with the positive power supply VDD, the first input end of the third NOR gate NOR3 is connected with the second signal output end of the pulse signal conversion circuit 11, the second input end of the third NOR gate NOR3 is used for receiving the reset signal POR, the output end of the third NOR gate NOR3 is connected with the input end of the eighth non-gate INV8, the output end of the eighth non-gate INV8 is connected with the reset signal end R of the third D flip-flop ZDR3, the output end of the third D flip-flop ZDR3 is connected with the ninth non-gate INV9, and the output end of the ninth non-gate INV9 is the signal output end of the trigger signal conversion circuit 12.
In this embodiment, according to the reset state, either one of the above two structures may be selected, as shown in fig. 9, when the input end of the seventh not gate INV7, the positive clock signal end CK of the third D flip-flop ZDR3 and the first signal output end of the PULSE signal conversion circuit 11 are connected, the first input end of the third NOR gate NOR3 is connected to the second signal output end of the PULSE signal conversion circuit 11, at this time, the generated up_pulse and the inverted signal thereof are used as the clock signal of the third D flip-flop ZDR3, when the UP-count control signal UP is valid, the clock signal end thereof is at a high level, the signal output by the output end of the third D flip-flop ZDR3 is at a high level of the positive power VDD signal at the trigger signal end D, the MODE signal of the MODE is changed to a low level, that is switched to the UP-count MODE, and when the DOWN-count control signal DOWN is triggered, the generated down_pulsecontrol signal of the third D flip-flop ZDR3 is reset, and the DOWN-count signal of the DOWN signal is simultaneously switched to the high level, that is switched to the UP-count MODE, and the UP-count signal of the DOWN signal is controlled to the UP-count MODE.
As shown in fig. 8, when the input end of the seventh non-gate INV7, the positive clock signal end CK of the third D flip-flop ZDR3 and the second signal output end of the PULSE signal conversion circuit 11 are connected, the first input end of the third NOR gate NOR3 is connected to the first signal output end of the PULSE signal conversion circuit 11, at this time, the generated down_pulse and the reverse signal thereof are used as the clock signal of the third D flip-flop ZDR3, when the DOWN control signal DOWN is valid, the clock signal end thereof is at a high level, the signal output by the output end of the third D flip-flop ZDR3 is at a high level of the positive power VDD signal of the trigger signal end D, the MODE signal becomes at a high level, i.e., the DOWN control signal UP is switched to the DOWN MODE, and the generated up_pulse controls the reset of the third D flip-flop ZDR3 after the UP control signal UP is triggered, the signal output by the output end of the third D flip-flop ZDR3 is reset to a low level, i.e., enters the DOWN MODE, thereby realizing the switching between the UP and DOWN control states of the DOWN control signal UP and the DOWN control signal DOWN.
As shown in fig. 10, in one embodiment, the second signal processing circuit 20 includes a tenth non-gate INV10 and a fourth D flip-flop ZDR4;
The input end of the tenth non-gate INV10 is commonly connected with the positive clock signal end CK of the fourth D flip-flop ZDR4 and is used for receiving the second clock signal CLK2, the output end of the tenth non-gate INV10 is connected with the negative clock signal end CKB of the fourth D flip-flop ZDR4, the trigger signal end D of the fourth D flip-flop ZDR4 is the signal input end of the second signal processing circuit 20, and the in-phase output end Q and the negative phase output end QB of the fourth D flip-flop ZDR4 are the signal output ends of the second signal processing circuit 20.
In this embodiment, the UP-count control signal UP or the DOWN-count control signal DOWN is converted into the first clock signal CLK1/CLK1B with positive inversion through the fourth D flip-flop ZDR4 and the second clock signal CLK2 to each flip-flop circuit at the back end, which is the clock signal of the D flip-flop of each flip-flop circuit.
As shown in fig. 11, in order to meet different counting requirements, in one embodiment, the up-down counting circuit further includes a counting lock circuit 60, and the counting lock circuit 60 is electrically connected to the plurality of flip-flop circuits and the second signal processing circuit 20, respectively;
the count lock circuit 60 is configured to cut off outputting the UP-count control signal UP or the DOWN-count control signal DOWN when the UP-count binary value or the DOWN-count binary value corresponding to the high-low level signals output from the plurality of flip-flop circuits is counted to a set value.
In this embodiment, assuming that the flip-flop circuit includes three signals SD0, SD1, SD2 as final output signals, 000, 001, 010, … …,111 (SD 0 is low and SD2 is high) are generated by combination thereof, and counted by the count lock circuit 60, when the three signals are 111, the count lock circuit 60 stops outputting the UP-count control signal UP or the DOWN-count control signal DOWN, and when the output combination is set by the logic processing of the count lock circuit 60, the UP-count control signal UP or the DOWN-count control signal DOWN is not output, and no effect is generated on the output result, that is, the UP-count maximum value can be locked at 111, the DOWN-count minimum value can be locked at 000, and the upper and lower limits can be locked at different values by different signal combinations, which are not listed any more.
As shown in fig. 12, in one embodiment, the count lock circuit 60 includes a first NAND gate NAND1, a second NAND gate NAND2, a fourth NOR gate NOR4, an eleventh NAND gate INV11, a twelfth NAND gate INV12, a first selector ZMUX1, and a second selector ZMUX2;
The input end of the first NAND gate NAND1 is connected with high-low level signals output by a plurality of trigger circuits, the output end of the first NAND gate NAND1 is connected with a selection signal end S of a selector, a first signal end IO of the first selector ZMUX1 is connected with a positive power supply, a second signal end I1 of the first selector ZMUX1 is connected with a positive counting control signal UP, the output end of the first selector ZMUX1 is connected with a first input end of a second NAND gate NAND2, the input end of a fourth NOR gate NOR4 is connected with high-low level signals output by a plurality of trigger circuits, the output end of the fourth NOR gate NOR4 is connected with an input end of an eleventh NAND gate INV11, the output end of the eleventh NAND gate INV11 is connected with the selection signal end S of the second selector ZMUX2, the first signal end IO of the second selector ZMUX2 is connected with the positive power supply, the second signal end I1 of the second selector ZMUX2 is connected with a countdown control signal DOWN, the output end of the second selector ZMUX2 is connected with a second input end of the second NAND gate NAND2, and the output end of the second NAND gate INV 2 is connected with an output end of the twelfth gate NAND gate 12.
In this embodiment, assuming that the flip-flop circuit includes three signals SD0, SD1, SD2 as final output signals, 000, 001, 010, … …,111 (SD 0 is low and SD2 is high) are generated by combining them to count, the three signals generate UL signals by nand combination, when they are 111, UL is 0, the output signal of the first selector ZMUX1 is equal to the positive power supply VDD, which is 000, 001, … …,110, UL is 1, the output signal of the first selector ZMUX1 is the positive count control signal UP converted by the corresponding logic gate, and by such a process, when the output combination is 111, the positive count control signal UP is not passed when the positive count control signal UP is triggered again, that is, the positive count maximum value can be locked at 111.
Similarly, when the count-DOWN control signal is DOWN, and the output combination is 000, the count-DOWN control signal cannot pass through when the count-DOWN control signal is triggered again, and no effect is generated on the output result, namely, the minimum value of the count-DOWN can be locked at 000, and the upper limit and the lower limit can be locked at different values through different signal combinations, which are not listed here.
Then, the twelfth inverter INV12 combines the two signals of the two selectors, and outputs a count control signal SW, where the count control signal is one of the UP-count control signal UP, the DOWN-count control signal DOWN, and the positive power supply VDD converted by the corresponding logic gate, the count control signal SW is output to the second signal processing circuit 20 for further signal processing, when the signal received by the second signal processing circuit 20 is the UP-count control signal UP or the DOWN-count control signal DOWN converted by the corresponding logic gate, the first clock signal is converted and output to each flip-flop circuit to provide the count clock signal, and when the signal received by the second signal processing circuit 20 is the positive power supply VDD converted by the corresponding logic gate, the first clock signal is stopped, and each flip-flop circuit stops counting.
The invention also provides a counter, which comprises a positive and negative counting circuit, and the specific structure of the positive and negative counting circuit refers to the embodiment, and because the counter adopts all the technical schemes of all the embodiments, the counter at least has all the beneficial effects brought by the technical schemes of the embodiments, and the details are not repeated here.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (10)
1. The positive and negative counting circuit is characterized by comprising a first signal processing circuit, a second signal processing circuit and a plurality of trigger circuits, wherein the trigger circuits comprise a first trigger circuit, a second trigger circuit and an nth trigger circuit, the output ends of the first trigger circuit, the second trigger circuit and the nth trigger circuit are respectively in zero position, the nth bit and the (1 st) bit, the ith trigger circuit is also respectively connected with the output ends of the first trigger circuit, the ith trigger circuit and the (i-1) th trigger circuit, and i is 2, 3..N;
The first signal processing circuit is electrically connected with the second trigger circuit to the N trigger circuit respectively, and the second signal processing circuit is electrically connected with the first trigger circuit to the N trigger circuit respectively;
the first signal processing circuit is used for converting the received up-counting control signal and the received down-counting control signal into up-counting trigger signals and down-counting trigger signals respectively and outputting the up-counting trigger signals and the down-counting trigger signals to the second trigger circuit to the Nth trigger circuit, wherein the up-counting control signal and the down-counting control signal are both in low level and effective;
the second signal processing circuit is used for converting the up-count control signal and the down-count control signal into first clock signals and outputting the first clock signals to the first trigger circuit to the Nth trigger circuit;
the first trigger circuit is used for circularly outputting a high-low level signal when receiving the first clock signal;
the ith trigger circuit is configured to:
outputting a corresponding inverted high-low level signal according to the first clock signal, the up-counting trigger signal and the high-low level signals output by the first trigger circuit to the i-1 th trigger circuit, wherein N-1 corresponding inverted high-low level signals output by the second trigger circuit to the N-th trigger circuit and the high-low level signals output by the first trigger circuit correspond to N-bit up-counting binary values; and
Outputting a corresponding inverted high-low level signal according to the first clock signal, the countdown trigger signal and the high-low level signals output by the first to i-1 th trigger circuits, wherein N-1 corresponding inverted high-low level signals output by the second to N-th trigger circuits and the high-low level signals output by the first trigger circuit correspond to N-bit countdown binary values;
the first trigger circuit comprises a fifth D trigger, a trigger signal end of the fifth D trigger is connected with an anti-phase output end of the fifth D trigger, a clock signal end of the fifth D trigger is connected with a first clock signal in positive phase and in negative phase, and output levels of the same-phase output ends of the fifth D trigger are switched in a circulating mode.
2. The up-down counting circuit of claim 1, wherein the up-down counting circuit further comprises a reset circuit and a clock circuit;
the reset circuit is used for outputting a reset signal to control the first signal processing circuit, the second signal processing circuit and the plurality of trigger circuits to be powered on and reset;
the clock circuit is used for outputting a second clock signal to the first signal processing circuit, the second signal processing circuit and the plurality of trigger circuits.
3. The up-down counting circuit according to claim 2, wherein the first signal processing circuit includes a pulse signal conversion circuit and a trigger signal conversion circuit;
the pulse signal conversion circuit is connected with the trigger signal conversion circuit;
the pulse signal conversion circuit is used for converting the up-counting control signal and the down-counting control signal into an up-counting pulse signal and a down-counting pulse signal respectively and outputting the up-counting pulse signal and the down-counting pulse signal;
the trigger signal conversion circuit is used for converting and outputting the up-count trigger signal when the up-count pulse signal is received and switching and outputting the down-count trigger signal when the down-count pulse signal is received.
4. The up-down counting circuit of claim 3, wherein the pulse signal conversion circuit comprises a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a first nor gate, a second nor gate, a first D flip-flop, and a second D flip-flop;
the input end of the first NOT gate is used for inputting the positive count control signal, the output end of the first NOT gate, the input end of the second NOT gate and the trigger signal end of the first NOR gate are connected with each other, the input end of the third NOT gate and the positive clock signal end of the first NOR gate are commonly connected and used for receiving the second clock signal, the output end of the third NOT gate is connected with the negative clock signal end of the first D trigger, the reset signal end of the first D trigger is used for receiving the reset signal, the same-phase output end of the first D trigger is connected with the first input end of the first NOR gate, the output end of the second NOT gate is connected with the second input end of the first NOR gate, and the output end of the first NOR gate is the first signal output end of the pulse signal conversion circuit;
The input end of the fourth NOT gate is used for inputting the countdown control signal, the output end of the fourth NOT gate, the input end of the fifth NOT gate and the trigger signal end of the second NOR gate are connected with each other, the input end of the sixth NOT gate and the normal phase clock signal end of the second NOR gate are commonly connected and used for receiving the second clock signal, the output end of the sixth NOT gate is connected with the reverse phase clock signal end of the second NOR gate, the reset signal end of the second D trigger is used for receiving the reset signal, the same-phase output end of the second D trigger is connected with the first input end of the second NOR gate, the output end of the fifth NOT gate is connected with the second input end of the second NOR gate, and the output end of the second NOR gate is the second signal output end of the pulse signal conversion circuit.
5. The up-down counting circuit of claim 3, wherein the trigger signal conversion circuit comprises a seventh not gate, an eighth not gate, a third nor gate, and a third D flip-flop;
the input end of the seventh NOT gate, the positive clock signal end of the third D trigger and the second signal output end of the pulse signal conversion circuit are connected, the output end of the seventh NOT gate is connected with the negative clock signal end of the third D trigger, the trigger signal end of the third D trigger is connected with a positive power supply, the first input end of the third NOT gate is connected with the first signal output end of the pulse signal conversion circuit, the second input end of the third NOT gate is used for receiving the reset signal, the output end of the third NOT gate is connected with the input end of the eighth NOT gate, the output end of the eighth NOT gate is connected with the reset signal end of the third D trigger, and the output end of the third D trigger is the signal output end of the trigger signal conversion circuit; or alternatively
The trigger signal conversion circuit comprises a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a third NOR gate and a third D trigger;
the input end of the seventh NOT gate, the positive clock signal end of the third D trigger and the first signal output end of the pulse signal conversion circuit are connected, the output end of the seventh NOT gate is connected with the negative clock signal end of the third D trigger, the trigger signal end of the third D trigger is connected with a positive power supply, the first input end of the third NOT gate is connected with the second signal output end of the pulse signal conversion circuit, the second input end of the third NOT gate is used for receiving the reset signal, the output end of the third NOT gate is connected with the input end of the eighth NOT gate, the output end of the eighth NOT gate is connected with the reset signal end of the third D trigger, the output end of the third D trigger is connected with the input end of the ninth NOT gate, and the output end of the ninth NOT gate is the signal output end of the trigger signal conversion circuit.
6. The up-down counting circuit of claim 2, wherein the second signal processing circuit includes a tenth not gate and a fourth D flip-flop;
The input end of the tenth NOT gate is commonly connected with the normal phase clock signal end of the fourth D trigger and is used for receiving the second clock signal, the output end of the tenth NOT gate is connected with the reverse phase clock signal end of the fourth D trigger, the trigger signal end of the fourth D trigger is the signal input end of the second signal processing circuit, and the same-phase output end and the reverse phase output end of the fourth D trigger are the signal output end of the second signal processing circuit.
7. The up-down counting circuit of claim 6, further comprising a count lock circuit electrically connected to the plurality of flip-flop circuits and the second signal processing circuit, respectively;
the count lock circuit is used for stopping outputting the up-count control signal or the down-count control signal when the up-count binary number or the down-count binary number corresponding to the high-low level signals output by the trigger circuits is counted to a set value.
8. The up-down counting circuit of claim 7, wherein the count lock circuit comprises a first nand gate, a second nand gate, a fourth nor gate, an eleventh nor gate, a twelfth nor gate, a first selector, and a second selector;
The input end of the first NAND gate is connected with high-low level signals output by the trigger circuits, the output end of the first NAND gate is connected with the selection signal end of the selector, the first signal end of the first selector is connected with a positive power supply, the second signal end of the first selector is connected with the positive counting control signal, the output end of the first selector is connected with the first input end of the second NAND gate, the input end of the fourth NAND gate is connected with high-low level signals output by the trigger circuits, the output end of the fourth NAND gate is connected with the input end of the eleventh NAND gate, the output end of the eleventh NAND gate is connected with the selection signal end of the second selector, the first signal end of the second selector is connected with the positive power supply, the second signal end of the second selector is connected with the counting control signal, the output end of the second selector is connected with the second input end of the second NAND gate, and the output end of the fourth NAND gate is connected with the output end of the twelfth NAND gate.
9. The up-down counting circuit of claim 1, wherein the plurality of flip-flop circuits includes a first flip-flop circuit, a second flip-flop circuit, and a third flip-flop circuit, a signal output of the first flip-flop circuit being connected to a signal input of the second flip-flop circuit and a signal input of the third flip-flop circuit, respectively, a signal output of the second flip-flop circuit being further connected to a signal input of the third flip-flop circuit.
10. A counter comprising a count-up circuit according to any one of claims 1 to 9.
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