DE2101105C3 - Method for automatically selecting the information with the fewest errors from a large number of successive wireless transmissions of the same k-digit information between mutually movable interrogation and response devices - Google Patents

Description

The invention relates to a method for automatically selecting the information with the least Errors from a number of with one depending on the relative speed between each other mobile interrogators and responders selected cycle of consecutive wireless transmissions the same Ar-digit information between the interrogators and responders, each digit being the Information represented by an »H-out-of-two code character is that checked for »/!« - weighty code and with the corresponding character of the more recent information compared and switched on if the code weight and identity are correct.

Several processes are already known (German Auslegeschriften 1 293 817, 1 005 115 and 1 216 347), in which multi-digit information is composed of data blocks and disturbed data blocks can be recognized by transmitted information. In the process of the first publication every single Dalen block becomes multiple by a fixed number of repetitions transfer. A code check is provided for the received data blocks, which is carried out on arrival of the first data block with the correct code weight, the storage of this data block in a Data sink initiated. However, this method has the disadvantage that file blocks with / were correct

Code weight but incorrect content can still be saved as correct undetected.

In the process of the second-mentioned document, one-time iden »ischi: or mirror image Repetition of each data block on the basis of a code check and a comparison of the transmitted and possibly disturbed data block with its repetition determined that a disturbance is present and, in the case of a single fault, even the faulty data block is reconstructed. In the case of no longer correctable Multiple faults within the same data block, however, this error is only displayed. The security against an undetected error is indeed greater than in the case of the first-mentioned publication. However, it is not large enough because both transmissions - the data block and its repetition - are in can be disturbed in the same way, so that - as with the first-mentioned publication - definitely a Data block with correct code weight but incorrect content can be regarded as correct.

Even in the process of the last-named publication, each individual repetition is only once Data blocks and code checking as well as comparison between data block and repetition provided. The same applies to the disadvantages of this method as to the disadvantages of the method according to the second mentioned Pamphlet.

In systems for automatic wireless transmission of information that move a Information carrier, e.g. B. a railway vehicle, relate to a stationary interrogator are on Information carrier for identification of his own transponders attached to certain, the Information related features are affected. These characteristics can be used in different systems can be queried through different media. Some preferred systems have these characteristics scanned by electromagnetic waves in the microwave range emitted by interrogators. The interrogators can, for example, in railway systems next to or between the rails be arranged so that the transponders attached to the passing railroad vehicles in which information for vehicle identification is permanently set, can query.

The information transmitted by the responders however, there may be errors in the correct information, e.g. B. as a result of damage of the transponder in question or temporary interference radiation. Part of that bug can be recognized and eliminated by the fact that the Ar-digit information is transmitted cyclically so often that at least two items of information that have been completely received one after the other can be expected can. The statement can also be important if a transponder is so far out of the range of action of the interrogator has removed that the transmitted information is only incompletely received can be. This statement can be used, for example, in a connected to the interrogation device Evaluation device a command / to evaluate, if necessary Storing or printing the received information can be derived.

The object of the invention is in a Method of the type mentioned above from a large number of A-digit information that an interrogator receives wirelessly one after the other during cyclical polling and after demodulation for evaluation passes on to automatically select the information with the fewest errors. In doing so, on the one hand contain as few errors as possible in the information

■ be marked and, on the other hand, unavoidable errors will. According to the invention, this object is achieved in that for the identity and Code check recognized incorrect characters error characters are advanced, the error characters each Information can be counted and compared with the number of error characters of the older information and that with a smaller number of error characters of the more recent information this as selected information up to is cached to select information with even fewer errors. Facilities for Implementation of the method are characterized in the subclaims.

Exemplary embodiments of the invention are explained in more detail below with reference to the drawing.
F i g. 1 and 2 each show a block diagram of one

ze exemplary device for the implementation of the method according to the invention.

F i g. 3 shows the timing of the states of the blocks in FIG. 2 shown block diagram when moving a response device past the interrogation device.

With the in F i g. 1 and 2, it is assumed that the same information is transmitted cyclically several times. A / r-digit information should consist of, k = 12 characters represented in the »2-out-of-5« code.

These characters are shown in FIG. 1 from a receiving device, not shown, of the interrogation device via the line 1 on the one hand to an error character marker 10 and on the other hand to a code checking device 11 . The five code elements of each character of received information are temporarily stored in the five memory cells 100 to 104 of the error zone marker 10 and 110 to 114 of the code checking device 11 , of which the

cells assigned to each other are connected to one another by lines 115 to 119. The code checking device checks whether the code of the character "2" has weight. If the code weight is correct, the character is transmitted via line 2 to a first pre-store 20. If the code weight is incorrect, instead of the character: 100 to ! 04, an error character is stored in the cells, which has the code weight "5", for example, and is transferred to the memory cells 200 to 204 of the preliminary memory 20 . This over-

Transmission can take place, for example, when the next character arrives in the error mark marker. The preliminary memory 20 consists of k -12 memory blocks with a total of m · k 60 memory cells. Each character transmitted from the error character marker 10 to the pre- memory 20 is initially stored in the cells 200 to 204 of the first memory block and is advanced by one memory block with each subsequent character. As soon as the first character of the more recent information received in the following cycle is stored in the error character marker 10 , the older information is completely in the pre-memory 20, namely the last character in the memory cells 200 to 204 and the first character in the memory cells 205 to 209 older information is saved.

The passed on from the FehlerzcichenmLirkicrer 10 Character also arrives there via line 21; Logic element 22, the other input of which is over

5 6

the line 23 to the output of the first buffer memory. The buffer memory 40 consists of memory CR-20 connected. Blocks 401 to 412 arriving via the inputs for all twelve characters of an Infor character are briefly mation in the logic element 22. As in the pre-memories 20 and 30 are also cached and then checked for identity. here the last character of a piece of information in the In the event of identity, this character is transmitted via line 3 5 to memory block 401 and the first character in memory the second pre-store 30 switched on. Stored at block 412. Contains those in the second missing one Identity is the logic element 22 a memory 30 stored more recent information less Error sign on line 3. In each case with the error character as the older information in the temporary storage a character of the more recent information memory 40, so the comparison circuit 33 is over into the memory cells 200 to 204 the corresponding 10 the line 332 blocking potential at the negating Signs of the older information from cells 205 input of locking element 42, the other input to 209 via line 23 to the linkage via line 41 with the output of the intermediate element 22 passed on, is connected there in the memory 40 described. As a result, the Wise compared with the younger character and when transferring the younger information from the second Identity unchanged, if there is no identity as 15 pre-storage 30 in the intermediate storage 40, the older one Error characters in a second pre-storage 30 information on the line 41 to the blocking element switched. 42, but not from this via line 421.

The second pre-store 30 also consists of switched.

m · k - 60 memory cells, of which the memory contains the more recent information in the second pre-cells 300 to 304 each via lines 315 to 319 20 memory 30 the same number or more error characters than with assigned memory cells 310 to 314 one of the older information in the intermediate memory 40 , so second code checking device 31 are connected. The comparison circuit 33 switches the opening via line 3 to transmit an error character with the code potential from the setting input of the AND element 35, weight "5", or has the character off, for example. If the number of error signals counted by the comparison circuit 33 as a result of a malfunction does not exceed the required number of error signals weighted consecutively "2", the code checking device 31 sends an error signal to a comparison information after a same or smaller circuit 33. Furthermore, in the first five memory numbers than is specified by switch 36, for example cells 300 to 304 instead of the character with code error, three times the specified number, so an error character is also stored by. All k- 12-30 of the line 332 switched off the blocking potential. In addition, signs of the information switched on from the first pre-store 20 are passed on via the line 333 to switch-on pulses are hereby given after the input of the intermediate store 40. The older Infor "2" -weight codes stored in the intermediate memory 40 are checked again in the code checking device 31. Each information contained therein with the fewest error characters is then the error character triggers a 35 in the code checking device 31 via the line 41, the blocking element 42 and the off error signal. The number of triggered error output line 421 in an informational signal (not shown) are switched on in the comparison circuit 33 for each mation memory,
forwarded information is counted and stored. In the example of FIG. 2 every character gets from

Are in the second pre-store 30 k --- 12 characters of a receiving device, not shown, practice

an older piece of information is stored, at 40 the line 5 is stored in a first test memory 51 mi

Weil switch the twelve characters of a younger k + 1 - 13 memory blocks and at the same time into one

Information from the preliminary memory 20, the characters of the second test memory 53 with k - ^ memory blocks

older information from the second pre-store 30 and five memory cells each. The exit de

via line 34 one after the other to the AND gate of the last memory block 511 of the first test memory

35 transferred. When the comparison circuit 33 is at 45 51 with an input of a comparison circuit 51

the older information is linked to at most as many error signals. The other input of this comparison

has counted how the adjustable switch 36 is connected to the output of the first memory

for any information to be allowed, then there are blockes 531 of the second test memory 53 connected

they via the line 331 opening potential to the The comparison circuit 52 checks the identity of the de

Setting input of the AND element 35. This switches 50 in each case into the memory block 531 of the test memory 5. ·

then over the line 4 the characters of the older information transmitted characters of each newer information mi

mation in a buffer 40. the corresponding character of the previously in the test

When adding twelve characters to a more recent memory 51, older information transferred, that

Information in the second pre-store 30 will be characters at this point in the last store

from the comparison circuit 33 the error block 511 are again switched on. The comparison scarf

signals counted. The counting result is matched by that of the device 52 which sends an error signal to the OR gate 55

compared to older information. In the comparison if the characters being compared are not identical

circuit 33 is the error character count in a code checking device 54 is also

older information is deleted if the counter result shows each character before being stored in the second!

the younger information is smaller. The comparison 60 check memories 53 for compliance with the "2-out-of-5" code

Circuit 33 is then checked for opening via line 331. If the checked character is not »2« -weight

potential to the AND gate 35. so that the younger one gives the code checking device 54 via the Leitunj

Information in the buffer 40 transmits 541 an error signal to the OR gate 55. Odenti

can be. These processes are repeated so the validity and code checking are carried out at the same time. With one

lanpc. as in the second pre-store 30 a more recent 65 error signal is given at one or both inputs

Information with fewer Fchlerzeichencn stored the OR gate 55 from an output signal that exercises

is, as the comparison circuit 33 in each of the line 552 a first error character / counter <

older information I chlcr / cichcn has counted. forischaltel and via line 551 in the memory

block 531 of the second test memory stores an error character instead of the character received.

The output of the second test memory 53 is connected via the line 532 to the input of an AND element 56, the other input of which is connected to a bistable multivibrator 61. The output of the AND element 56 is connected via the line 561 to the input of a buffer 7 and to the input of a second code checking device 71. The intermediate store 7 also has k -12 storage cells, each with m 5 cells. The output of this buffer 7 is connected to an information memory (not shown) or to a data output device. The code checking device 71 works in the same way as the code checking device 54 and, if the code weight of the checked character is incorrect, sends an incremental signal via the line 711 to a second error character counter S. The counters 6 and 8 have the same number of a maximum of k 12 levels, the outputs of which each have an input of one further comparison circuit 62 are connected. The comparison circuit 62 is activated for a short time after each piece of information and sends a setting pulse to the flip-flop circuit 61 if the number of stages in the error counter 6 is lower than that of the counter 8.

To reset or set the error characters / counters 6 and 8, the comparison circuit 62 and the bistable flip-flop circuit 61, clock pulses generated by a device, not shown, are provided. These clock pulses / Vl / V2 and V3 closely follow one another and are repeated after the \ inspeichern each twelve digit information in the l'rufspeichcr 51 and 53rd

The pulses NX cause the bistable flip-flop 61 to switch back to the hatched position. f) ic Iinpuls: Nl switch the comparison circuit 62 effective and act on a blocking element 91. The pulses Λ / 3 switch the I ehierzeichencnzähler 6 directly and via the LND-Eq, ed 81 when the toggle switch 61 is folded into the hatched position , the l'chler / eichcn / ählcr 8 in their basic positions / inuck. Succeeded! the counter 6 when counting the I chlcr / eidicn / wischen /ν.ei clock pulses / V3 in its finding. so he gives blocking potential to the negating input of the blocking plus ⁽ > 1 and opening potential to an input of the 1 M) element 92 ^{via the line 601. If / at this point in time the / 1} AtMc I chlcr / cichcn / dialer 8 is on a Counting level which is equal to or less than the number of errors set by an error / cith switch 82. Thus, via line 921, there is also setting potential at the other input of 1 IND-Cilicdcs 92. This AND element then sends an incremental pulse to the taxpayer 9. When a given counting stage is reached, the taxpayer emits a signal via its output 901. the transfer of the information from the buffer 7 to the information memory h / w. the Dalcnausgabeetnrichtung triggers. If the counter 6 / between two clock pulses / V3 does not reach its final position. so there is no blocking potential at the blocking input of the control element 9l, and the clock pulse Nl Nlells the control element 9 back to the basic position via the blocking element.

Using the diagram in FIG. 3, the mode of operation of the exemplary embodiment η.ti Ii I ι y ^Ί nalii'i is explained below. In the lines of the Dia-)!, IMi'iH's Mini im ciii / elncM dargcMclli:

The clock pulses / Vl, Nl and / V3, the characters contained in the last memory block 511 of the first test memory 51 and in the first memory block 531 of the second test memory 53 before the code and identity test, the output signals of the OR gate 55, which is after code - and identity check in the memory block 531 respectively contained characters or the error character Z (line 531 / V), the counting stages of the first error character counter 6, the output pulses of the second code checking device 71, the counting stages of the second error character counter 8, the output pulses of the comparison circuit 62, the non-hatched Position of the flip-flop 61, the characters contained in the first memory block of the buffer 7, the output pulses of the AND element 92 and the blocking element 91 and the counting stages of the control counter 9. In the exemplary embodiments of FIG. 1 and 2 it is assumed that the received information is composed of k 12 characters: n. In the diagram of FIG. 3, on the other hand, for reasons of simplicity and the limited space, the reception of information with only four characters is assumed.

During the reception phase Λ1 and the transmission of the first information, only incorrect characters X are contained in the first test memory 51. When comparing the memory contents of the memory blocks 511 and 531 by the comparison circuit 52, weighty code characters are taken from the memory block 531 from the second character B ^ «; the comparison circuit 52, however, does not determine any identity and sends an error signal to the OR gate 55 for each character first error / .calibrate / .counter 6 advanced by four levels. The clock pulse Λ ί and Λ'2 have no effect here. In contrast, the clock pulse Λ'3 switches the counter 6

4 <> back to its basic position.

During the reception phase R1 , an incorrect character X and the characters B, C, D are successively stored in the first test memory 51. The following information A, ß, A, D contains from-M.! Iiieß! Ii.h ■ '2 "-gcv» ic! I'iigc characters, but this information is obtained at two compared places, namely at the first When the characters of these positions are compared, the OR element 55 emits output signals, as a result of which Fchler / calibrate Z are stored in the memory block 531 instead of the non-identical characters. Furthermore, the counter 6 is incremented by two levels.

When the device is switched on, the second fan symbol / counter 8 has been set to its highest counting level. After the second reception phase R1 , the counting stages of the counters 6 and 8 are compared by the comparison circuit 62 at the clock pulse NI. Since the counter 6 is at a lower counting level than the counter 8, the comparison circuit 62 switches the flip-flop 61 to the non-cliraffed position, whereby the AND gate 56 is prepared. The following clock pulse N3 switches counters 6 and 8 back to their basic positions. During the reception phase Λ3, the next item of information A, S, C, D is transmitted, the characters of which are successively stored in the first memory block 531 of the second test memory 53. The characters Z previously contained in the / wide test memory,

309 638/479

2 ΙΟΙ 105

9 10

B, Z, D of the older information (line 531 N) are removed. The information contains two faulty ones via the prepared AND element 56 in the characters A \. During the reception phase Rx-3 , intermediate memories 7 have already been switched on. Only faulty in all received characters, so that the third character C of the most recent information A, B, counter 6 is switched to its highest counting level.

C, D is not identical to the third character A 5. However, the counter 8 remains in the basic position, since the older information A, B, A, D. OR gate 55 receives an opening potential, as a result of which the more recent information signal to the counter 6, which is not advanced by one step mation / 1, B, Z, Z and is incremented. At the same time, in the second test device, the code test device 71 does not output an incremental memory 53 in block 531 instead of this symbol. In this basic position, the error character Z is stored. When switching the switch 82 permanent potenti.il to the AND gate 92, older information Z, B, Z, D in the interim the one incremental pulse to the taxpayer? The memory 7 switches the code checking device 71 at whenever the counter 8, which switches the second error character pulse N3 back to the basic position in each case, advances the second error character pulse N3 by one step. After the further counter 6 is again switched to its highest counting level, the flip-flop circuit 61 is switched on. The control counter can not be switched back to its basic position at the clock pulse N2 by the clock pulse Nl in the hatched position. In the case of the clock pulse N2 , the control circuit 62 outputs a setting pulse to the potential given by the counter 6 at the highest counting level and blocks the blocking element 91. The circuit 61, since the counting stage of the error character counter 6 in the example shown, is a total of counter 6 lower than that of the error character counter 8. four times to its highest counting stage, namely during the clock pulse N3 switches both error characters of the receiving phases Rx-3, Rx -I, Rx-I and Rx. The counters 6 and 8 return to the basic position. This puts the control counter on the fourth counting level

During the reception phase R4 , the advances. If, for example, the third stage is not connected to the output 901 at any point of the transmitted »5, the missing identification of the reception phase Rx-I from this stage causes information on the older information to be missing. Therefore, the counter 6 remains in its basic signal to advance the information from the position. When the older information buffer 7 is switched to the information A, B, Z, D, not shown, from the reception phase Λ3 from the mation memory or the data output device. Check memory 53 is determined 30 in the intermediate memory 7. The invention is not limited to the two shown, the code checking device 71, an error character Z and play. The device according to FIG. 1 can advances the counter 8 by one step. The information Z, B, previously contained in the intermediate memory 7, see the first and the second pre-memory still Z, D has been deleted in the interim, for example. further pre-storages are connected in series, their

During the reception phase RS , only 35 outputs are additionally connected to further inputs of the “2” -weight and identical characters to which the linking element 22 is connected. In the case of two additional corresponding positions in the received and borrowed pre-memories, the older information received could then be ascertained. Both counters 6 and 8 items of information from not just two but four therefore remain in their basic position. When clock successive acquisition phases verimpuls together Nl, the comparison circuit 62 not be compensated 40th

different counting levels, and the Kippschal- Furthermore, the information can also not

device 61 remains in its receive phases immediately following each other by the clock pulse N 1,

assumed hatched position. but, for example, from every third reception

The characters A, B, C, D of the information from the phase are compared with each other.

Reception phase Λ 4 were still from the second test 45 Furthermore, the control counter 9 in FIG. 2 so entered

spetcher 53 in the buffer 7 onward. poses that only when reaching a much higher level

tet. This information has the fewest errors and level than the third via its output 901

remains cached until it is emitted by a signal. In practice, the amount will be

at the output 901 of the control counter 9, the level may be dependent on how often the information

will. 5 »mations at the highest speed of the through

If the transponder moves cyclically beyond the effective area of the device.

removed from the area of the interrogation device, they can be received. On the other hand, the stage may

catch signals always weaker, so that the information is not selected too low, since then possible-

mations are initially still incorrect and later even wisely in the case of brief disruptions, the content of the

can no longer be received. The receiver 7 can already be issued,

In the initial phase Rx-4 , the transponder begins to display information with as few errors as possible

within the scope of the interrogation device has not yet been received

1 sheet of drawings

Claims (4)

Patent claims: 1. Method of automatically selecting the information with the fewest errors a number of with one depending on the relative speed between each other mobile interrogators and responders selected cycle consecutive wireless Transfers of the same Ar-digit information »o between the interrogation and answering devices, whereby each position of the information is represented by an »rt-aus-m« code character, which is weighted on »« « Code checked and compared with the corresponding character of the more recent information and corrected Code weight and identity is advanced, characterized in that for the wrong characters recognized during the identity and code check, error characters are forwarded become the error signs of any piece of information counted and compared with the number of error characters of the older information and that in the case of a smaller number of error characters in the more recent information, this is the selected one Information cached until information with even fewer errors is selected will. 2. Device for carrying out the method according to claim 1, characterized in that two series-connected pre-storage (20 and 30) and a buffer (40) connected in series are provided that the first pre-storage (20) has an error mark marker (10) with a parallel first code checking device (11) connected upstream and a first logic element (22) connected downstream, the inputs of which are led to the input and to the output of the first buffer store (20) that to the first m cells (300 to 304) of the second buffer store (30) a second code checking device (31) is connected, which sends an error signal to a comparison circuit (33) for each code error, and an AND element (35) between the output of the second preliminary memory (30) and the input of the intermediate memory (40) ) is switched, the other input of the comparison circuit (33) only then opening potential for switching on information from the second pre-store in the intermediate memory receives when the number of code errors in the information is at most equal to the number specified by a switch (36) (F i g. 1). 3. Device for performing the method according to claim 1, characterized in that a first test memory (51) with (Ar f 1) memory blocks and a second test memory (53) with Ar memory blocks are provided that the last memory block (511) of the first test memory and a comparison circuit (52) is connected to the first memory block (531) of the second test memory, which outputs an error signal to an OR element (55) if the characters in the two memory blocks (511 and 531) are not identical , which thereby and by a connected before the input of the second Prüfspeichers (53) first Codeprüfeinricht'ung (54) emits an output signal upon detection of an erroneous codes in the first Sneicherblock (531) of the / wide test memory (53) an error flag saves ^ is voShen that the output of the second test memory S and the input of a buffer (7) k switched by output variables emer zwSn ™ »** <*** ? aS- £ A lehle ^ ichen-Ser (6 and 8) compare and only with lower Level of the first error character counter (6) the Forwarding of fc-digit information from Tm second test memory (53) in the intermediate store (7) release (Fig. 2). 4 Establishment according to claim, characterized in that the first error counter £> Todisten has k counting stages and the lock mechanism of a blocking element (91) and an input of an AND-5 £ ϊθ »ί are connected to the output of the highest counting stage _; whose first input (921) receives single potential via an error sign switch (82) if the counting stage of the second error sign counter (8) is at most equal to the error sign switch (82), and that a through the output signals of the AND gate (92) incrementable control counter (9) is provided, de, after each storage of information in the. second test memory (53) via the blocking element (91, • can be switched to its basic position if the first error character counter (6) has not reached the highest number level, on the other hand, when it reaches a predetermined counting level, an output signal ₂ : to advance the in the intermediate memory (7 ) containing information in an information memory or a data output device emits