DE2101105A1 - Method for automatically selecting the information with the fewest errors from a large number of wireless transmissions of the same k stelhgen information between mutually movable interrogation and answering devices - Google Patents

Description

Procedure for automatically selecting the information with the fewest errors from a large number of interrogation and response devices that can be moved relative to one another successive wireless transmissions of the same k-digit information

The invention relates to a method for automatically selecting the information with the fewest errors from a Multiple successive wireless transmissions between mutually movable interrogation and response devices the same k-digit information in which each digit is represented by an "n out of m" code character.

The interrogators can, for example, in railway systems be arranged next to or between the rails in such a way that the transponders attached to the passing freight wagons, in which information about the vehicle identification is permanently set, can query.

The information transmitted by the transponders can but have errors in the correct information, e.g. as a result of damage to the responder in question or temporary interference radiation. Part of those mistakes can be recognized and eliminated by the fact that the k-digit information is transmitted cyclically so often that with at least two items of information received in full in succession can be calculated. Forner can also make the statement important no, when a transponder has moved so far out of the interrogator's range that the

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transmitted information is only received incompletely can be. This statement can be used, for example, in an evaluation device connected to the interrogation device a command for evaluating, possibly storing or printing out the received information can be derived.

The object of the invention is to obtain from a large number of k-digit information that an interrogator when receives cyclical queries wirelessly one after the other and, after demodulation, forwards the information for evaluation automatically select the fewest errors. In accordance with the invention This object is achieved in that each code character is checked for "n" weighted code and with the corresponding Signs of more recent information are compared, "n" -weightc and identical characters are advanced on the other hand, error characters are advanced for the other characters, the error characters of each piece of information can be counted and compared with the number of faulty characters of the older piece of information and that with a smaller number of error characters of the more recent information this as selected information until the selection information is cached with even fewer errors will.

As a device for carrying out the method according to the invention can, for example, have two series-connected pre-storage units and one intermediate storage unit connected in series and an error marker with a parallel first code checking device is connected upstream of the first pre-store and a first logic element can be connected downstream, deaaen inputs to the input and to the output of the first pre-store are performed, and connected to the first m cells of the second preliminary memory, a second code checking device be, which outputs an error signal to a comparison circuit for each code error, and between the output of the second And the input of the intermediate memory an AND-Glicü

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be switched, the other input of the comparison circuit only then opening potential for further switching information from the second pre-store into the intermediate store is obtained when the number of code errors in the information is at most equal to that specified by a switch Number is.

As a further alternative, a first test memory with (k + 1) memory blocks and a second test memory with k memory blocks is provided be, with a comparison circuit to the last memory block of the first and to the first memory block of the second test memory is connected, which if the characters in the two memory blocks are not identical, an error signal is sent to a OR gate emits, which in this case and when a faulty code is detected by a before the input of the second test memory switched first code checking device an output signal outputs, stores an error character in the first memory block of the second test memory and a first error character counter advances by one step, and with a second Error character counter is provided, the output signals between the output of the second test memory and the Input of a buffer with k memory blocks connected second code checking device can be incremented, and wherein Devices are provided which compare the counting levels of the two error character counters and only at a lower counting level of the first error character counter the advancement of k-digit information from the second test memory into the Release cache.

To determine whether a transponder has passed the effective area of the relevant interrogation device, it is advantageous to use the first error character counter have a maximum of k counting levels and the blocking sequence at the output of the highest counting level a blocking element and an input of an AND element, the setting input of which has an error

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Character switch receives setting potential if the counting stage of the second error character counter is at most equal that of the error code switch, with a control counter which can be incremented by the output signals of the AND element is provided, which after each storage of information in the second test memory via the locking element in its basic position is switchable when the first error character counter has not reached the highest counting level, on the other hand when it reaches a specified counting level Output signal to switch the information contained in the buffer to an information memory or outputs a data output device.

The method according to the invention is explained in more detail below with reference to the exemplary embodiments shown in the drawing explained.

1 and 2 each show a block diagram of a device for carrying out the method according to the invention.

Fig. 3 shows the timing of the states of

Blocks of the block diagram shown in FIG. 2 when a transponder a moves past on the interrogation device.

In the examples shown in FIGS. 1 and 2, it is assumed that the same information is transmitted cyclically repeated several times. A k-digit piece of information should consist of k = 12 characters shown in the "2 out of 5" code.

These characters are shown in FIG. 1 by a receiving device, not shown, of the interrogation device via line 1 on the one hand to an error mark marker 10 and on the other hand to a code checking device 11. The five code elements each character of received information is temporarily stored in the five memory cells 100 to 104 of the

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Pe-hlerzeichen marker 10 and 110 to 114 of the code checking device 11 are stored, of which the respectively assigned cells are interconnected by lines 115 to 119 are connected. The code checking facility checks whether the code of the 3 character is "2" -weight. With the right one Code weight, the character is transmitted via line 2 to a first pre-store 20. If the code weight is incorrect instead of the character, an error character is stored in cells 100 to 104, for example the code weight "5" and is transferred to the memory cells 200 to 204 of the preliminary memory 20. This transmission can, for example, with Arrival of the next character in the error character marker take place. ^

The preliminary memory 20 consists of k = 12 memory blocks with a total of m * k = 60 memory cells. Each character transmitted from the error character marker 10 to the pre-memory 20 is initially stored in the cells 200 to 204 of the first memory block and is advanced by one memory block with each subsequent character. As soon as the first character of the more recent information received in the following cycle is stored in the error character marker 10, the older information is completely in the pre-memory 20, namely the last character in the memory cells 200 to 204 and the first character in the memory cells 205 to 209 older information stored. L

The character passed by the error character marker 10 arrives also via line 21 to logic element 22, the other input of which via line 23 to the output of the first buffer 20 is connected. Characters arriving via the inputs are briefly entered in the logic element 22 cached and then checked for identity. With identity this character is forwarded to the second pre-store 30 via line 3. If there is no identity the logic element 22 sends an error signal via the line 3

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away. Each time a character of the more recent information is stored in the memory cells 200 to 204, this becomes Corresponding characters of the older information from cells 205 to 209 via line 23 to the logic element 22 advanced, compared there in the manner described with the younger character and unchanged in the case of identity, if there is no identity, it is switched to a second pre-store 30 as a fault sign.

The second pre-store 30 also consists of m · k = 60 memory cells, of which the memory cells 300 to 304 each via lines 315 to 319 with assigned memory cells 310 to 314 of a second code checking device 31 connected are. If the line 3 is a fault sign with the code weight "5" is transmitted or the character, e.g. due to a malfunction, does not have the required code weight "2", the code checking device 31 enters via the line 32 Error signal to a comparison circuit 33 · Furthermore, in the first five memory cells 300 to 304 also store a fault character instead of the character with a code error. All k = 12 characters of the information advanced from the first pre-store 20 are thereby successively in the Code checking device 31 checked again for "2" weight code. Each error symbol contained therein triggers an error signal in the code checking device 31. The number of triggered Error signals are counted and stored in the comparison circuit 33 each time information is passed on.

If 30 k = 12 characters of older information are stored in the second pre-memory, the twelve characters of more recent information from the pre-store the characters of the older information from the second pre-store 30 are transmitted one after the other to da3 AND gate 35 via line 34. When the comparison circuit 33 in the older Information has counted at most as many error signals as

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admitted by the adjustable switch 36 for each piece of information, then gives it over the line 331 Opening potential at the setting input of the AND gate 35 · This then switches the characters of the via line 4 older information in a buffer 40.

When storing twelve characters of more recent information in the second pre-memory 30, the comparison circuit 33 the error signals are counted again. The counting result is compared with that of the older information. In the comparison circuit 33, the error character count result of the older information is cleared when the count result the younger information is smaller. The comparison circuit 33 then gives opening potential via the line 331 to the UHD element 35 so that the more recent information in the Buffer 40 can be transferred. These processes are repeated as long as one in the second pre-store 30 More recent information is stored with fewer error characters than the comparison circuit 33 in the case of the older one Information has counted error characters.

The buffer memory 40 consists of memory blocks 401 to 412 for all twelve characters of information. As in In the preliminary memories 20 and 30, the last character of an item of information in the memory block 401 and the first are also here in each case Characters stored in memory block 412. If the more recent information stored in the second pre-store 30 contains less The comparison circuit 33 outputs the older information in the buffer memory 40 via the line Blocking potential to the negating input of blocking element 42, the other input of which via line 41 to the output of the buffer 40 is connected. As a result, when the more recent information is transferred from the second pre-store 30 in the buffer 40 the older information via the line 41 to the locking member 42, but from this not switched on via line 421.

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Contains the more recent information in the second pre-store 30 if the same number or more error characters as the older information in the buffer 40, then the comparison circuit switches 33 the opening potential from the setting input de3 AND gate 35. Exceeds that of the comparison circuit 33 counted number of error signals of the information passed on one after the other from the second pre-store 30 after an equal or smaller number than specified by the switch, for example three times the specified number, so the blocking potential is switched off from the line 332. Furthermore, switching pulses are transmitted via line 333 given to the input of the memory 40. the Older information stored in the buffer 40 with the fewest error characters is then transmitted via the line 41, the blocking element 42 and the output line 421 are switched on into an information memory (not shown).

In the example of FIG. 2, each character arrives from a receiving device, not shown, via line 5 into a first test memory 51 with k + 1 = 13 memory blocks and at the same time in a second test memory 53 with k = 12 memory blocks and five memory cells each. The output of the last memory block 511 of the first test memory 51 is connected to an input of a comparison circuit 52. The other input of this comparison circuit is with the Output of the first memory block 531 of the second test memory 53 connected. The comparison circuit 52 checks the Identity of the character of each new item of information transmitted in each case to the memory block 531 of the test memory 53 with the corresponding character of the older information previously transferred to the test memory 51, whose Characters are switched to the last memory block at this point in time. The comparison circuit 52 inputs Error signal to the OR gate 55 if the characters compared are not identical.

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In. a code checker 54 also checks each character checked for compliance with the "2 out of 5" code before being stored in the second test memory 53. Is the tested sign not "2" -weight, so the code checking device gives An error signal is sent via line 541 to OR element 55 · Identity and code checks are carried out simultaneously. At a Error signal at one or both inputs is the OR gate 55 from an output signal, which via line 552 a first error character counter 6 advances and takes place via line 551 in memory block 531 of the second test memory of the received character stores an error character.

The output of the second test memory 53 is connected via the line 532 to the input of an AND element 56, the other input of which is connected to a bistable multivibrator 61. The output of the AND element 56 is connected via the line 56i to the input of a buffer 7 and to the input of a second code checking device 71. The intermediate memory 7 also has k = 12 memory blocks, each with m = 5 cells. The output of this buffer 7 is connected to an information memory (not shown) or a data output device. The code checking device works in the same way as the code checking device 54 and, if the code weight of the checked character is incorrect, sends an incremental signal via line 711 to a second error character counter 8. The counters 6 and 8 have the same number of at most m k = 12 levels, each of which has an output with one input a further comparison circuit 62 are connected. The comparison circuit 62 is activated for a short time after each piece of information and sends a setting pulse to the flip-flop circuit 61 if the number of steps in the error character counter 6 is lower than that of the counter 8.

For resetting or setting the error character counters 6 and 8, the comparison circuit 62 and the bistable multivibrator 61 are from a facility not shown

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generated clock pulses provided. These clock pulses N1, N2 and N3 follow one another closely and repeat after each twelve-digit information has been stored in the Test memories 51 and 53.

The pulses N1 cause the bistable trigger circuit 61 to switch back to the hatched position. The pulses N2 switch the comparison circuit 62 effective and act on it a blocking element 91 · The pulses N3 switch the error character counter 6 directly and via the AND gate 81 when the flip-flop 61 is switched to the non-hatched position is, the error character counter 8 back to its basic settings. If the counter 6 comes between counting the error characters two clock pulses N3 in its end position, it gives blocking potential to the negating input via line 601 of the blocking element 91 and opening potential at an input of the AND element 92. If the second is at this point in time Error character counter 8 at a count level which is equal to or less than that indicated by an error character switch 82 If the set permissible number of errors is set, setting potential is also present at the other input of AND element 92 via line 921. This AND element then sends an incremental pulse to the control counter 9 · When a specified value is reached The control counter emits a signal via its output 901 indicating that the information has been accepted triggers from the buffer 7 in the information memory or the data output device. When the counter reaches 6 between two clock pulses N3 not in its end position, there is no blocking potential at the blocking input of blocking element 91, and the clock pulse N2 resets the control counter 9 to the basic position via the blocking element.

On the basis of the diagram in Fig. 3, the mode of operation is shown below of the embodiment of FIG. 2 explained in more detail. The lines of the diagram show in detail:

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The clock pulses N1, Ν2 and Ν3 »that in the last memory block 511 of the first test memory 51 and in the first memory block 531 of the second test memory 53 before code and Identity check characters contained in each case, the output signals of the OR gate 55, the code and identity check each character contained in the memory block 531 or the error character Z (line 531 N), the counting levels of the first error character counter "6, the output pulses of the second code checking device 71, the counting stages of the second error character counter 8, the output pulses of the comparison circuit 62, the non-hatched position of the toggle circuit 61, which is in the first memory block of the intermediate memory 7, respectively characters contained, the output pulses of the AND gate 92 and of the blocking element 91 and the counting stages of the control counter 9 ·

In the exemplary embodiments in FIGS. 1 and 2, it is assumed that the information received is composed of k = 12 characters are. In the diagram of FIG. 3, on the other hand, for the sake of simplicity and the limited space, the reception of Assuming information with only four characters.

During the reception phase R1 and the transmission of the first information there are only faulty items in the first test memory 51 Character X included. When comparing the contents of the Memory blocks 511 and 531 by comparison circuit 52 "2" weighted code characters are taken from the memory block 531 from the second character B onwards; the comparison circuit However, 52 does not establish any identity and gives an error signal to the OR gate 55 for each character. The output signals of the OR gate each cause an error character Z to be stored in the memory block via line 551 and increment the first error character counter 6 by four levels via the line 552. The clock pulses N1 and N2 are effective not yet settled here. In contrast, the clock pulse N3 switches the counter 6 back to its basic position.

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During the reception phase R2, an incorrect character X and the characters B, C, D are successively stored in the first test memory 51. The following information A, B, A, D contains only “2 ^dd- weight characters, but there is a lack of identity at two points compared with one another, namely in the first and third position." OR gate 55 outputs signals, as a result of which error characters Z are stored in memory block 531 instead of the non-identical characters. Furthermore, the counter 6 is incremented by two levels.

When the device is switched on, the second error character counter is 8 has been placed in its highest counting level. After the second reception phase R2, the counting stages become the counters 6 and 8 are compared by the comparison circuit 62 at the clock pulse N2. Since the counter 6 is at a lower If the count level is as the counter 8, the comparison circuit 62 switches the flip-flop 61 to the one not hatched Position, whereby the AND gate 56 is prepared. The following clock pulse N3 switches counters 6 and 8 to their basic positions return.

During the reception phase R3, the next information A, B, C, D are transmitted, the characters of which are successively stored in the first memory block 531 of the second test memory 53 will. The characters Z, B, Z, D of the older information (line 531 N) previously contained in the second test memory become this is switched on via the prepared AND element 56 into the intermediate memory 7. Only with the third character C der The most recent information A, B, C, D is not identical to the third character A of the older information A, B, A, D. Therefore, the comparison circuit 52 outputs through the OR gate a signal to the counter 6, which thereby advances one step, is switched. At the same time in the second test memory

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an error character Z is stored in block 531 instead of this character. When the older information Z, B, Z, D is advanced into the intermediate memory 7, the Godeprüfeinrichtung switches 71 "for the two error characters Z the second error character counter 8 by one step at a time. After the information has been switched, the flip-flop 61 is activated by the clock pulse N1 switched back to the hatched position. At the clock pulse N2, the comparison circuit 62 emits a setting pulse to the flip-flop 61, since the counting stage of the error character counter 6 is lower than that of the error character counter 8. The clock pulse N3 switches both error character counters 6 and 8 return to the basic position.

During the reception phase R4, the comparison circuit provides no identity is found at any point in the transmitted information for older information. Therefore remains the Counter 6 in its basic position. When switching the Older information A, B, Z, D from the reception phase R3 from the test memory 53 to the buffer 7 is determined by the code test device 71 an error character Z and advances the counter 8 by one level. The one in the buffer 7 before The information Z, B, Z, D contained therein was deleted.

During the reception phase R5, only "2" -weight ones become and identical characters in the corresponding places of the received and older information. Both counters 6 and 8 therefore remain in their basic position. In the case of the clock pulse N2, the comparison circuit 62 does not determine any different counting stages, and the flip-flop circuit remains in its hatched position assumed by the clock pulse N1.

The characters A, B, C, D of the information from the reception phase R4 were still from the second test memory 53 in the Buffer 7 switched on. This information has the fewest errors and remains cached until it called up by a signal at the output 901 of the control counter 9 will.

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If the transponder is out of the range of the interrogator removed, the received signals become weaker and weaker, so that the information is initially still incorrect and later cannot be received at all. In the receiving phase Rx-4, the transponder starts from the To remove the scope of the interrogation device. The information contains two incorrect characters X. In the receiving phase Rx-3, all received characters are incorrect, so that the counter 6 is switched to its highest counting level. The counter 8 remains in the basic position, since the AND gate 56 does not receive any opening potential from the flip-flop 61, thereby the more recent information A, B, Z, Z is not switched further and therefore the code checking device 71 does not emit any port switching pulses. At this In the basic position, switch 82 applies permanent potential to the AND element 92, which emits a port switching pulse to the control counter 9 whenever the clock pulse N3 in the counter 6 switched back to its basic position again to its highest count level is switched. The control counter cannot now be switched to its basic position with the clock pulse N2 because the potential output by the counter 6 at the highest counting level blocks the blocking element 91. The counter 6 reaches its highest counting level a total of four times in the example shown, namely during the reception phases Rx-3, Rx-2, Rx-1 and Rx. The tax meter is thereby advanced to the fourth counting level. Is for example If the third stage is connected to the output 901, then the Rx-1 output from this stage at the end of the reception phase has the effect Signal the switching of the information from the buffer 7 into the information memory, not shown or the data output device.

The invention is not restricted to the examples shown. The device according to FIG. 1 can, for example to the extent that further pre-storages in series are added between the first and second pre-storage units are switched, the outputs of which are also switched to other

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Inputs of the logic element 22 are connected. at two additional pre-stores could then contain the information received from not just two, but four successive ones Reception phases are compared with each other.

Furthermore, the information from not directly successive reception phases, but for example can be compared with each other from every third reception phase.

Furthermore, the control counter 9 in Fig. 2 can be set so that that a signal is only emitted via its output 901 when a much higher level than the third is reached. In practice, the level of the level will depend on how often the information is sent at the highest speed ' of the device moved through the effective area can be. On the other hand, the level must not be selected too low, as this may be for short-term Disturbances the content of the buffer 7 can already be output, although information with as possible few errors has not yet been received.

The exemplary embodiments are intentionally drawn as block diagrams. For each individual block are a matter of course many variants of circuit designs possible.

4 claims
3 figures

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Claims (2)

21011 claims 1. A method for automatically selecting the information with the fewest errors from a large number of successive wireless transmissions of the same k-digit information between mutually movable interrogation and response devices, in which each digit is represented by an "n out of m" code character, characterized that each code character is checked for "n" -weighted code and compared with the corresponding character of the more recent information, "n" -weighted and identical characters are advanced, however, error characters are advanced for the other characters, the error characters of each information are counted and with the number of error characters of the older information are compared, and that with a smaller number of error characters of the more recent information, this is temporarily stored as selected information until information with even fewer errors is selected. 2. Device for performing the method according to claim 1, characterized in that two in Series-connected pre-storage (20 and 30) and a series-connected intermediate storage (40) are provided are that the first pre-store (20) an error character marker (10) with a parallel first code checking device (11) upstream and a first logic element (22) are connected downstream, the inputs of which to the input and to the output of the first buffer store (20) are carried out that to the first m cells (300 to 304) of the second buffer store (30) a second code checking device (31) is connected is, which outputs an error signal to a comparison circuit (33) for each code error, and between the output YPA 9/475/7 VPA 9/260/0030 - 17 - 209832/0900 of the second buffer store (30) and the input of the buffer store (40) an AND element (35) is connected, the other input of which is from the comparison circuit (33) only then opening potential for switching information from the second pre-store to the intermediate store obtained when the number of code errors in the information is at most equal to that indicated by a switch (36) specified number is (Fig. 1). 3 device for carrying out the method according to claim 1, characterized in that a first test memory (51) with (k + 1) memory blocks and a second Test memory (53) with k memory blocks are provided that the last memory block (511) of the first Test memory and to the first memory block (531) of the second test memory connected to a comparison circuit (52) If the characters in the two memory blocks (511 and 531) are not identical, an error signal is output an OR gate (55) emits, which in this case and when a faulty code is detected by a prior to the input of the second test memory (53) connected first code checking device (54) emits an output signal into. The first memory block (531) of the second test memory (53) Stores error characters and advances a first error character counter (6) by one counting stage that a second Pehlerzeichen counter (8) is provided, which by output signals between the output of the second test memory (53) and the input of a buffer (7) with k memory blocks connected second code checking device (71) progressively iat, and that devices (62, 61 and 56) are provided which the counting stages of the Compare both error character counters (6 and 8) and only if the first error character counter is lower (6) forwarding k-digit information, from the second test tape (53) into the buffer (7) release (Fig. 2). VPA 9/475/7 VPA 9/260/0030 - 18 - 209832/0900 4 ·· Device according to claim 3, characterized that the first error character counter (6) has at most k counting stages and at the output of the the highest counting level of the blocking input of a blocking element (91) and an input of a 3 AND element (92) are connected, whose setting input (921) receives setting potential via an error switch (82) when the counting stage of the second error character counter (8) is at most equal to that of the error character switch (82), and that a through the output signals of the UtJD element (92) are switchable Control counter (9) is provided, which after each storage of information in the second test memory (53) Can be switched into its basic position via the locking element (91) is when the first error character counter (6) has not reached the highest counting level, on the other hand when it reaches a predetermined counting stage an output signal for advancing the information contained in the buffer (7) in a Releases information memory or a data output device. VPA 9/475/7
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