DE1524150A1 - Device for controlling program interruptions in electronic data processing systems - Google Patents

Description

Device for controlling vv © n program interruptions in electronic data processing systems

The invention relates to a device for program interruption and for initiating a fixed interruption program in a data processing system with a command control unit for the decryption of commands and a command execution control unit » where, at a given point in time, the decryption and execution of two different commands takes place in an overlapping manner. The system allows the program interruption of a data processing system the central unit to change its status due to certain conditions These conditions can be caused by external influences, by input / output units or by the central unit itself

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develop. According to these conditions, there are a number of possible types of program interruption: Interrupt in the event of a machine error, external interruption, interruption by the operating personnel, program-related interruptions and Input-ZOutput interruptions.

Every time the program is interrupted, the current program status word is stored away and a new program status word is loaded into a special register of the central unit. The old program control word contains all the necessary information about the status of the system at the time of the interruption. If, after the termination of an interrupt routine, there is an instruction which fetches the "old program control word stored away" and reinserts all current program control words, the system is set back to the old status and the program is "at the" point at which it was interrupted ". continued The advantages of the present system consist in the large number and different ti gkei.t of the circuits and signals, ii @ make the '' program interruptions. -The cost of the. Interrupt 'sechanisiaus simd / Ijifolg © .J © s sophisticated system relative

Fix ¹ a .Eimriefei & ss & g to interrupt the program and to initiate

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processing system with a command control unit for decrypting T \ fDTi commands and a command execution control unit, with the decryption and execution of two different commands taking place in an overlapping manner at one point in time, the invention consists in that a bistable circuit arrangement for interrupting the normal program sequence by an interrupt command of the command control unit and a bistable circuit arrangement for interrupting the normal program sequence by an interrupt command of the command execution control unit, interruptions by the Ε-unit have priority over interruptions by the I-unit, and the bistable circuit arrangements to logic output signals in the event of an interrupt request Transferring circuits that record the cause of the program interruption in the old program control word, store this program control word, and retrieve it initiate a new program control word · j

Further features and developments of the subject matter of the invention can be found in the subclaims.

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is not yet set.

In the following, the invention is described in more detail with reference to an embodiment illustrated by drawings. Show it:

1 shows the block diagram of the overall system,

Fig. 2, 3, block diagrams of circuits for the definition 4, 5, 6 and 7 of the interruption priorities,

8 shows the block diagram of the device according to the invention with the two mentioned control switches,

Fig. 9 e ^ n block diagram for the control of an interruption of the Ϊ-unit by the I-Elnhelt,.

Fig. 10 is a block diagram of a logic control circuit . for the definition of the interruption priority,

> ■■■. . ■ ^: ■ '' ■ '■■■' ■ ^:

Figure 11 is a block diagram of a facility for maintaining the interrupt priority,

.u. Fig. 12 U. the block diagram of a recovery circuit,

14 shows the block diagram of a device for the address of the Proßraramstatusworteo in the event of an interruption;

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15 shows the block diagram for the interruption device 1,

44 shows the block diagram of a device for the interrupt code 2;

Fig. 16 is a block diagram of a device for the interrupt code >,

Fig. 17 further block diagrams of control and switching

to 46

circles for the definition, allocation and review of interruption priorities and

47 shows an overview of the ver in the system applied clock signals.

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The system in connection with which the invention will be explained in the following la, consists essentially of a central processing unit CPU, a number of autonomous and more Speiohereinheiten Elngabe-./AusgabeknnJilen. The central unit itself consists in turn of a unit for the interpretation of commands, hereinafter referred to as the! The i-unit contains control devices for the fetching of commands, for command branches, command interruptions and for the traffic with the input-output channels. The! Unit is used to carry out the algebraic and logical operations, transfer and shift.

As the block diagram of FIG. 1 shows, daa has a system also a bus control unit BCU which controls the flow of data also conveyed to the various units of the system, as well as the control of the storage devices causes the controls to be operated by the operating personnel for system maintenance and basic start-stop and reset controls are included in the PDV power distribution unit. The in Flg. 1 also provides clock generator shown the main timing impulses which are present in the whole system Synchronizing operations can be used. Finally, the system also contains an input / output tariff for the connected input / output devices.

009812/1359 BAD

Rait in data processing systems modernster structure - necessary Gründen.-■ '■ for many. Interruptions' in the normal sequence of commands depending on best! filmed internal or external signals. Interruptions. can therefore generally be defined as such signals which interrupt the normal command sequence in the central processing unit and switch it on to a fixed routine. The purpose is to change the state of the 'central unit' depending on certain internal or external conditions of the system.

In general, such a fixed routine includes spewing of the old Prograrmaüfcatuswortec, which is an interruption code in which the cause of the interruption is defined and the retrieval of a «new ProfxarainstatusWordes, with which processing continued 'V-ird.

The program ta tucwort PSV / is a double word that defines the for

correct execution of the program

contains. The FBW includes the instruction address, condition key and other fields. The PSW is generally used to control the instruction sequence and to display the status of the central processing unit in connection with the program execution. The term "running PSW" means.

the program status word that is currently performing its function

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. By saving the running PSW. During an interruption can check the status of the central unit for later testing be held · By loading a new PSW or As already mentioned, the status of a part of the PSW can be set up or changed.

The program interruption system allows the central processing unit change their status due to certain conditions. In the present system, there are essentially five types of program interruptions possible 1 ») Input / output interruption, 2.) program-related interruption, J5.) Interruption by the operating personnel, 4.) external interruption and 5 · ") interruption in the event of a machine error«

Every time the program is interrupted, the current PSW is saved and a new PSW is loaded. The old PSW contains all the necessary information about the status of the system at the time of the interruption. If after completing an interrupt routine an instruction exists that brings back the ^w eggespelcher1e, old PSW and resumes as current PSW, the system will be set to the old status and the program at the point where it was interrupted continues.

Interruptions only take place when the central processing system » unit can be interrupted for a certain condition.

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Through the system mask, program mask and machine error mask Certain interruptions can be masked in the PSW will. ·

The program is always interrupted after completion one instruction and before starting the execution of the next Instruction. However, the occurrence of a program interruption can prevent the. Execution - '"of the current instruction -influence- · So that the program branches into the correct program phase after an interruption »'becomes the cause of the interruption established and precautions taken that the place of the last executed instruction can be determined.

During the execution of an instruction, several interrupt requests occur at the same time. These requirements are in the present system according to the following order of precedence allowed "1.) machine error interruption, 2.) program-related interruption or>.) call by operating personnel" 4.) external interruption, 5 ·) input / output sub | refraction. .

In the present system, interruptions in the E-unit executions Priority over interruptions in the I unit take over, because the JS unit of the I unit by one Order is ahead. This does not apply to externally induced

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Interrupts, clock advancement requests, input-output interruptions, machine tests and "the introductory program control, because these are asynchronous with respect to the! Unit and the Ε-unit or - as in the case of the machine test - no further meaningful processing can take place under any circumstances "Interruptions in the E-unit are recognized in a system designated with" CTRL LCYC ^W , v / as-exactly one machine cycle "while interruptions in the I-unit of the type" I IRPT PM I "are recognized in the transfer from I to £ "The cycle referred to above represents the absolutely last cycle in the execution of the I and E units. All interrupt signals of classes E IRPT FM E and Ξ IRPT FM I are monitored." If one or more of these signals occur, then the bistable flip-flop EXIT switched on for the interruption of the execution. The priority between these interruptions is thus determined by the fact that the "CTRL L CYC" signal occurs half a cycle before the I-to-E transmission. At a given point in time, as far as normal interruptions are concerned, the interruptions sense «that" CTRL L CYC "would normally have priority * · The discussion of the circuit arrangement now begins here«. \. * -: '■■ --.-. "'" .Y -

Absolute © interruption from ^ data tuften C table) - ·

System WQFdssi dt © Mlflmngen of the recognition of a

■ .. ■■■: ^ Ö98t2 / I359 ■ · ■■. ■■■ '.

-U-

E-unit interruption of a first command that is being executed before an I unit interruption of a following Eo command it is recognized which one is being prepared for execution, the absolute Priority level, which necessarily relates to the mass examination (failure-oriented) and the introductory program submission PSW-RGßters intends to change the definitions of interrupt priority calls, as given in the table, and all factors solved by the allocation of an absolute Priority for the various interruptions «g

Absolute Interrupt Priority Levels (Table I); to be considered- Elchtlfcende! 'alctorcn ^ __________ .

The absolute priority of various interruptions becomes indicated in the table below in which the priority assignments 6-8 externally caused interruptions, which are shown there, because of their individuality Treatment. .

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-XK-

Table I.

absolute
priority Interruption
by: i
abbreviation Great IRPT PM 1 1 ' Machine testing MOT CHK - _ IRPT PM 1 2 Initial program load
PSW IPL PSW - IRPT FM E. Store address loading CPU SAP "" E. IRPT FM E) 4 * Invalid memory address CPU INV STR E. IRPT FM X 5 E-progranan E POM IRPi E. IRPT FM 1 (6-8 External interruptions EXT IRPT E. IRPT FM 1 6th 1.) Interrupt button, desk CONS IRPT E. IRPT
IRPT FM
FM 1
1 7th 2.) Timing TIM IRPT E. IRPT FM 1 8th >.) 6 external signals EXT SIO E. IRPT FM 1 9
10 Time keeping
Request
Input / output TIMREQ
CH IRPT E.
E. IRPT FM 1 11 E increase RCVY E. 12th !-Program I PGM IRPT ' I. 1? service SUP CALL I.

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A-break group and B-sub-break group

In Flg. 2, the B-Interrupt group, which includes all interrupts with priority levels from 1 to 11 (which according to Table I contain all interrupts with the exception of I IRPT PM) is indicated by a signal on the B-Interrupt3 line from an OR circuit 1, which responds to signals related to priority groups 1-4, 7-8, 9-10 and 11 »These signals appear on lines IRPT PRI 1-4, IRPT PRI 5-8, IRPT PRl 9-1Q and IC RCVY REQ. Likewise, an OR circuit 2 generates a signal on the A interrupt line, which indicates the asynchronous from interrupt group B IRPT FM 1. This includes the externally effected interruptions (CONS IRPT, TIM IRPT, EXT SIO), cell transmitter forwarding requests and input / output interruptions (CH IRPT). The OR circuit 2 responds to the signal on the ⁰ IRPT PRI 9-10 "line and to a signal on an" EXT IRPT "line.

The "IRPT PRI 1-4 * line is excited in Pig. 3 by an inverter i 1 in response to a signal on an" IRPT PRI Ir4 "line which is generated by an AND circuit; 2 whose input signals are signals * which indicate the absence of the various interruptions with the priority levels between 1 and 4. Exactly the And-Soh & Xtung 2 responds to signals on the lines "CPU SAP ¹ *," MCH CMK! KPT ¹ and ^B IPL LCH "· The output signal of the AND circuit 2 is also fed to an and so holding ^, which also responds to a signal on a ^B B IRPT LCH ¹ * line from the

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Ε-unit responds and thus recognizes the case »in which there is an E program ^{interruption M} E IRPT PM E" with priority level 5 and there are no interruptions with a higher priority level. The AND circuit 3 indicates that the E program interruptions have the highest Have priority by generating a signal on the "iS PQM IRFT PRl" line.

In Figure 4, a signal is generated on the "IRPT PRI 5-8" line through an inverter 1, which is switched to an AND circuit 2 generated signal on a "ΪΛΡΤ PRI ij-ii" line responds. The AND circuit 2 is actuated by signals on the lines "NOT EXT IRPT" and "N (XP E IRPT LCH". The signal on the "IRPT PRI 5-8" line 2 either one of externally caused interruption or an increase in intensity at the input to the AND circuit 2.

By switching Pig «4, the correct priority is assigned between the externally caused timer * * and the channel interruption I - by means of two AND circuits>, -A ₀ - which can only work if a signal is on the * PRI 5 - $ "line is present. The AND circuits>, 4 also require a signal on the" IRPT PRI 1-4 "line to indicate that there is no priority level after the external ^ nterbruchungen'.ausai-teht. * The AND circuit - \

aprloht an aiii © in signal on the ⁹⁸ TIM ADV REQ LCH "line © in Sijpial, on the" TIM ADV RSQ PRI ⁿ "line,

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ν which indicates that, since there is no priority level between 1 and 8, the timer advance has priority. The AND circuit 4 must also recognize that the timer advance has not been given priority by means of a signal on a "TIH ADV REQ ₁ LCH line, and if all of these other input signals are present, the AND circuit 4 can switch on Generate the "CH IRPT PRI" signal in response to a signal on an ¹¹ CH IRPT OUTST LCH "line.

The signal on the "IRPT PRI 9-10" line is generated in Fig. 5 by an inverter 1 in ^{response to an 11} IRFr PRI 9-10 "signal from an AND circuit 2, which in turn reacts to signals on the lines" TIM ADV REQ LCH ⁿ and ⁿ CH IRPT OUTST LCH "responds" The interrupt priority 9-10 is thus assigned if either a timer or a channel interrupt input signal for the AND circuit 2 in FIG. "5 is present.

The output signal of the AND-So hold 2 in Fig. 5 is also M fed to an AND circuit y together with other priority ^{signals on the lines 11} IRPT PRI 1-4 "and * 'IRPT PRI 5-Ö' ¹ · If an input signal on a If the "IC RCVY REQ" line is presented, the AND-So hold 3 generates a signal indicating that priority has been given for command counter recovery on a "RCVY PRI ^M " line. ·

The "IC RCVY REQ ^{! I} signal is generated in Fig. 5 by an AND circuit 4, provided that the IC-Wlederge

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win request hold circuit is set, which is indicated by a signal on the "IC HCVY REQ LCH" line. However, the AND circuit Λ also requires an input signal from an OR circuit 5, which respond either to the lack of execution commands (indicated by a signal on the "ZKQ OP" line) or to the output signal of an AND circuit 6 which recognizes that no "I IRPT FM 1 ^{H is} outstanding, by means of signals on lines ⁿ I PGH IRPT LCH" and ¹¹ BD ■ SUP CALL ". Although according to Table I, the recovery has priority level 11, the ram recovery is in the interruption circuit is not recognized in each case when an "I IRPT FM l" is present. The output signal of the OR circuit 4 is also fed to an inverter 5-7, which transmits a signal on a line "Ip. RCVY REQ "is generated.

The circuits related to external interrupts are in Fig. 3 shown, namely there is a signal on the "EXT IRPT" line generated by an OR circuit 1, if any one of three ANDs 2-4 is operated; these each require an indication that bit 7 of the PSW register equals a 1, which is indicated by a signal on the PSVv? line. The reason for this is that one external interruption can only take place if that corresponding mask bit (PSWT ") is a 1. To the external Interrupts-belong-, external signals, the interrupt button on the console and time interruptions that

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are conditioned by a timer advance which has resulted in the setting of the timer memory word being changed from a positive to a negative value. These are recognized by the various AND circuits 2-4. in FIG. 6 when these respond to signals on the lines "EXT ÖIO IRPT OUTÖT", "CONS IRPT LCH" and "TIM IRFT TGR". If one of the three types of external interruption is present, the OR circuit 1 therefore generates the signal on the "EXT IRFr" line. This signal also passes to an inverter 5 in FIG. 6 which generates ^{a signal on the n} EXT IRPT ^{11 line.} This signal is applied to an AND circuit 6 in Fig. 6 which generates a signal indicating that external interrupts take precedence on an "EXT IRPT PRI" line, provided it has no interrupt priority 1-4 and none "W IRPT FME", which is indicated by signals on the "IRPT PRI 1-4" and "£ IRFI LGH * lines.

In Flg. 2 , after the A IRPT ^H and ⁿ B IRPT ^B signals, a signal indicating that there is an interruption of the execution type from the I unit is transmitted to an "E IRPT FM iViÄltung by an OR circuit 3 which responds to signals on lines ⁿ IRPT PRI 1-4 ^W , "EXT IRPT", "IRPT PRI 9-10" and "IC RCVY REQ". The machine check interrupt and. the initial program load of a PSW controller bind initially k # ine interruptions and secondly do not fall into the "E IRPT FM I" group, but the signal on the ¹¹ E IRPT FM I ^{M line} is used in the catfish * that the use

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of the "IRPT PHI I- ² *" signal does not cause any trouble, and therefore the layout of the circuit can be kept simple. The OR connection 3 thus recognizes all interruptions shown in Table I with the exception of "E IRPT FM E" (E program interruptions) and ¹¹ I IRPT FM I "(I program interruptions and monitoring call).

In this section it has been described how the "A IHPT""and ⁸¹ B IRPT" signals are generated by means of the detection of interruptions of certain priority groups and individual interrupt types, and also describes part of the circuitry which the input signals for generates the "A IRPT" and "B XBPT" signals.

Elnao holding the EXIT folding step

EXIT Selbathaltesehaltung can be adjusted ent "k neither because the last Ε-circulation (ELC) achieved 1st and together nlt last IS-Uralauf and the last branch circulation recent tax circulation (CTRL L CYC) has caused or because the last ünterbreohungsumlauf (IRPT L CYC) is reached and an asynchronous ⁸ E IRFF PM I "is present, in which there are interruptions from the external, channel" and timer advancement type.

The EXIT self-holding circuit of Fig. 8 is shown by

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■■■. ■. ■ ■ ■. ■■. Λ

a signal on a "TON EXIT" line, shown at the top in Fig. 7 - iat; this signal "is generated by an AND circuit. i. The AND circuit 1 senses the fact that" interrupt request hold "is not in the on-state, which indicates that the system is not in the waiting state The "interrupt priority hold" latch circuit is used to prevent even asynchronous interruptions from switching the system back from the wait state to the running state when the hold latch circuit is in the set state.

If there is a signal on the "IRPT PRI HOLi) LCH" line, the AND circuit 1 can respond to the output signal of an OR circuit 2, which in turn is responsive to the output signal of one of the three AND * circuits 5-5. each of these aND circuits indicates one other type and catfish in which can take place entering a monitored by the EXIT Selbathalteschaltung over- Λ interrupt sequence. The AND circuit ^ recognizes the last control cycle with a B interruption, the AND circuit ^ a last interruption cycle with a Α interruption and the AND circuit 5 the occurrence of an A interruption during the on-2ustandes the wait state self-holding circuit. .- * ■■■

The "TOH EXIT" signal is applied to an AND circuit 1 in FIG which is actuated at the Α time (as a result of a signal

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on the AC line) and an OR circuit 2 causes a self-holding circuit $ to be set. The output signal of the self-holding circuit> is reflected in a bipolar self-holding circuit 4 at the beginning of the "Not L ⁿ -Hity" due to the effect of the bipolar self-holding circuit Λ on an LC

Line fed complement-controlled. L clock signal. The output signal of the bipolar self-holding circuit 4 is a signal on the EXIT line. The OR circuit 2 can also be set by "scan" control ^{signals thanks to an AND circuit c} j » which responds to signals on the lines ¹¹ J REQ 32 ^M and" SC GT WD 3 ^W , whereby the AND circuit 5 is actuated if a 1 is contained in bit J52 of the J register during word 5 of a scan operation. The latching circuit 3 is back divided by an OR circuit 6 when a signal is present on the ^M CFU RST "line or when an output signal is present from an AND circuit 7> which is actuated at the Α time if an interruption ^{pulse reset signal is present on the "H} IBPT PULSE RST" line.

The signal on the ECIT line (referred to elsewhere as EXIT signal) defines entry into the interruption 6-pole Or all interruptions with the exception of "I IRPT FM I" either as a result of a "CTRL L CYC" or as Result of an ¹¹ IRPT L CYC "."

The basic functions of an interruption-6-series can entwedir ⁵ by daa ^ '^ EXH signal or by "the ^W I IliTERRUPT ΏΙΏ" -

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Signal-executed-; the latter signal is the equivalent of the EXIT signal but relates to class ¹¹ interrupts I IRPT FM I ^H > The generation of the "I IRPT END '^1" signal is described in the next section, and punctures are explained in the following sections which can be generated either by the EXIT or by the "IIRPT END" signal. \

Compliance with the "! IRPT END" self-defense circuit

In Fig. 9, the signal * that the ¹¹ I INTERRUPT END ^M * self * holding circuit holds * on a line ^Μ Τ0ίί I IRPT / END * .by an and ^ So condition 1 generated * when a signal ⁿ I IRPT FM and the signal ^M I TO H XFER ¹¹ occur at the same time and the EXiT self-locking has not been switched on beforehand »This is achieved by * causing the Ürid circuit 1 to send a signal on the line" i IRPT FM t * and a signal on the line "1 tO e XFER" as well as on the Ausgangsslgnai a | responsive inverter £ * duröh of a signal on line * * IRPF RBf is actuated ^1, Daö signal on the "IRPT RST ⁿ is -Leltung in Figure 9 * dureh einö Oder Schalfeung 5 generated when either the EXIT * signal ödöF a signal BMT the line * t- lÄPT INB iiÖH * * Since the present IXif-Slgnal; iu beginning dei * L-time (during early dor i * 2eit) eraöhöint "erseheint the Signal mt dir ¹¹ IBPf Mf "^ line forward at * ϊ TO S XFER * -Signal» wtnn the EJCIT self-holding in on-state is »the starting»

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signal of the OR-Süheltttng 3 reaches the inverter 2 and defines the priority levels between the interruptions of the type "CTRL L CYC - EXIT" compared to the interruptions ¹¹ I TO E XFER-I IRPT END ".

The signal on the "I IRPT FH!" / Line in FIG. 9 is generated by an OR circuit ^ if signals are present on the lines "SET ID T2 ^tf or ^If I PGM IRPT LCH ^W. These

* Both signals indicate two different classes of ¹¹ I UlPT FM 1 ^M interruptions »The" SET ID T2 ^tt signal indicates interruptions of the type / which are discharged in T2, while the * t PGM IRPT LCfI "signal in T1 indicates sensed interruptions * The signals "SET ID T2 ^B and ⁿ I PGM IRPT LCH ^W identl-, function as a ^w r. IKPT FM I * _f so that a signal" TON I IRPT END "can be generated by" ITOE XFER ^{M "} , provided that the signal ¹¹ IRPT R3T "let has not been generated earlier, which indicates that the EXIT latch circuit is still

} is not in the on-state »

The signal * I TO E XFER ¹¹ is also fed to an AND circuit 5 in FIG. 9 together with the output signal of an inverter 6 which responds to the EXIT signal. This produces a signal on the line “GT I PGM IKPT” which is fed to an AND circuit 7 in FIG. 9 ′. This also responds to the "SET ID T2 ^W " signal and to a signal on the line

BADORiQlNAL

"I PUM IKPT ICiV ¹ on. The AND circuit 7 thus differs somewhat from the input signals of the AND circuit 1, namely the AND circuit 7 does not work / when" I PQMIRPf "is already in the on state this way the T1 and T2 interruptions can be distinguished from each other. So if an interrupt of the ... T1 type has already been sensed (before the "I TO K XFEn" signal), the "I PQM IRPT" - Self-holding circuit already in the on state, so that the AND circuit 7 is blocked.

In FIG. 10, the signal on the “SET ID T2” line is generated by an OR circuit 1 when a signal is present on the “BD SUP CALL ¹ 'line or an output signal from a self-holding circuit 2, which is indicated by an- the L-time circuit. 3 at the beginning set if a signal is present on a line "BD SPEC 1ΠΡΤ ^11, which indicates that the BOP decoding circuit has sensed an invalid Qrenzangabe. The OR circuit 1 can also respond to a signal from an AND circuit 4, which in turn responds to signals which indicate "PRIVILEGE COMMAND" on a line "BD PRIV INSTM", provided that the PSW register indicates that the system (and not the supervisor) is in the problem state, which is indicated by a signal on the "PSW 15 ^{M line} . In addition, the OR circuit 1 responds to the situation in which an execution command other than Thenia command has another execution command what by öin signal on the line

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BADORKSfNAL «- t \ c

"XEQ TO XEQ ^M is displayed. The signal on this line is generated in Fog. 10 by an AND-So hold 5 when the BOP decoding circuit senses an execution command and at the same time a previous execution command has set the execution latching circuit. This is displayed by simultaneous signals on the ¹¹ XEQ OP LCH "line and the" BD XEQ line. '

The OR circuit 1 in FIG. 10 corresponds almost exactly to an OR circuit 6 (shown directly dantoen), which cools all input signals of the OR circuit 1 with the exception of the monitor call input signal on the "BD SUP CALL" line. The OR circuit 6 therefore recognizes interruptions of the T2-I program type. The output signal of the OR circuit 6 is fed to an AND circuit 7 together with a signal on the line “QT I PGM.IRPT”. The effect of the OR circuit 7 is to detect I-program interruptions of the T2 type (v / elehe exclude the supervisor call), the connection of which is made possible (as shown in FIG. 9 and described above) by the absence of the EXIT signal when the signal ^W I TO E XEER "appears. Note that the T2 interrupt is not prevented from generating a signal from the AND circuit, even if a T1-type interrupt may already have occurred; this is indicated in the In contrast to the AND circuit 7 in FIG. 9, which does not cause a T2 setting for the PSW register if the I program interruption self

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• hold circuit has previously been set by an interruption of the TL type. The output signal of the AND circuit 7 in FIG. 10 is a signal on a line "T2 I PGM IRPT", which is fed to an OR circuit 8 in FIG. 6, the output signal of which is a signal on the line "TON I PGM IRPT" is. The OR circuit 8 also responds to the output signal of an AND circuit 9, which is actuated when 12 is switched on as a result of the signal on the TON T2 line, if there is an interruption of the T1 type, which is indicated by a signal on the line "Tl IRPT" is displayed. The "Tl IRPT" line responds to the output signal of an OR circuit in FIG. 10, and this can be ^{activated by a signal on the H} I0P INC ADR "line (indication of a command-related invalid address), by a signal on a Line ^tt ID INV OP "or by a signal from an OR circuit 11. The OR circuit 11 recognizes two different types of specification interruptions from the I unit. The first of these is indicated by a latch circuit 12, which is set by an AND circuit 1> whenever there is a 1 in bit 23 in the command counter register, which indicates that the command counter is trying to address the memory field for the byte level, although all commands are limited to the syllable level (two bytes per syllable).

A further AND circuit in Fig. 10 indicates that the Invalid-Operation-Type Priority was given to the T1 interrupt

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was 1st, namely the AND circuit 16 responds to the output signal of an inverter 17 inuner when there is no output signal from the OR circuit 11, which means that there is no invalid specification interrupt type. The AND circuit 16 also requires an input signal on the ¹¹ IOP INV ADR "line" When these two input signals are present, the AND circuit 16 generates a signal on the ¹¹ INV OP PRI "line in response to a signal on the ⁿ ID INV, 0P ^w line.

In Pig. 10 below, the AND circuit 18 generates a signal for setting the PSW companion in the event of interruptions from the Tl-Tyρ. The AND circuit 18 generates a signal on the "Tl SET PSW * line when signals are present on the lines" Tl IRPT ⁿ and "EXIT". The signal appears even on the ¹¹ Tl SET PSW "" line when an interruption of T2 type can be removed later. The reason is, da3 the interruption of T2 type set the PSW register again, thus his κ setting can change so that the condition existing within the T2 interrupt is reflected, thereby canceling the effect caused by setting the interrupt code of the T1 interrupt in the PSW register. Register is shown in the table in the following section.

The signal on the "TON I IRPT" line, which is passed through the And-

00.98 12/1359

Circuit; 1 is generated in FIG. 9 is fed to an AND circuit 10 in FIG. 8, which causes an OR circuit 11 to be actuated at time A in order to thereby set a self-holding circuit 12. The output S3 signal of the latch circuit 12 is reflected in a bipolar latch circuit Ij5 at the beginning of the "!!" time, so that a signal is generated on the line "I IRPT END LCH". This signal is referred to here as the ¹¹ I IBPT END "signal. The OR circuit 11 also responds to the output signal of an AND circuit 14, which enables the self-holding circuit 12 to be set during Afataat operations when signals are simultaneously present on the fSC OT WD 5 "and the ¹¹ JREQ ^" line. The self-holding circuit 12 is reset by an OR circuit 15 when a signal is present on the "CPU RST ^{W line} or an output signal from an AND-holding 16 which is used for Α time is actuated by a signal on an ^M IRPT PULSE RST ^{H line.} The ¹¹ IRPT PULSE RST "signal appears as soon as either the EXIT signal or the ^W I IRPT END" signal has caused the interrupt reset, provided that there are no outstanding memory requests from the CPU unit, as will be explained below.

Another factor in setting "I IRPT END ¹ * is the I program interruption latch. In FIG. 10, the OR selection 8 provides a signal on the" TON I PCM IRPT "line which is sent to an AND circuit 20 in FIG. 8. The AND circuit 20 responds at the Α time (AC line) and causes an OR circuit 21 to set a self-holding circuit, ^^. ΑΟθβ 1 2/1359

ORfQiMAL _: ^J ■ '"■. ■"' ^V "* _ ..- ... ■■■■. ■" ■ .. ■■ - -

22, which generates a signal on the "I PGM IRPT LCH" line. This signal in turn allows the signal supplied to the OR circuit Λ in FIG. 9, which, together with the signal on the "SET ID T2" line, enables the detection of an! Interruption from I by generating a signal on the ^H I IRPT PM I "line. This in turn is one of the signals that are necessary for the AND circuit 1 of FIG. 9 to generate the signal on the" TON I IRPT END "line. In other words, the OR- So hold 8 in Fig. 10 responds to the output signal of the AND circuit 9 if there is a T1 interrupt, this in turn causes the setting of the ^W I PGM IRPT "latch circuit in FIG. 8, which would be the OR circuit 4 in FIG Fig. 9 is actuated so that the AND circuit 1 in Fig. 9 can generate the "TON I IRPT END" signal. In the case of a ^ interruption, however, the OR circuit 1 in FIG. 10 generates a "SET ID T2 ⁿ signal which is used directly by the OR circuit 4 in FIG. 9 to set the AND circuit 1 to generate the ^M TON I IRPT ENp "signals. One of the reasons that the T1 interrupt has a longer path in the "I IRPT END" latch setting is that buffering is required to hold the interrupt indications from T1 until the later part of T2 when the ? i after E "transfer takes place.

In Flg. 8, the I program interrupt self-holding circuit 22 is reset by an OR circuit 24 when a signal is present on the "CPU RST ^{n line} or an output

009812/1359 '

Signal of an AND circuit 25, which at the Α-time on the "IRPT END RST "signal is actuated. This signal occurs at the end the succession of overbreeding, and therefore becomes the self-keeper circuit 22 during the fixed interruption sequence in the bin * State brought up «so that they continue the Tl interruptions Identifies and distinguishes them from T2 interruptions.

Time control for setting the interruption quality

One of the features of the fixed interrupt sequence is the setting of the interrupt code in the PSW register prior to the replacement of the PSW. This is done at different times > and the times for bits 15-22 in the differ

Comparison with the tent control for bits 24-21 in some cases. For example, bits 24-21 of an interruption type T1 are set when T2 is switched on. "Bits 24-31 of an interruption type T2 are set for the" I to K "transmission; bits 24-31 of channel (I / O) - Interrupts are set when the interrupt circulation ο 2 is switched on. On the other hand, bits 16-22 of all interruptions when interrupt circulation 1 is switched on and bits 24-21 of all interruptions with the exception of channel »and" Ϊ IRPT FM I ⁿ interruptions are also set when the Interruption cycle 1 set. ·

Priority holding and interruption reset,, Two of the main introductory functions of a normal solid

009812/1359

. Interrupt sequences are the resetting of normal system functions if this is necessary for the interrupt functions to take place, the stopping of the operation of the command setting and the command execution and the "freezing" of the interrupt detection circuit, so that after an interrupt either the EXIT or the ¹¹ I IRPT END "circuit has been set, no further interruptions are recognized until the end of the fixed recognition sequence.

In FIG. 9, the "IRPT-RST signal is generated by the OR circuit when either the" I IRPT END ⁿ - or the EXIT signal is present. The signal on the Interrupt HungarUckatell line (IRPT RST) is used in various parts of the CPU unit to allow interrupt handling.

In FIG. 7, a signal on the ^w IRPT TON PRI HOLD "line is generated by an OR circuit 6 in the presence of either the" TON I IRPT END * or the "TON EXIT" signal. The signal that switches on one of the additional interruption sequence self-holding circuits also serves as a switch-on signal for "IHPT PRI HOLD ¹ *. The output signal of the OR circuit 6 in Fig. 7 is fed to an OR circuit 1 in Pig. U, which at the A time causes the AND circuit 2 to operate an OR circuit 3 and thereby set a self-holding circuit 4, the output signal of which is reflected in a bipolar self-holding circuit, which a signal on the "IRPT PRI HOLD (hereinafter referred to as" IRPT PRI HOLD "signal)

generated. The OR circuit ^ in Fig. 11 can also by a

(309812/1359

-OV-

AND circuit 6 when the scan signal is present on the "SCAN GT WD 6 "line operated so that the self-holding circuit 4 can always be set if bit 27 in J-Regiater is a 1.

The OR hold 1 in FIG. 11 receives a further input signal from an AND circuit 7 which responds to a signal on the "HALT LCIi" line simultaneously with the output signal of an and circuit 8. The AND circuit 8 recognizes the waiting state of the system if the timer ^{global circuit request has not been set as a result of signals on the lines 11} TIM ADV KEQ LCH "and ¹¹ WAIT STAT LCH". The ¹¹ IRPT PRI HOLD ^M signal can therefore be generated by "IRPT TON PRI HOLD" when either the EXIT or the ¹¹ I IRPT END ^W signal is present, or it can be generated when the machine is waiting and the " HALT locking "is set, provided there is no pending timer advance unö3 request.

The latch 4 in Fig. 11 is reset by an OR latch 9 when there is a signal on the "CPU RST * ^{1 line} or the output signal of an AND circuit 10, which is actuated at Α-time if an output signal from a Or circuit 11. The OR circuit 11 for its part responds either to the "UNDERDRECHUNOSUMLAUF 5 ^rt -" Eienal on the "IRPT CYC 5 ^{W line} or to the output signal of one of three AND circuits 12-14. The AND circuit 12 detects when the system is in the Wartcstadlum and the sub-

00 9 8 12/1359 _{& Art Λ}

Breaking priority self-holding circuit is set to prevent interruptions from occurring (which only happens if the HALT interlocking is also set when the system is in the waiting state), and the and hold 12 is then actuated if the halts -Self-holding circuit is switched off, which is indicated by a signal on the "HALT LCH" line. The AND circuit 12 receives an output signal from the AND circuit 8 and a signal on the line ^w IRPT PRI HOLD LCH ^W as further input signals. The AND circuit IJ allows a short interruption sequence in the event of a timer forwarding request, in that it recognizes the deactivation of the interruption cycle 2 when the timer forwarding request as a result of signals on the lines "TOP IRPT CYC 2 * and" TIM ADV REQ PRl The AND circuit 14 enables an even shorter sequence, if only recovery is to take place, by having the signal on the ¹¹ IRPT PULSE RST "line at the same time as a signal indicating that recovery priority has been granted, on the "RCVY PRI ^{n line} ".

The signal "hold interrupt priority" is also used at the beginning of a fixed sequence if the feet sequence is used for timer advancement or recovery purposes, and it is also used to recognize the case that * the system is in the waiting state and the hold latching circuit fc is set to prevent mn any of the asynchronous interrupts, daa Sjpteji; auis dara waiting state listening nimsit #

2 / i359

BADORfQlNAL

• by preventing the sensing of the interruptions in the interruption circuit.

IC return recovery requirement-self-holding

The normal operation of the Pig. 12 shown IC recovery request self-holding circuit begins with a signal on the line "TÖN IC RCVY REQ", which is fed to an AND circuit 1, which is actuated at the Α-time and an OR circuit 2 causes a self-holding function ^ · whose output signal is reflected in the bipolar self-holding 4 on the L-time, so that a signal is generated on the ^H IC RCVY REQ LCH "line. This signal is always generated in FIG. Oils or circuit 2 in Pig. 12 can | also respond to an AND circuit 5, which recognizes bit 26 of the J register during scan word 6 as a result of signals on the lines "J REG 26" and "SCAN GT WD 6". The hold circuit 3 is reset by an OR circuit in response to a signal on the "CPU RST" line or at the instigation of an AND hold 7 that is activated at the Α time if a signal from an OR hold 8 is present . The ORC 8 responds to a signal on the "IRPT PULSE RST" -

-3 * - Ί. 524150

Line which indicates that the storage sequence can begin « without being disturbed by data being returned from the memory, or on a signal on the line "BR .TOP'XEQ OP", which indicates that the system branched out has "so that no execution operation will take place and therefore no execution recovery is necessary; actually lifts the signal "BR TOP XEQ QP" on the execution recovery.

The output of the circuit of Fig. 12 on the "IC RCVY REQ LCH ^{n line} is applied as an input to the circuit of Fig. 5. As briefly described above, the IC recovery request latch then generates the IC recovery request signal in Fig. 5 not if there is an I interruption from I (AND circuit 6) or if it is an execution operation, because it is only known that IC RUok recovery is necessary if these conditions apply Recovery priority is only granted in page S when there is no higher priority level 1-10. If recovery priority is granted, it is used in page 11 to grant "HOLD INTERRUPT PRIORITY" and it is not required to provide interrupt control bits to address Memory words in Fig. 14, and it is not needed in Figs. 15 and 16 to generate interrupt codes, since recovery no interrupt 1s t and appears in the interruption controls only to achieve interruption arüokstellong conditions, for which purpose the

■ - ■ I.- '

Unlocking certain IC controls heard; besides, she will

009812/1359

- ■; »■ -

In Flg. 7 all input signals are used for the circuits, which cause the MODAR circuit to be reset.

Console break self-holding circuit

In Plgv- '17, a signal on an "IRPT TB" line from the switchboard area of the system relating to the power distribution unit (PDU) causes an AND circuit 1 to set a self-holding circuit 2 as soon as it is reset at the beginning of the BR- ( tent Output signal of Solbsthaitesohaltung 2 Bird fed to an AND circuit 3, which causes an OR circuit 4 to set a self-holding circuit 5 at Α-time as a result of a running A-Taktolgnals on the AR line Self-holding circuit 6 reflected when the "LCiFpRl" signal occurs, which indicates that the self-holding circuits within the interruption output circuit arrangement are allowed to switch and assume the state corresponding to their input signals. The bipolar self-holding circuit 6 generates a signal on the line "CONS IRPT. LCH".

The OR circuit 4 in Pig. 17 can also respond to an AND circuit 7 during scan word 5 if signals are present on the lines "JR ^ G J51 ^M and" SCAN QT WD 5 ⁿ . The self-holding circuit 5 is reset by an OR circuit 8. a signal on the "CPU RST" line at the Α time on the output.

0098 12/1359
BADORH3INAL

signal to an AND circuit 10. The And-Sohaltung 10 recognizes the case that the console interruption self-holding is already in the on state and the console interruption has been given priority, which is indicated by a signal on the "EXT IRPT PRI ^M * line, so that the And so hold 10 is actuated during cycle 4 of the interrupts by the signal on the ^H IRPT CYC 4 LCH "line.

The output of the "CONS IRPT LGH ¹ * line (Pig. 17) is fed to the circuit of FIG. 15, although it is not shown there, and is used in generating a signal on the" CPU RST & MCH CHK ^{1 line} 'or by an AND circuit 9 which generates the interrupt code bit 25 in the same way as the TIM IRPT trigger circuit generates the interrupt code bit 24.

Machine test circuits .

This system is used to sense errors or failures the errors first from the maintenance controls used within the power distribution unit (PDU) to effect a logical operation ("log" operation) in which a gray number of conditions recorded within the machine - to be examined by maintenance personnel. To. The maintenance controls then sense completion of the "log" operation a scan control signal to initiate a machine test interrupt au cause the exchange of PSW registers and the

■■■ '■ 00 9 8 1 2/1359

Execution of a diagnostic or other program related to of the new PSW register.

In FIG. 18, the maintenance controls request a machine test interruption by sending a signal over a line "SCAN SET MCH CHK" to an and circuit 1, which is actuated when there is also a signal on the "CPU RST ^{11 line} The signal on the "CPU RST ¹ * line is a function of the completion of the" log "operation as related to the PDU | Maintenance controls is described. The Uend circuit 1 causes the OR circuit 2, a signal on the adjusting line produce su (dies® signal serves sure adjusting the Selbsthaltesohaltung 10 in Flg. 19) s whose output signal is a signal on a "MGH CHK START * line The ^K MCH CHK START "signal is also fed to an OR circuit 11 so that it ^{generates a signal on a" MCH CHK IRPT W line} . After the setting signal has been generated, the signal on the "CPU RST * -" disappears. Line, so that the AND-Sehaltung 1 receives no input signal Sföhr, and the output signal of the OR circuit 2 also disappears, whereby the disappearance of the signal on the setting line and the appearance of the signal on an "NXGHT setting line through the ' . Effect of an inverter 3 (Fig. 18) is effected,

In FIG. 18, an and circuit 4 is not actuated; because when there was a signal "on tier ^ CPU BSl ^ -tsifcs & g to excite the Uno circuit!" was offensive. no Bi ^ mX on the

"SCAN SET MCH CHK" line, because there was a S.gnai on the "SCAN SET MCH CHK ^{M line} * Since the fixed interruption sequence has not yet started, there is no signal on an ⁿ IRPT CYC $ LCH" - Line, and therefore the OR circuit 5 does not generate an output signal. The inverter 6 therefore generates a signal on an "RST ⁿ " line.

In Flg. 19, signals are now fed to an AND circuit 12 via the lines "IST", "RÜT ⁿ and" F2 ^ff . The circuits of Fig. 18 stabilize with the signals "sEt", "RST ^w and ^W F2 ^B. After the CPU reset, however, the main clock generator of the system is set in motion and supplies an L clock signal as the first signal, so that a The signal arrives at the input of the AND circuit 12 in Fig. 19. This is therefore affected and causes the setting d®2 »self-holding circuit 13.

sends an input signal to the Oder-Söfealtung 11, so if the self-holding circuit 10 is reset ^, a signal appears on the ^W MCH CHK IBPT "line "LC ¹¹ -

der (Ind ^ Schaltuus 14., Fig. 19 »der auöerdeia Signal over the PI line is routed. · The ■ Ünö circuit

mlmltvmg 10 rüekz% asfe © llen. Leg - backsetting the Schaltiang 10 ksin P2 "Slpial .msiai" in front of _P wau äafeei? erkesmt oil © UnoL-scarf =

1 2713Si

- 39-152A15O

more. The first L clock signal is therefore through the on-state of the self-holding circuit 10, so that the "MCH CHK START "signal appears, which is used in Pig * 20 and a Or circuit 1 contained therein causes an AND circuit 2 to feed an input signal, whereby an OR circuit> is caused to set a self-holding position Λ, Anders Expressed: the machine test start signal allows the detection of the first λ clock signal at the AND circuit 2y but there the machine test start signal after the end of the first L cycle | signals (an L clock signal has the length of an A clock signal) disappears »there are no further A-clock signals that ea allow the AND circuit 2 to become wkrsara as a result of Machine test input signals that are fed to the Oder-S. will. .

The fixed interrupt sequence continues until interrupt run 6 is terminated, creating a signal on the "IRPT CYC 6 LCH" line in FIG. This ^ -... ■> * it smoothes the OR circuit 5 in Figure 18 is a signal to represent ^ to generate ΐ -Leitung that an OR circuit is supplied to l6 in Fig 19, which in turn resets the self-holding circuit 15, so that the signal from the ^W MCH CHK IRPT "line disappears. In addition, this causes the resetting of both latching circuits in the circuits of FIG ^M MCH CHK IRPT "line is sent to

0098 12/135 9

BADORFQINAL

Identify the machine test as opposed to any other type of interrupt in all interrupt circuits used. However, this signal also disappears after PI is reset by "IRPT CYC 6". '

ι ■■■■ - ■

Wait state self-holding circuit

In FIG. 21, an AND circuit 1 can cause an OR circuit 2 to set a self-holding circuit, which in turn sets the bipolar self-holding circuit 4 at the "!" Time, so that it sends a signal on the "WAIT STAT LCH" line which is hereinafter referred to as the wait state signal. The self-holding circuit 1 scans bit 14 of the PSW register, which indicates that the system must always be put into the waiting state when bit 14 is a 1. In order to scan the PSW register, the AND circuit " There is a signal on a "WAIT STAT COND" line, which is generated in Fxg # 7. In Fig. 7, an OR circuit 7 responds to the output signal of one of the two AND circuits 8, 9 and enables bo to be generated of the wait state signal · The AND circuit 8 responds in "CTRL L CYC" if there is no B interrupt, which is indicated by a signal on the * B IRW "line. This is the reverse of the activation condition for the AND circuit 3 in FIG. 7, which causes EXIT to be switched on at "C TRL L CYC" when a signal is on the "B IRPT ^{B line} .

009812/1359

In the last round of a fixed interrupt sequence, an AND circuit 9 responds to a signal on the ¹¹ IRPT L CYC "line There is a signal on the A IRPT "line. If so EXIT would not be switched on, it is always possible to apply the "WAIT STAT COND" signal to the And-So position 1 in Fig. 21 to cause.

In Flg. 21, the OR circuit 2 can also respond to an And-So position 5. which is activated by word 6 in a scanning ((operation by signals on the lines "J REO 29" and "SCAN GT WD 6". The self-holding circuit> is reset by an OR circuit 6 to a signal on the "CPU RST "Line or an output signal of an AND circuit 7, which in turn requires an output signal from the OR circuit 8. The OR circuit 8 detects one of the asynchronous interrupt signals, which include external interrupts, channel interruptions and timer maintenance requests, although the EXIT signal is used as an indication that a timer handover request has been accepted "the purpose of the OR circuit 8 will be described in greater detail in the system YSO Manual, is wherein explained that the waiting state, any activity of the system with the exception of Zeltgeberweitersohaltung, the input / output interrupts (CH IRPT) or the external interrupts. If either of these interrupts is sensed, v the OR circuit β causes the AND circuit 7 to operate the OR circuit 6 so that the Seibathalt © circuit 3 is reset. The system »

009832/1359 /

thus leaves the wait state long enough for a PSW exchange and interrupt operation to take place according to the fixed interrupt sequence, or long enough for the timer word to be corrected. In the event of channel interruptions or external interruptions, PSW registers are exchanged, and bit 14 may or may not contain a 1 in the new PSW. Thus, the machine may or may not return to the wait state depending on the new PSW content related to the interrupt in question. In many cases, the new PSW content requires a short sequence of commands in response to the channel or external interruption, and this short sequence of commands can well end with a "LOAD PSW" command, which RUokUbtransfer the original PSW content (before exiting the wait state) in the PSW register. At this time, the last control circulation detects the last instruction that the PSW bit 14 is a 1, 1st and causes the self-hold circuit> to return to the ON state, whereby the system returns to the waiting state.

Since it does not require an exchange of the PSW contents, the system is only taken out of the waiting state for just as long as necessary to allow the removal of the tentor word, its reduction in the E-flow and its re-registration with or without to allow ZeItgeberunterbrechimg, namely depending on the timing of word eine® positiveil inen on "oh negative

9 ύ 4 ■? / ι

/ ■ Value changed when it was corrected.

A simplified diagram of the timing of the engine check interrupt start circuits is shown in FIG. This sketch shows that the CPU reset causes a momentary set signal while F2 is set, causing the ¹¹ MCH CHK IRPT ¹¹ signal to appear. The circuits remain in this state until the appearance of the first clock signal after the clock is restarted; i this is an LC signal which, together with the P2 signal, causes F1 to be set. If PI is set, the next A clock signal causes "IRPT CYC 1 ^{w to be set} , and the circuits leave all future clock signals except for. Near the end of the next interrupt sequence" IRPT CYC 6 "appears to reset Fl. Fl sets So the generation of the ¹¹ MCH CHK IRPT "signal continues even after switching off F2 ·

After resetting the self-retaining hold 2 at the beginning of a Channel or an external interruption or a timer forwarding, the EXIT self-holding circuit is set, and the last control cycle or the last interrupt cycle are no longer available, so that the signal is on the "WAIT." leading to the input of the AND circuit 1 in FIG

STAT COND "line does not appear. Therefore, the latching hold y must remain reset until" IRPT Ii CYC "appears, which enables a further signal on the" WAIT STAT COND "line.

0098 12/1369

BADQRfQINAt.

The EXIT signal can be generated in response to channel or external interruptions or in response to a timer resetting request by means of an AND circuit 5 in FIG and the nioh & instalation of the hold-on-hold requires. An A interrupt (to which the asynchronous interruptions belong «namely channel interruptions, external interruptions, timer advances] then causes an OR circuit 2 in FIG. 7 to actuate an AND state 1, whereby a signal on the" TON EXIT "line is produced. This leads to the appearance of the EXIT signal in FIG. 8, and this then sets the interrupt circuit 1 in FIG. 20, as will be described below. The EXIT signal is also available to activate the OR circuit 8 in Flg. 21 to operate and thereby reset the self-holding circuit 3 and dismantle the system from the waiting state. However, no interruptions can occur, since there is no ^ T after B * transmission, no last control cycle and no last interrupt cycle takes place until the timer has been advanced. The asynchronous interruptions therefore allow the waiting state self-holding circuit to be reset so that entry into the fixed interruption sequence can take place.

009812/1 359

, Flashing-end program load buffer

In FIG. 23, an AND circuit 1, which switches the interrupt circuit 2 latch on receipt of an acceptance signal from the BCU unit in response to the setting of the interrupt circuit 2 latch, also sends a signal to an AND circuit 2. The and Circuit 2 also responds to the lack of a priority level for a timer advance request, as indicated by a signal on a "TIM ADV REQ PRI line" and the simultaneous presence of a signal on an "IPL A ^{w line} , the indicates that a preliminary program unload is required. The signal on the "IPL A ^{w line" is} activated in FIG. 24 from the time when the maintenance controls begin to activate the IPL latch in FIG Self-holding circuit itself is switched off. The signal on the "IPL A ^{n line} thus indicates that an initial program loading of the PSW register is required.

In Fig. 23 there is therefore an introductory program loading it is necessary to switch on »an open-door mode on 2, the reception an acceptance signal from the BCU unit indicates that the program status word, that for the initial program load operation has been taken from the BCU unit and that therefore the IPL buffer must be switched on, like it is indicated by the "TON IPL BFR" signal · This signal is fed to an AND circuit 1 in Fig. 26 * which leads to the A-

J3O98 12/1 ^ 59
BÄDORf ^ HNAL -

is actuated and an OR circuit 2 causes a latch release> set whose output signal is reflected in a bipolar self-holding circuit to the "!!" tent so that a signal is generated on an "IPL BFR LCH" line will. The OR circuit 2 can also be actuated by an AND circuit 5 during scan word 6 as a result of signals on the lines "J REQ 31" and "SCAN OT WD 6 ·% The self-

"Holding circuit 3 is reset by an OR circuit 6 when there is a signal on the "CPU RST" line or the Output signal of an AND circuit 7. The AND circuit 7 detects the switching on of the interrupt circuit 5, whereby the normal fixed interruption sequence is switched on when it becomes known "that the stored word is returned * In the case of an initial program loading, the switching on of the interrupt circuit 5 in FIG. 27 is effected by an AND-so hold 1, which responds to signals on the lines "J LOADED LCH "and" IPL BFR LCH "responds. Since the" J LOADED "signal as A "J ADV" signal will result in the CPU unit receives from the BCU unit, the "J LOADED" signal indicates that the FSW has been transferred back to the J controller. the AND circuit 1 in Flg. 27 causes the OR circuit 2, a To generate a signal on the "TON IRPT CYC 5" line, which is at the input of the AND circuit 7 in Flg. 26 appears so that the Or circuit 6 can be operated at the Α-time and thereby the self-holding latch 3 is reset.

The IPL self-holding posture in FIG

00W12 / 1359

Switching on the ¹¹ IPL A ^w input signal is sent to the AND circuit 2 in FIG. 23, also causes in Flg. 28 the generation of an "IE IPL START'SEQ *" signal "which is passed to the OR-So hold 1 in FIG. 20 and causes the interruption of the interruption 1 to be set. The interruption of circulation 1 causes the SPL to be prompted, and when the acceptance signal is received by the BCU Unit., Interrupt Circulation 2 is turned off and the IPL buffer (Fig. 26) is kept in. The buffer

remains in the on-state while the memory actually removes the new PSW / and the interruption cycles 4 and 4 are blocked because the interruption cycle 3 is normally set by an AND circuit 1 in FIG. is blocked in a signal on an "IPL A ⁿ line. Since the interrupt circulation 3 is not switched on, the interrupt circulation 4 is not switched on either; this is desirable because a memory circulation is involved in the removal of the PSW for an initial program loading Return of the memory word (J LOADED, and circuit 1, Fig. 27), the normal interruption sequences are resumed by switching on the interruption cycle 5. The activation of the interruption cycle 5 causes the new PSW to be set in the normal way.

Timer Advancement Request \ .

In FIG. 20, an AND statement 1 responds to a signal an * INT TIM IRPT "line, which in the Stroaverteller unit (PDU) in response to a network identification signal (e.g. the usual

01) 981 ^ / 1359

60 Hz current signal> which can be used to supply the ystem with working current). The ^{circuit arrangement generating the M} INT TIM IBPT ^ff signal is shown in FIG. The And-So hold 1 is operated at the beginning of the ^W BR ^M -ZGit, and that immediately after the resetting of a Solbsthalteeohaltung 2, which is thereby set again A clock signal & l actuated because there is a signal on the AR line, and therefore an OR circuit sets a latch circuit 5. The output of the latch circuit 5 is reflected in a bipolar latch circuit so that a signal is generated on the "TIM ADV HEQ LCH" line, provided there is a signal on the "LCH PRI" line indicating that the asynchronous input self-holdings for the interrupt circuits are not "frozen" in the locked state. The OR circuit 4 can also be ..- by an AND circuit 7. are made- »when signals are present on the lines" J REQ 50 ^w and "SCAN GT WD 5". The self-holding circuit 5 is reset by an OR circuit 8 in response to a signal on the "CPU RST" line.

Latching connections for external signals

In Fig. 32, several bipolar self-holding postures 1 In each case actuated by a signal on an "LCH PRlV line,

009812/1359.

in order to restore the setting of a corresponding one of several self-holding devices 2, each of which can be set by an assigned OR circuit 3 to corresponding scan signals, e.g. signals on the SCAN EXT SEQ 2 "line, or to a corresponding one of several ANDs Each and circuit 4 responds to a running A clock signal on the AR line and a signal on the associated external input bus line, such as on the "EXT SIG BUS IN 2" ^line , each of the latches 2 lwrd Rückge-Btelit by an assigned OR circuit 5 when there is a reset signal from an AND condition 6; this speaks to auf.Signale on the lines ⁰ CPU R5T ^M and "SCAN SET MCH CHK", which correspond to the reset signal, which with regard to the timer forwarding request self-holding circuit in Fig. JO and the console interrupt self-holding by Pig. is used. Each of the OR circuits 5 also responds to the output signal of an associated AND circuit T. This is activated by current A clock signals on the AR line and by a signal on the "EXT IRPT EMD * line simultaneously with an associated external interrupt latch signal, for example on the" EXT 310 IRPT 2 LCH "line The prerequisite that a certain bipolar self-holding circuit 1 has been set, the resetting of the corresponding self-holding position 2 at the A-time is brought about by the application of the external interrupt end signal to the AND circuit 7. External original interruption end only means that the external sub-

: 0 0 981 2/1359. *

interruption priority has been granted and that the interruption cycle 4 has been reached (Flg. 27) ·

The designations in Figs. 22 and 36 are after the components aligned and are shown in the table in FIG. 35. In Fig. 25 the external signals 1 - 6 are in the first column listed ο In the second column, the names of the external signal collector lines correspond to the external ones Signals that represent si®. 2 B. the external signal I appears on the input line 7 of the external signal line, the external signal 5 on the input line 3 of the external diagnosis system etc. The third column shows that the external signal self-holding circuits of Fig. 22 are numbered corresponding to the input lines of the external signal collecting line; the external signal 1 is e.g. in the external signal interrupt v =} - self-confidence circuit 7 saved. The last column represents the bit allocation in the interrupt code for the various external signals as well as for console interruptions and timer

-. ■■■■: ■
Since bits 24-21 of the interrupt code can be thought of as bits o-7 of a particular byte of the interrupt code, the components have been named according to the 0-7 meaning of these bits. For example, interrupts caused by timer advance requests cause the interrupt code block 24, which is bit 0 of the byte shown in FIG. 25, to be set. Likewise, console interruptions would cause bit 1 of the byte to be set, and external signal β would

009812/1359

of bit 2 of this byte. Note, however, that the Distinction between the various external signals in the system is only represented by the setting of the interrupt signal will. A certain external signal causes the setting the corresponding self-holding circuit in Fig. 32, the Output signal of any one of these self-holding circuit caused the OR circuit 1 in Fig. 36, a signal on the "EXT SIQ IRPT OUTST "line which is communicated to the interrupt controls that an interrupt caused by an external signal is requested. In addition, the output of the latches in Fig. J2 is fed to the circuits of Figs Generate interrupt code, the relevant bit of the interrupt code which is shown in the last column of FIG. In addition, there is no distinction between the external ones Signals, and each of them is treated equally by the interrupt circuits.

The output signals of the external signal interruption latches in Fig. J2 an exclusive OR complement 1 in Fig. 33, together with signals on the lines "TIM IRPT TGR" and "CONS IRPT LCH". The output of the exclusive OR circuit complex 1 is fed to an inverter 2, so that when there is an even number of bits at the input of the exclusive Or circuit 1 this does not generate an output signal and therefore an in-

• 0098 12/1359

verter 2 generates a parity signal on the "EXT IRPT PAR" line, This ^H TIM IRPT TGR "line comes from the Ε-unit and represents a flip-flop that is set whenever the timer word from a positive is changed to a negative value, indicating that the puncture represented thereby has been completed. This same line is used in Fig. 6 in the generation of the signals aif the lines "EXT IRPT" and "EXT IRPT PRI".

TABLE II

Type of interruption
- - - - ..... 1 PSW bit Circuit for
Masking (fig.) Selector channel 2 1 38 3 2 38 η « ■ 4 3 38 η it 5 4th 38 η η 6th 5 38 η μ 6th . 38 External 7th 6th MGH GHK 13th • - _; ;. Wait state 14th 21

The table shows only a part of all maskings, since im; ■ The system of the present example comprises a PSV / at least 39 bits.

009812/1359

Fixed interruption follow .

The two previous sections have described in detail the circuits which determine which input signals are bonded to the interrupt circuit and which determine whether the EXIT or the "I IRPT END" latching circuit is switched on. The following sections describe the basic fixed interruption sequence and the modifications therein required to handle machine test interruptions, camper maintenance requirements, recoveries, and other special cases. Each of the basic functions of the fixed interruption sequence is described, some of which are used in all poles and others only in certain poles * >

Under break- interruption treatment

The interrupt reset signal is a signal on the ¹¹ IRPT R3T "line that is generated by an OR circuit 5 in Pig. 9 when either the * I IRPT END" or the KXIT signal is present. The ¹¹ IRPT RST "signal is used at various points in the system to enable the execution of the fixed interruption sequence or part of it without interference from punctures of the I-unit or the E-unit, in particular it stops the reception in the 'I-Einhelt and the E-unit until the new PSW is loaded and the interruption is otherwise fully controlled (sequenced).

BADORKSINÄL 00 ^ 0 12/1359

reset signal and a signal indicating that recovery priority has been granted. provided that there is no outstanding memory request from the CPU allocation; Serve everything is indicated by signals on the lines ¹¹ RCVY PRI "," IRFr RST "and" ϋΗΓΤοΠΠ ^ βϋοΥ ¹ ', The AND circuit 10 generates a signal on an "IRPT TO RCVY" line that is in the IC EtJTNMIME -Sholding. Of PIg, 29 is used to cause an OR circuit 1 to generate the "TOM IC RCVY" signal. The EXIT-3rd signal does not effect the setting of the first interruption run in FIG Since there is a signal on the "RCViT PRl" line, "recovery" only goes into the interruption circuit in order ^{to then generate the interruption of the satellite signal on the "IRPT RST n line} and thereby the resetting of several functions in the CPU To achieve unit, and when the UnteröhungörUckstellsignals appear, the control is transferred to the IC control part of the CPU unit "CTÜ ^ C ^ M ^ HJSY" and emits a signal on the "IRPT PULSE RST" line, as soon as the "Interrupt reset signal appears, provided that" no pending withdrawal has been requested by the CPU unit from the memory unit. That. "1HPT _: PULSE RST ^U -signal wLrü the 'EXIT-S eibsthai tea ohaltimg yon FIg, 8 augefllhi ^ t in order to rüoiczu« stsllejij uikI is also the OR circuit 8 in Pig »20 reineiton> to dls ^fi IC RGW REQ ⁿ -Selfhalteschaltuni5 rUckaustelLeü, after one «.single ECIT <» UffllaiU% Within this the "'IRPT RST' ¹ signal

BADORK3INAL

ÜÜ.9 8 ι Ll "1-3 5 9

therefore causes the EXIT latch to be set The following A clock signal resets the EXIT and the "IC RCVY HEQ" latching circuit. ·

The "IRPT PULSE RST" signal generated by the "IHPT RST" signal becomes the EXIT and "I IRPT END" latches in each Interrupt sequence supplied; in other words, these are two Self-holding circuits only during the first machine cycle fixed interruption sequence in the on-state. ■

Note that the actual output signals of the EXIT and the "I IRPT END" self-holding circuits in FIG. 8 are the output signals of the bipolar self-holding circuits 4 and 13, which are only set at the end of the L time, If the time reaches completely beyond the Α time, there is no possibility for the generation of the interruption reset signal by the OR circuit 3 in FIG. 9 before the "I?" Signals through the AND circuit 11 in Fig. 7 before the start of the "L" time, which corresponds to at least half the A-time, so that a second A-clock signal (one following that which is used, to set either the EXIT or the "I IRPT EIID" latching circuit) before resetting the EXIT or the "I IRPT END ¹ * latching circuit"

09812/1353

If the recovery priority has not been granted, a AND circuit 12 in Fig. 7 by the interrupt reset signal and a signal on the "RCVY PRI" line causes a signal to appear an "IRPT SET BLK IC & TI" line.

Set the 3 interrupt codes

The insertion of the interrupt code into the PSW is timed. In particular, the "TI SET PSW" line in Pig. IO and the "T2 3ET PSW" line in Figure 9 represents the substitution for the bits 24-31, and the "EXEC SET PSW" line in Figure 39 does that late onset for bits 24-31. Bits 16-23 of the interrupt code are always canceled by the interrupt reset signal , used, which occurs when the interruption cycle 1 is switched on. Bits 24-31 are sometimes turned on when the interrupt is turned on 1 set (all with the exception of "I IRPT FM U" or "CH IRPT ") by the" EXEC SET PSW "signal.

In Fig. 39, a signal on the "EXEC SET PSW ^{H line is} generated by an OR circuit 1 in response to an AND circuit 2 or a signal on the" MCH CHK START "line. The AND circuit 2 is generated by © An OR circuit 3 is actuated when a signal is present on the ^w CH IRPT REL LCH "line or when an output signal from an AND circuit 4 is present. The AND circuit 4 speaks to that

00 9 8 Ί Ll 1.3-5

EXIT-3 signal together asserts a signal on an ¹¹ CH IRPT BtI "line and normally controls generation of the" EXEC SET PSW "signal. Therefore, AND circuit 4 is the means by which bits 24 are inserted into the PSW in all cases with the exception of channel ^{interruptions and 11} I IRPT FM I "interruptions. The OR circuit 3 responds to the signal on the "CH IRPT REL LCH" line to define the time when the channel sends the response signal to the CPU

Unit sent back and informed it that the address of the unit which caused the interruption is on the unit address bus (UABI) and that it is therefore possible to insert the unit address in PSW bits 24 - Jl as an interruption for it which occurs at the instant of turning on interrupt run 2 because the ^w CH IRPT REL LCH "signal is used to turn on interrupt run 2 in FIG.

A special case of a memory address interruption which is initiated by a memory request which occurred directly before an ⁿ IRPT FM I * «interruption is dealt with by the OR circuit 5, 6 in FIG. If an "I IRPT FM I" interrupt has been sensed and a "CPU SAP" signal is received at the interrupt controls, the "CPU SAP" interrupt will be from the * I IRPT END "latch instead of the EXIT latch since this has already been initiated, in this particular case the interrupt code for "CPU SAP" is passed through

009812/1359

The "EXEC SET PSW" line inserted into the PSW at the time the interrupt circuit 1 'was activated as a result of "! IRPT END" instead of as a result of EXIT. In such a case, bits 24-31 of the interrupt code have already been set for an "I IRPT FM!" Since "CPU SAP" sometimes has priority over '* I IRPT FM I ^H , the interrupt code bits 16-23 of the "I IRPT FM!" there is an "I IRPT FM I" interruption following a "CPU SAP" interruption. The combination of the time-controlled interrupt priority level (as between "I IRPT FM I" and all other interruptions ^ with the absolute priority levels of all interruptions (where "CPU SAP" has priority over "^ tRPT FM I") enables late interruptions with higher priority level, previously sensed interruptions with a lower priority level, even if the race between the EXIT self-retaining circuit and the "I IRPT END" self-retaining circuit has been won by the latter ". This race takes place at a rate that starts with" CTRL L CYC ' ¹ and "ITO E 2FER" zuaamraenf5111t, because the EXIT self-holding circuit via the monitor

The breakout reset signal prevents the setting of the "I IRPT EIID" -Self3 Thai circuit and ^{because the tt} I TO B XFER "is about half a Ural run later as" CTRL L CYC *.

The generation of interrupt code bits 2% - 28 1st complete

009812/1359

152415Q

- 59 -

in Pig. 15 illustrates that these bits can only be used by interrupt types "E IRPT PM I", "EXT 310" and "CH IRPT""," PRIV OP "," XEQ TO XEQ "," IKV ADR "and" INV SPEC "are used. Therefore, the output signals corresponding to bits 29-31 become Pir. 15 in Flg. 16 mlther-n coding signals are combined in FIG. 37. The code transfer signals _{ are sent in the manner shown in FIG. 37 so that each of the interrupt types "invalid operation", "privileged operation", "execution", "invalid address" and "specification" generate a corresponding signal on the output line of FIG whether the interruption is sensed at T1 or at T2 (such as "SPEC PRI"). The output signals from FIG. 37 are combined with bits 29-31 and the parity bit of the output signals from FIG. This is done in FIG. 16, which only contains a plurality of OR circuits 1. The circuits of Figures 15, 16 and 37 operate in the manner that an Interrupt3codeblt is generated for each of them, as shown in the Interrupt Code Table in the following sections. If a signal appears on a ^W CPU SAP "line, a signal is automatically generated on the" SAP PRI "line. The reason for this is that whenever a memory address protection interruption occurs, this automatically has priority, since a machine test is impossible can be present (because the system is divided back immediately before the machine test) and since it cannot possibly be necessary to load the PSH in an initial program loading operation (because the machine has not done anything before loading the IPL PSW)

009812/1359

- 6ο -

Ib Fig. 40, an AND circuit 1 generates a signal on an "INV STR PRI ^{W line} , provided that there are no" CPU SAP "interruptions, which is indicated by a signal on the" CPU SRP "line * and that in signal is present on a "CPU INV SIR * line. In Pig» 43. an AND circuit 2 generates a signal on a ⁰ SUP CALL PRI "line, provided that no other interrupt and no other input signal for Unterbrechungssohaltungen present · in particular, the AND circuit 2 speaks only -an when signals are present on the following lines: "BD SUP CALL", "IRPT PRI 1-4", "IRPT PRI 5-10 ¹ '," IC RCVY REQ " ¹ and ¹¹ I PCM IRPT LCH ¹ '. Further input signals for the circuits of FIGS. 15, 16 and 27 appear in FIGS. 4, 40, 41, 5, 5, 9 and 10.

Generation of the PSW address

Flg. 14 shows circuits which use address bits for storing the generate the old PSW and remove the new PSW. In Flg. 14 supplies an OR circuit 1 a through-connection signal for bits 26-28 and the parity bit of the interruption address. This is effective during the interrupt cycle 1 and during the PSW store tell of the interrupt sequence «well signals on de, η lines" IRPH CYC 1 LCH * and "STR PSW" are present. Bits 26-28 are replaced by the Auageuigeeignal of the OR circuit from a corresponding And-öchaltune 2 - 4 forwarded. Every 4's and circuit 2 «3 # 4 generates a -«.

Output sign on the corresponding "IBPT CTRL BITS" lines Jt

009812/1359

after "trie e3 is necessary" to meet certain conditions. For example, the AND circuit 4 generates bit 28 for external program or channel interruptions as a result of the presence of signals on the lines "EXT IRPT PRI *," PTM IRPT PRI ¹¹ and "CH IRPT PRI" at the input of an OR circuit. 3. Bit 28 is a 1 for external »program and channel (I / o) interruptions both when removing the new PSW and when saving the old PSW Bit 27 and responds to external "machine test or channel interruptions or to a timer switching request" The and-so position 2 is then activated by an OR circuit 7 "if there is a program interruption", which is indicated by an and-so position 8 “The AND-So hold 8 is operated by an OR circuit 9” which in turn responds to an AND-circuit 10. The And-So hold 10 only recognizes I-Prograasi interruptions as a result of the switching off of interruptions with a priority level of 1-11 according to Table 1 and the OR circuit 9 also responds to E-Programffi interruptions and to interruptions old of a priority level between 1 and 4. The AND circuit 8, however, eliminates the interruption en with a priority level I or 2 «if signals are present on lines ⁸ MCH CHIC IRPT" and "IPX · LCÖ". The output signal of the AND circuit 8 thus equals the priority level of the program interruptions, which, together with monitor call, machine test or channel interruptions, causes the bit 26 to be generated by the AND circuit 2. ■ "'-"' * ■

009312 / 13SS

BÄDQRH3INAU ■. -

-.62 ■ * : ■ "V -

Circuit Ii recognizes _s when PSW. · »Are withdrawn with the exception of the IPL-PSW ₉ wesm signals on lines ¹¹ IRPO? CYC 1 LCH "and" IPL LCH ^rt are present »This generates a bit 25 to remove the * geitgehe ^ signal and to remove all PSW ⁵ S with the exception of the IPL ' ^:

In Pig.14 below, the parity bit for bits 25-28 of the PSW address is generated by an OR circuit 12 on one of the two Lind circuits Ij, lh . "Pica BeMltung 15 during the interruption run 1 then bstätisö _s when an output signal from an OR circuit 1§. Is present, which in turn responds to an OR circuit 16 · The ©« ter circuit responds to Oberwaoheraufruf parity or channel interrupt Priorltä & also so produced and to a TlM ^ Weiterschaltungsanf conveyance or an introductory Frogramisbeladung "While the circulation 1 a parity bit for the fiDtnabneedreese ^, di" refers to IPL-timer Oberwacher- t call -and output operations.

The Schaltusg 14 is tiMferend.-a storage of the FSW operated -at Unt © rbrt: v; i; ^; W3Si - '>P'3 ^ a ^f -ifnen jedop ürt with the exception of the Uberwachar call "and Kanr.1 (I / O) -' Jn! -, erbrochung ^^ i what through an inverter responding to the OdergohaituD ^ 16 17 is effected. A parity bit is generated for external, program and machine check interrupts when the corresponding PSW is gaapai, as it is a signal on 4's

009812/1358

- 6 J «" -. ■■■ ... - '■

¹¹ STR PSW ^W line is out. Note that the step in Fig. 14 is not generated for storing the corrected transmitter signal, because the transmitter-wide switching prevented the setting of the test cycle, because at that point in time control is transferred to the E unit , and when everything is ready, the interrupt control is resumed with the interruption cycle 5. The setting of the address adder for storing the timer word remains unchanged the same as when the timer word was extracted and therefore there is now no new generation for storing the Timer value necessary.

In Pig, 14 below, an And-So hold 18 generates a signal "which causes the length code in the FSW to be set to Q" whenever the memory address protection interrupt occurs because it is impossible to tell whether the memory address protection is a result of a memory command currently being executed or a previous memory command 1st. This in turn results from the fact that ( the last Ε cycle can be stopped (so that the previous execution is ended) as soon as a memory acceptance is accepted by the BCU unit, even if the actual memory run does not start immediately. Since the correct memory command is not identifiable, the length is set to 0 to indicate this.

009812/1359

Interruption cycles ^v

The interruption cycles within the fixed interruption sequence are characterized by the different punctures that each must do by you. The interrupt circulation 1 supplies the address for the removal of the FSW or the timer word j the interrupt circulation 2 results in an interrupt removal together with

) setting flags in anticipation of later storage of either the old PSW or the corrected timer wordosj The interrupt run 5 automatically follows the interrupt run 2, unless it is an introductory program load for the timer relay and causes the movement the right half of the PSW through a boost circuit high-digit half of the K register; Circulation 2 stops when one is received Acceptance signal for the interrupt removal request; the interrupt roundabout 4 generates a memory request and makes the

t External signal latches back and letet the left half of the PSW through the boost circuit to the K register. The memory buttons are used during both interruption cycles 3 and 4 blocked »to get a" CPU SAP "now. The interruption number Run 5 begins »when an acceptance signal for the memory request

'is received according to the tent provider word or according to the old PSW »and is therefore used "to recognize" that the withdrawal request was made beforehand Rough3 because the storage unit received the new PSW first

009812/1359

delivers and must then be available so that the acceptance signal brings the circulation 5 self-holding circuit to the setting state « The interruption run 6 automatically follows the interruption cycle 5

The final interruption cycle provides a means of exiting the fixed Uofcerbrechungssequence or to enter another fixed Interruption sequence in the case of an asynchronous interruption.

Interrupt cycle X _f

Your pig. 20, an OR circuit 1 recognizes the various conditions that can cause the interruption cycle 1 to be set. The OR circuit 1 responds to signals on the lines "MCH CHK STABT" and ¹¹ ZE IPL START SEQ "or to the output signal of one of the two AND circuits % 6. The AND circuit 5 is always actuated with the exception of recovery situations «If the EXIT self-holding circuit is switched on» if there is no pending memory ^{request from the CPU unit · This is caused by signals on the - ■ lines 11} RCVY PRI "," EXIT "and ^w CPy COMM-BUSY? Likewise, the AND circuit 6 is actuated when the self-holding circuit is not in the on state, through the action of an inverter 7 on the ^M I IRPT END ¹ * - Sigh & l · The inverter 7 gitfc of the EXIT self-holding circuit has priority over the " I IHPT END "latching circuit. The output signal of the OR circuit i Irann through an AND circuit 2 at A-time

009812/1359

«Ββ -

s © © Ine Ode ^ -Schaltimg 3 to initiate a © Selbetlaalteechalfeung% gift · The output signal of the self-holding. 4 - is the Qlner bipolar _ Selbsthaitesohaltung 9 aur "P ¹ ^ time täledergeepiegel * so that © iss signal on the ^W IRPT CfYC 1 IjCH" line @r ^j s @ ugt wiM »Μ, θ or-scarf twig ^ can also by means of an AND circuit IO during scanning operations when signals are present on the lines ^M J REG 24 * "md ⁸ SCAH GT WD 5" Presence of a signal on the tier ⁰ SM-BSf * line or the output signal of an unft-Solml & gns -IS, m 4aS '"! So the self-holding latch 4 one cycle smelt its lins @ ^ aitu" g is switched off by a signal on the? "IRFf

l ·. BADORKSINAL

0098 12/1359

Interrupted circulation 2

In Pig. 23 causes an OR-So position .3 and a © AND circuit 4 to operate an OR circuit 5 and thus set a self-holding position 6, the output signal of which is reflected in a bipolar self-holding circuit 7 for "IT 'time, .bo'" that a signal is ^{generated on the n} IRPT CYC 2 LCH "line. The OR circuit 3 responds to a signal on the ¹¹ CH IRPT REL IsCH" line or to the output signal of an AND circuit 8, which is triggered by signals on the Lines ¹¹ CH IRFi ¹ EiSSP LCH "and" IRPT CYC 1 LCH "operated irrd. The OR circuit 3 and the AND circuit 8 differentiate between channel interruptions and other interruptions, since the interrupt control must inform the channel in order to deal with a channel interruption that the interrupt has been accepted (given priority) and a response to it must be transmitted from the CPU unit to the channel to Uok, after which the channel must indicate that it has received the response by sending back that of an enable signal to the CPU unit. This is controlled by the "CH IRPT RESP" and "CH IRPT REL" latches shown in Figures 42 and 4 and described in the next two sections.

The OR circuit 5 can also be actuated by an AND hold 9 during scanning operations when signals on the lines * J REQ 25 "and" SCAN QT WD 5 ^W are present. The self-holding circuit 6 is rtickgestitted by an OR circuit 10 when a signal is present on the "CfÜ RST" line or in response to the output signal of an AND circuit 11, if

009812/1369

"■ * this at A-time by a signal on the AC line when present an output signal from an AND circuit, 1 actuated will. The AND circuit 1 responds to an acceptance signal, which indicates that the PSW service request from the BCU unit has been accepted »if the interruption cycle 2 switched on 1st. This is done through signals on the lines

If the interrupt circuit 2 is switched on, an AND circuit 12 generates the interrupt request by means of a signal on the "IRFT FTCH RJSQ ^{0 line,} provided that there is also a signal from the OR circuit 3 (the same signal that the setting of the self-holding switch 6 in the first place.) In the course of scanning operations, the interruption request is not generated by the AND circuit 12 even if the interrupt circuit 2 is switched on 12 be "wifkt turning on the Seitgeberumlaufs 1 in the e unit by generating a signal on a" TON TIM CYC l ^w -'Leitung in the presence of a signal on the "TIM ADV FRlV REQ line.

-When the And-Sc-haltüng. 1- generates a signal to switch off the self-holding 6, - it also generates a signal on the line ⁿ TOF IRFT CYC .2% the raehrerea and circuits 14,

009812/1359

15, 2 is fed as an input signal * Oils AND circuit 14 causes the insertion of marker bits for storage in the highest half of a memory word, and the AND circuit 15 causes the insertion of marker bits / to allow the storage of the lower half of a memory word. AND circuits 14 and 15 are responsive to signals on the "JPLHk" line indicating that this is not a preliminary program load operation and that a store operation is therefore involved. The AND circuit 15 also requires a signal on the ^tt TIM ADV REQ Pill "line to prevent the generation of marker bits for the lower half of the memory word during a timer advance operation; this is due to the fact that the timer word consists of jJ2 bits, the include only the high-digit half of a memory word.

If it is an introductory program gray loading operation acts, causes the AND circuit 2 to turn on the IPL buffer, which causes the interrupt loops> and 4 (which are memory circulations) and causes a time delay sufficient to - ensure the removal of a PSW for the initial program loading

Channel interruption response and release

When the EXIT latch is on, it will recognize '0098 1 2 / T359

in Pig. 42 an AND circuit 1 that priority has been given to a channel interruption, and causes an OR circuit 2 to set a self-holding position whose output signal is reflected in the bipolar self-holding circuit 4 at the beginning of the "Γ" time, so that a Signal is ^{generated on an 11} CH IRPT RESP LCH ^ -LeittSÄg. Bio-OR circuit 2 also responds to scanning signals from a tlnd control 5, which is connected to the ⁿ J REG 26 ⁵¹ - ^{and the} SCAH GT WD i> ^w »lines. The self-holding latch 3 is reset by an OR circuit β when a signal is present on the "CPU RST" line or when an AND circuit 7 is actuated, which excites ViVu ₉ at the Α time if a signal on the line ^W CH IRPT REL LCH "is present. If the EXIT latching function is switched on as a result of a channel interruption, the" CH IRPT RESP ^H latching circuit is switched on; when the channel enable signal is transmitted back from the channel to the CPU unit so that the ^W CH IRPT REL ⁿ latch circuit is turned on, the ^e CH IRPT RESP "latch circuit is turned off.

In Pig * 45, an and circuit 1 detects a "CH REL ⁿ signal, this is a signal from a channel indicating that it has received the response and is ready to handle the interrupt. This signal causes a Self-holding circuit 2 at "B" time, the output signal of which is fed to an and-holding 3 * The Ünd circuit y * also requires input signals on an AC line as well as signals which

0 0 9812/1359

indicate that the response latch is set, but the release latch is not set, on lines "ui ju-irx ¹ wjüu jjüiV ¹ and" CJH IRFT RESP LCH ". The output of the ■ ..Und circuit- j5 is fed to an OR circuit 4 and used to set a self-holding circuit ^f j> * whose output signal causes a bipolar self-holding circuit 6 to be set at the ¹¹ L "" time, so that the signal is generated on the "CH IRPT HEL LCH" line In addition, the OR circuit Λ responds to an AND circuit J ₀ which is actuated during scanning operations by signals on the lines "SCAN GT WD ö and" J REO 27 ". The self-holding circuit 5 is reset in Fig. Ky by an OR circuit δ, either as a result of a signal on the ¹¹ CPU RST "line or as a result of the output signal of an O and holding circuit 9, which at the A-time by a signal on ei * er ¹¹ CH IRPT RSL LCH "line is operated. As soon as the bipolar self-holding circuit 6 in Flg. 4JS has been set, oils Selbsthaiteschaitung is 5 rücfcgestellt to the following A-2eit. The ¹¹ CH IRPT RBL "signal is therefore only available for the duration of one cycle.

Uiiterbrechungsumlauf ^

In Fig. 29, an AND circuit 1 precedes another AND circuit 2 to operate an OR circuit 3 and so a self-holding circuit 4, whose output signal is in a

009 812/1359
640

bipolar self-holding circuit 3 ati * "L" time reflected so that a signal is generated on an "IRPT CYC 3 LCH" line will. In addition, the OR circuit 3 is controlled by sampling signals operated as a result of the presence of signals on the Lines "J IiEO 24" and "SCAN GT WD 6" at the input of an AND circuit 6. The self-contained circuit 4 is reset by an OR circuit 7 when a signal is present on the "CPU RST" line or at the instigation of an AND circuit 8> those at A-time after setting the bipolar self-holding circuit 5 is operated. The interruption cycle remains switched on for exactly one cycle duration.

The AND circuit 1 recognizes an acceptance signal from the BCU unit during the interruption cycle 2 if there is neither a timer advance nor an introductory program load. This is caused by signals on the lines "ACCEPT", "IRPT CYC 2 LCH", "TIM AUV REQ PRl" and "IPL A". The signal on the "IRPT CYC 3 LCH ^M line coincides completely with a signal on the ^M STR PSW" line which causes store operations to be initiated so that the old PSVLiri is stored in operations other than timer or initial program load operations.

Interruption cycle 4 -

In FIG. 27, an AND circuit 1 responds to a signal on the ^w IRPT CYC> LCH "line at the A time and thereby causes an OR circuit 2 to set a self-hold position 3.,

0 0 981 27.1 35Ü ^v

whose Ausgansssignal In a bipolar Selbathalteschaltung 4 to ¹¹ I? '-. time is reflected, so that the Unterbreehungsumlauf-4 signal on the ¹¹ IRPT CYC 4 LClI "line is generated Dieaes ·' signal predisposed ELNO OR circuit ij, a "MPT STH RECi" signal to generate; the other input signal "dor OR circuit 5 is the ^tt IRPT CYG" signal This point detects a signal on the "EXT IRPT EHI" line by generating an "EXT IRPT END" signal, which causes the external signal latches in FIG.

The OR circuit 2 is activated by an AND hold 7 during scan operations when signals are present on the lines "J BSQ 25 ¹ * and" SCAN GT WD 6 " when a signal is present on the "CPU RST" line or when an AND circuit 9 is actuated. The AND circuit 9 detects an acceptance signal during the Α time of the interruption incident 4 when signals are present on the "ACCEPT" and "IRPT" lines CYC 4, LCH ". The interrupt circulation 4 signal is therefore effective until an acceptance signal is received from the BCU unit and is then terminated. ·

The same condition is met by an AND circuit β in Flg. 27 recognized and causes the interruption cycle 5 to be switched on,

BATH ORIGINAL 009812/1359 V

which is described below.
Interruptions , 5

In FIG. 27, each of two AND circuits 1, 3 can cause two associated OR circuits 2 _t ¹ I to generate the same signal on the lines "TON-IRPT CYC 5 ¹¹ and" IRFT SET PSW " -ßohaltung 2 AND Circuits ^ 'j supplied to a, whereby an OR circuit 6 is caused to set a Selbsthältesehaltung 7, the output of which is reflected in a bipolar self holding circuit 8 to ^R L ^W -time, so that a signal on lines "IRPT CYC 5 LCH" and "IRPT END RST® is generated * These © signals become one

with OR circuit 9 supplied and can together / the signal on a "SET PSW ^ -Laitimg the generation of a signal on a "RST CH IRPT" line cause »Duroh this signal will be in the IK controls the channel priority circuits (not shown) reset.

The OR circuit 6 can also be actuated by an AND circuit IO if signals are present on the lines "JREQ 28 ⁿ and" SCAN QT VD 5 ^W. The self-holding circuit 7 is reset by an OR circuit 11 as a result of a signal on the "CPU RST" line or at the instigation of an AND circuit 12, which resets the self-holding circuit 7 at the first Α time after the bipolar self-holding circuit 8 has been switched on causes; here it is achieved, clai der

0098 12/1359 " _{BAB 0RieiNAL}

Interruption in run ^l j only has the duration of a single cycle.

. Turning on the Unterbrechungcumlaufs 5 by the G of circuit 2 in Figure 27 with kolnzidiert illustrates operation of the OR circuit 4 which effects the insertion of the PSW, by generating a signal on the "SET IRPT PSW" line. The signal also becomes an OR circuit. IjJ which generates the "IRPT RST J LOADED" signal described above.

Interrupt run 6

In FIG. 45, the coincidence of the Α time with the "IRPT CYC 5 ⁿ signal causes an AND circuit 1 to actuate an OR circuit 2, whereby a self-holding circuit 3 is assigned whose output signal is in a bipolar self-holding circuit at the beginning of the "L" time is reflected, so that a signal is generated on an "IRPT CYC 6 LCH" line. The OR circuit 2 can also respond to scan signals * the lines "J REQ 29" and "SCAN OT ND 5 * can be fed to an And-So hold 5. The self-holding circuit 3 is rüekgestifted by an OR-6 in response to a signal on the ¹¹ CPU RST ^ft line or at the instigation of an AND circuit J at the Α time of the ünt.erfareehungsumlaufs 6. The interruption circuit 6 signal appears on End of an L-time after a Α-time of the round 5 and disappears at the end of the L-side, which on a Α-time in

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_t in circulation 6 follows. The self-holding circuit is therefore in the kin state for the duration of one cycle.

Different circuits n

In FIg. 46, an AND circuit 1 responds to an accept signal during a timer circuit backup, provided the machine is running, which is indicated by an ¹¹ PSW 14 "signal; this causes an OR circuit J5 to output a signal on a "IRPT TO RCVY 2 ^{n line} . This is used to initiate IC recovery in the IC harvest control circuits. Another input signal of the OR circuit 3 is the output signal of the AND circuit 4, which is actuated when the machine is running for the interrupt circuit 4. Thus, when the fixed interrupt sequence has reached circuit 4, it is to be expected that the PSW register will be set to enable circuit 5 and that a recovery can be initiated for the removal of instructions according to the new PSW contents at this point in time.

An OR circuit 2 blocks the memory protection keys during a timer advance storage or during the regular interruption cycles 3 and 4.

An OR circuit 5 causes the left to be forwarded Half of the PSW through the boost circuit to the K register

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, during the interruption university run 4 or when a Signals on a line "XE GT LH PSW TO INCIi".

An OR circuit 6 either responds to an interrupt run 4 or on interruption cycle 5 and causes the connection the error in the expansion circuit for the increase circuit; this error would either use the high-order bits the left half or the right half of the ^ PSW at its Accompany the forwarding through the incremental maintenance to the K-Register. An OR circuit 7 responds to one interruption > or 5 and causes a PSW to be forwarded to Increase in connection.

The PSW can be set in response to operations of the power distribution unit, readjustments of the command counter by maintenance control, interruptions or I-execution operations. An OR circuit 8 effects, for example, the setting of PSW 0 - 39 on the instigation of an AND circuit 9 or on the interruption or IE control of the PSV /. An AND circuit 9 responds to the interruption in the ΙΕ controls and also to an AND circuit 10. The AND circuit 10 is actuated when the maintenance controls set a command counter "by causing the OR circuit 9" Signal. On line ⁿ SET PSW 40-63 "to generate.

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Fig. 47 then finally shows a part of the in the system clock pulses used,

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Claims (5)

152.41 SC - 79 PATEN TA NSPRO CHE t. Device for program interruption and initiation of a fixed interrupt program in a data processing system with an instruction control unit for decryption Of instructions and an instruction execution control unit, where at one point in time the Decryption and execution ν on two different commands takes place in an overlapping manner, characterized in that that a bistable circuit arrangement (12, 13, Fig. 8) to interrupt the normal program sequence by an interrupt command of the command control unit (I-unit, Fig. 1) and a bistable circuit arrangement (3, 4, Fig. 8) to interrupt the normal program flow by an interrupt command of the command execution control unit (Ε-unit, Fig. .1) »· are seen, whereby interruptions by the Ε-unit have priority over interruptions by the I-unit, and the bistable circuit arrangements (Fig. 8). Output signals in the event of an interrupt request (EXIT, IRPT END LCH, Fig. 8) transferred to logic circuits (e.g. Fig. 9, 20, 39), which an entry of the cause of the program interruption in the old program control word (PSW), the storage this program control word, and cause the retrieval of a new program control word. ÜÜHb i2 / 13bp P 15 24 150.6 jüQ Unuii'iaQGn (Art. 7 S 1 Abs, 2 No. 1 S: -ir J ütö Äi.i <efun8ej) es. v. 4. 9.1967) 2. Device according to claim 1, characterized in »that logic circuits (Fig. 14, 16, 40 are provided, which responds to invalid memory operations and one through the I-unit interrupt switch (3, 4; Fig. 8) initiated interruption sequence into an interruption sequence change which is determined by an E-unit interruption (switches 12, 13; Fig. 8). 3. Device according to claim 1 and / or 2, characterized in that an OR gate (1; Fig. 20) is provided, whose Output signal (IRPT CYC 1 LCH) initiation of an interrupt sequence bypassing the bistable switch (Fig « 8) brings about. 4. Device according to claims 1 to 3, characterized in that a logic circuit (Fig. 19) is provided, which an output signal when machine errors occur (MCH CHK IRPT), which directly initiates an interruption sequence « 5. Device according to claims 1 to 4, characterized in that logic circuits (Fig. 28) are provided which enable the initiation of an interrupt sequence through an initial program load. Ü 0 9 8 1 27 iiSa P 15 24