DE3200042C2 - - Google Patents

Description

The invention relates to a data processing system Cache memory according to the preamble of claim 1, in particular improvements in memory access Administration in the operation of such a data processing system.

The data processing system on which the invention is based has a central unit (central processor unit), a main memory (working or central memory), which is controlled by a memory control unit, and a number of peripheral processors (the devices such as data stations, Operate printers, communication devices or the like). The data processing system also has one Cache memory. A cache is a very fast one Memory that is spatially assigned to the central unit and a time-varying subset of the content of the main memory contains.

A cache memory can be the average memory access time considerable for the central unit storage operations decrease because a very high proportion of memory read can be fulfilled by the very fast cache memory. For a smaller proportion of memory read attempts, the Operation of the central processing unit to be stopped to get the requested data from the main memory. In the described data processing system is the cache memory read directly by the central unit and is in the Cache memory by a cache write circuit on Cache miss or a central processing unit main memory Write operation written out. The peripheral processors read and write to or into the main memory via the memory control unit, but without the cache memory  to read or write in it what the central unit Operations reserved.

When operating such a cache memory occur in particular three difficulties, all of which Reduce the speed of the data processing system.

First difficulty: Although the peripheral processors do not write to cache if they are in a The cache memory must write the position in the main memory be checked to find out if the content of the subject Main memory location transferred to the cache memory has been, and if so, the cache entry be declared invalid (by setting a validity / Invalid bits in an "invalid" indicating State), since the entry is no longer exactly the content of the Main memory corresponds. That is, at a given time there may be a competitive situation between the surgery attempting to read the cache and the operation attempting to cache the content after a write operation regarding peripheral processor and main memory check (identifier check).

Second difficulty: Because the cache is not simultaneously Can be subjected to writing and reading a competitive situation between the central unit at all times, which tries to read the cache memory, and the cache write logic that is trying to cache Memory on a previous cache miss write there (to update the cache), consist. There can also be a competitive situation when the cache write logic tries to Write invalid bit after a previous one  Identification check a state of identification- Has matched.

Third difficulty: A competitive situation can arise at any time occur when the CPU tries to cache Read memory while the memory control unit is in writes the cache memory to update it after a previous letter from the central unit in the Main memory.

In known data processing systems, the cache Storage operated as follows:

• (1) Organization (overhead) time must be used to clean up the Competitive situation, especially with the first difficulty;
• (2) in cache update after a previous one The CPU must stop cache misses are during a cache cycle that is going to Updating the cache content is determined, and
• (3) the CPU must be stopped while the memory Cycles used to update the cache content are determined according to a central unit letter.

All of these competitive situations cause delays in memory access and therefore affect the operation the central unit.  

Data processing systems according to the preamble of claim 1 are also known:

• - US 42 08 716 (Porter):
  In the event of conflicts when accessing the cache memory, the shortest possible access time is guaranteed by dividing the cache memory operation cycle into two sub-cycles, and
• - FR-OS 24 19 561 (IBM):
  the cache cycle is also divided into two sub-cycles during a processor cycle.

The object of the invention is therefore in a data processing system of the type mentioned in the event of conflicts when accessing the cache memory in a new way to ensure the shortest possible access time, d. i.e., to maximize processor operation speed in cache memory, by keeping the processor secure data and instructions from the cache memory can receive during each cache operation cycle, d. i.e., a continuous flow of data and instructions to the processor is assured.

The solution to this problem according to the invention takes place through the teaching according to the characterizing part of patent claim 1.

A cache memory generally has an operation cycle of the same length as the central processing unit's memory operation microinstruction cycle. In the case of the invention Data processing system is the cache memory operation cycle in a known manner Way divided into two sub-cycles, but according to the invention mutually negative operations are assigned.  

The first subcycle is assigned to the receipt of a central processing unit memory read Request with your address.

The second sub-cycle is associated with every other type of cache operation. In particular, these are either (a) receiving an address from a peripheral Processor for checking the cache content after writing by one peripheral processor into main memory or (b) writing any data into the cache including an invalid bit after a cache check Match state or data after either a cache miss or a CPU write to main memory. In this way the Competitive situation eliminated so that organizational time does not solve the Competitive situation must be expended, and will be write operations "transparent" for the central processing unit that reads the cache memory. From the central unit as seen, the cache is always available for read operations. The CPU can continue to cache for successive CPU read microinstruction cycles regardless of that Cache content is checked "simultaneously", declared invalid or updated after central unit letter. After a cache miss, it can, though the CPU must be stopped to allow operations to continue Record a cycle earlier than without the split cache cycle would have been possible.

The memory management created by the invention is special circuit economically, which reduces both costs and space requirements.  

Advantageous embodiments of the invention are in the Subclaims specified.

With the aid of the drawing, the invention will be explained, for example explained. It shows

Fig. 1 is a simplified block diagram of a data processing system according to the invention with a data processing system,

Fig. 2, the data and address paths through the data processing system,

Fig. 3 certain features of the central unit of the data processing system,

Fig. 4-9, the formats of various data and addresses that are essential to the invention,

Fig. 10 Characteristics of the control memory,

Fig. 11 shows the master clock,

Fig. 12 basic system clock signals generated by the master clock generator of Fig. 11,

Fig. 13 shows a part of the cache memory, are provided for address functions,

Fig. 14 shows a part of the cache memory, provided for storing data,

Fig. 15, certain parts of the cache memory are provided for memory control and other control functions,

FIG. 16 parts of the circuit for memory access priority,

Fig. 17 is a cache memory circuit for generating a control signal for memory operations of peripheral processors,

Fig. 18 is a circuit of the cache memory to use certain control store signals by the cache memory,

Fig. 19 to the main memory,

Fig. 20, the cache write logic and

Represent Fig. 21-23 signal timing diagrams, the parts of the operation of the data processing system according to the invention.

The entire data processing system is shown in simplified form in FIG. 1. A data processing system 10 has a central processing unit (CP) 12 , a control memory 14 and a main clock 20 . A main memory 16 , to which access is controlled by a memory control unit 18 , is also provided. Various peripheral devices (data stations, printers, disks, tapes, message transmission devices or the like) are connected to the data processing system 10 and form the data processing system with it.

Each peripheral device has a processor called a peripheral processor. Various peripheral processors are connected to one of bus adapters 22 , which in turn are connected to the memory controller 18 . Several bus adapters can be provided. The bus adapters 22 serve to buffer between the 64-bit data lines within the data processing system and the 16-bit data lines that connect the peripheral devices to the data processing system 10 . The memory control unit 18 provides access to the main memory 16 for the central unit and the peripheral processors; it can also transmit commands from the central processing unit 12 to the peripheral processors in a manner not essential to the invention.

The central unit 12 is connected to a very fast local memory or cache memory 24 which contains a time-varying subset of the data stored in the main memory. The cache 24 is also connected to the memory controller 18 . The special cache memory used in the preferred exemplary embodiment is directly mapped and contains 32 kbytes. It uses a "write-through" strategy, that is, the cache is updated every time the CPU writes to main memory.

The cache memory 24 , the main memory 16 and the memory control unit 18 together form the physical (real) memory of the data processing system.

The data and address paths through the data processing system are shown in more detail in FIG . The central unit 12 has a 24-bit address bus 26 , which leads the address lines, which are designated with the mnemonic "MA" (for "Memory Address", memory address) 0-23 ", to the cache memory 24 . The central processing unit 12 has a 32-bit data input bus 28 which carries the data lines, designated with the mnemonic "MM (for" Main Memory "0-31"), and a 32-bit data output bus 30 , which carries the data lines, designated with the mnemonic "WD (for" Write Data "0-31").

The address lines MA 0-23 in the bus 26 are fed from the central unit 12 to the cache memory 24 , and in addition it is connected to a bus 32 , the address lines, designated with the mnemonic "BMA" (for "bus adapter memory Address ", bus adapter memory address) 0-23", from the bus adapter 22 leads. This address information is used to keep the information in the cache up to date when corresponding information in the main memory is changed by one of the peripheral processors, as will be described in more detail below.

The cache memory 24 is connected to an output address bus 34 , which leads address lines, designated by the mnemonic "CMA (for" cache memory address ", cache memory address) 0-23", to the memory control unit 18 . Furthermore, the cache memory 24 is connected to a bus 36 , which leads the address lines, designated by the mnemonic "BMAR (for" Buffered Memory Address Register ", buffered memory address register) 3-20", to the main memory 16 .

Cache 24 has a data input bus and a data output bus. The data entry bus 38 carries the data lines from the memory controller 18 , designated by the mnemonic "CAWD (for" cache write data "0-63"). The data bus 38 is used by the memory controller 18 to write data to the cache after a cache miss or upon a central unit write to the main memory, as will be explained in more detail below. The bus 38 is also used in a manner not essential to the invention to transmit data to the bus adapter 22 . The data output bus 40 carries the data lines from the cache memory 24 , denoted by mnemonic MM 0-31, as an input to the central unit 12 on the bus 28 . A data bus 40 provides data to the CPU 12 after a cache meeting upon a CPU read request, as will be described in more detail.

The main memory 16 receives the address lines BMAR 3-20 from the cache memory 24 , as previously described, via the bus 36 together with memory module select signals, which are not shown and are not essential to the invention. The main memory 16 has a 64-bit data input bus 42 which is connected to the memory control unit 18 and the data lines, designated by the mnemonic "MMWD (for" Main Memory Write Data ", main memory write data) 0-63 ". All data written into the main memory 16 are entered on the bus 42 . The main memory 16 has a 64-bit data output bus 44 which is connected to the memory control unit 18 and the data lines, designated by the mnemonic "MMRD (for" Main Memory Read Data ", main memory read data) 0-63 ". All data read from the main memory 16 are read out on the bus 44 .

The bus adapter 22 issues address bits to the cache memory 24 via the previously described bus 32 for memory access requests of the peripheral processors in a manner not essential to the invention. The bus adapter 22 has a 64-bit data output bus 46 which is connected to the memory control unit 18 and the data lines, designated by the mnemonic "BARD (for" Bus Adapter Read Data ", bus adapter Read data) 0-63 ", and a 64-bit data input bus 48 , which is connected via a buffer 50 to the bus 38 and the data lines, designated by the mnemonic" BAWD (for "bus adapter Write Data ", bus adapter write data) 0-63", leads. It should be noted that "bus adapter read data" refers to data read from the peripheral processor into main memory 16 , while "bus adapter write data" refers to data read from main memory 16 and into one peripheral processor can be written.

In addition, the bus adapter 22 issues certain control signals to the cache memory 24 . These are MRBA ("bus adapter memory request signal") and BAC 0-2 ("bus adapter control signals"). The BAC-0-2 signals are switched through in the cache memory for convenience; in their interconnected form they are called BBAC 0-2.

As already described, the memory control unit 18 receives data via the bus 44 from the main memory 16 , via the bus 46 from the bus adapter 22 or via the bus 30 from the central unit 12 . The memory controller 18 receives address data on the bus 34 from the cache memory 24 . The memory control unit 18 outputs data on the bus 38 to the cache memory 24 and to a data signal memory 50 for output to the bus adapter 22 . The memory control unit 18 also outputs data to the central unit 12 (via a switch 54 ) on the bus 52 , which identifies the data lines with the mnemonic "DIRD" (for "Diagnostic or Read Data", diagnosis or reading of data) ) 0-31, In a main memory read after a cache miss, as will be explained in more detail, an miss extended signal derived from the cache miss condition allows the data to be described in a manner yet to be described get from the bus 52 via the signal memory 54 to the bus 28 and thus to the central unit.

As evidenced by FIG. 3, only two components in the central processing unit 12 essential to the invention. These are a memory data register 56 which receives data via the lines of the bus 28 (MM 0-31) and a memory address register 58 which (not essential to the invention) is loaded with the addresses which are transmitted via the bus 26 (MA 0 -23) are to be submitted to the cache memory.

If the central processing unit is not stopped (ie if the STCP inverse signal is high; the extraction of this signal will be described below), the address signals are transferred from the memory address register 58 to the cache memory 24 at time L 0 (The clock signals including L 0 will be explained with reference to Fig. 12).

In Fig. 4-9 different formats of data and addresses are shown that are essential for the operation of data processing system.

Fig. 4 shows a data byte that has 8 bits. Fig. 5 is a data word indicates the byte 4 or consists of 32 bit. Fig. 6 shows a double word consisting of an even word and an odd word, each having 32 bits. The data are stored in the main memory as double word units.

Figure 7 shows a 24 bit physical address as seen from main memory; the address has a 12-bit page frame number (which can be expanded by two if the memory is expanded) and an 11-bit relative pointer that locates the byte within the page.

Figure 8 shows the same 24-bit physical address as translated by the cache memory; the address has a 9-bit identifier and a 12-bit index. The least significant two bits are ignored because they are used to select a byte within a word, while the cache always transfers a word to the central processing unit, which then has to select the particular byte that is sought. The third bit from the right selects the even or odd word of a double word pair.

Fig. 9 shows the format of data as it is stored in the cache memory. The even and odd words of a double word pair are stored together with the 9-bit identifier for each. This entire 72-bit unit is addressed by the 12-bit index of the physical address.

The use of an index and an identifier to address a directly mapped cache Storage is in itself in the technology of data processing systems well known. Compare to the principles of administration of cache memories e.g. B. Computer Engineering from Bell, Mudge and McNamara (Digital Press, 1978).  

Referring to FIG. 10 of the control memory 14 contains control signals, which are accessed in groups of eight signals at the output on eight parallel lines. The signal on each line can be either high (1) or low (0) and is fed directly into the hardware circuitry of the CPU 12 to control its operation.

Of the forty-eight signals on the lines that represent a microinstruction, only certain are significant. These are signals 0-6 (called "micro opcode") which are decoded as a group to give one of a number of signals indicating the operation to be performed (such as adding, moving, comparing, shifting) and signals 22 -29, which are decoded as a group to give one of a number of signals indicative of a memory operation (read or write with details of memory address register drive, memory data register drive and other non-invention operations). These signals are indicated in Fig. 2 as "memory control signals". Certain of the control signals which are accessed by the central processing unit are fed directly from the central processing unit into the cache memory and the memory control unit, as will be explained in more detail. The access to and the decoding of such groups of control signals (microinstructions) when operating a data processing system is well known per se, so that a description is not necessary here.

In Fig. 11 the relevant parts of the system master clock 20 are shown. The main clock for the data processing system is controlled by a 50 MHz crystal, the output signal of which is fed into a clock generation circuit 60 , which generates suitable clock signals for the system in a manner known per se. The basic clock signal (CLOCK) has a period of 40 ns and a 20 ns pulse duration. The signals TA, T 0 , T 1 , T 2 ; LA, L 0 , L 1 , L 2 ; CLOCK and the inverted CLOCK are shown in the signal-time diagram of FIG. 12. These pulses are entered into the central processing unit 12 .

Signals LA, L 0 , L 1 , L 2 are free-swinging, while signals TA, T 0 , T 1 , T 2 depend on the operating states in the central unit and elsewhere. Furthermore, L and T pulses can be generated under conditions to be described, but they are not shown in FIG. 11 and are also not essential to the invention.

Two touch signals GT 1 and GT 2 are generated in a manner yet to be described. The signal GT 1 samples (releases or blocks) the central unit clock signals TA and T 0 , the signal GT 2 samples the clock signals T 1 and T 2 . By definition, the CPU cycle begins with a TA pulse. Therefore, the operation of the CPU can be stopped after T 0 or after T 2 . The signal GT 2 is normally subordinate to the signal GT 1 ("slave"), but when a signal "miss" occurs GT 2 is blocked in a manner to be described below, so that the pulses T 1 and T 2 do not occur even though the pulses TA and T 1 have occurred.

The length of the central unit's microinstruction cycle varies with the type of microinstruction. The central unit cycle (of any length) begins by definition with TA. Most microinstructions, including those that involve memory operations and are essential to the invention, take 160 ns to execute. The pulses TA, T 0 , T 1 and T 2 form the cycle for these microinstructions, as can be seen from FIG . Other commands may take more than 160 ns to execute; further T-pulses must be generated for such commands (T 5 -T 8 , not shown). To determine the number of T-pulses to be generated, the control signals 0-6 (the "micro opcode") of the current microinstruction which controls the central unit 12 are output from the central unit 12 to a decoder / counter 62 together with the signal CLOCK entered into circuit 60 ; according to the type of operation as determined by the decoder, the counter is set and, at an appropriate time, the signal "COB" (end of cycle) is generated to mark the end of the instruction cycle. This signal resets circuit 60 and begins the next cycle with a pulse TA.

The CLOCK signal is fed directly into the cache 24 and the memory controller 18 , where a similar clock circuit is provided to generate synchronous L and T pulses. However, if the tactile signals GT 1 and GT 2 do not have the particular course explained above, the pulses T in the cache memory and in the memory control unit do not stop when the central processing unit is stopped.

The control memory cycle has the same length as the read or write cycle of the central unit, ie 160 ns. However, by definition it begins with the pulse L 1 and comprises the pulses L 1 , L 2 , LA, L 0 , which, as shown in FIG. 12, means that the control memory cycle is offset by 60 ns from the central unit cycle. The memory control unit cycle is offset by 40 ns from the central unit cycle and comprises the pulses T 0 , T 1 , T 2 , TA.

Furthermore, certain clock pulses from the central processing unit are input directly into the cache memory 24 so that events are synchronized with specific events in the central processing unit. Such cache events cannot occur when the CPU is stopped even though the cache is not stopped.

Referring to FIG. 13-15, 17, 18 and 20, 24 has the cache memory in principle an address part (Fig. 13), further comprising a data storage and Identifizierungskennzeichenvergleich- part (Fig. 14) and various control signal decoder (Fig. 15, 17, 18 and 20). The circuit of Fig. 16 and parts of the circuit of Fig. 15 are physically cached, but are conceptually part of the memory controller since their functions relate to the management of the main memory.

As evidenced by Fig. 18 (not shown in this figure) reaches the central processing unit address the cache memory 24 together with the control signals CM 22-29 of the 48-signal group, which controls the current central unit operation. As previously described, control signals 22-29 are memory access control signals that control the type of memory operation to be performed at the address indicated by the central processing unit. For ease of use in cache 24 , various of these signals are delayed by switching or buffering, and the delayed signals are labeled "CCM", "BCM", "LCM" or "MCM" according to their delay, as can be seen in the figure .

Referring to FIG. 16, the memory controller 18 has a circuit 140 that determines the priority of the main memory access. This circuit is designed to give main memory access priority over any bus adapter request (from a peripheral processor side). Only when there is no bus adapter memory request pending does CPU 12 gain access to main memory, either to write or read after a cache miss. The input signal LC ("Last Cycle") comes from the memory control unit clock according to FIG. 15, which will be described later, and is generated at the end of a memory access operation. Upon completion of each current memory operation, if no bus adapter memory request is pending, by default BA will go low and the waiting CPU address will be transferred to main memory 16 . Therefore, after a cache miss, there may be a delay of several cycles until the main memory is available to the central processing unit. During this time, the central unit remains stopped, as will be described.

This assignment of priority for main memory access between the central unit and the bus adapter the occurrence or absence of bus adapter memory requests, must be clearly distinguished from the division the cache cycle between central processing unit memory Reading and other operations, as more detailed below is to describe. The circuit for dividing the Cache cycle works freely and, as described, regardless of whether any request from the central unit or a bus adapter.

As evidenced by Fig. 17, a "BA-enable" signal by means of a flip-flop in an enable circuit 142 at time TA in each generated bus adapter memory request (MRBA), provided that the memory control circuit is prepared (R / B). The BA enable signal is fed into the circuit of Fig. 13 to feed the address of the BA memory operation for purposes of cache checking or invalidation procedure, as will be described.

The timing control signals (clock pulses) are largely generated by the circuit of FIG. 15, the majority of which is functionally part of the memory control unit 18 . Methods for clocking and operating a main memory for a data processing system of the type described here are generally known per se and are therefore not essential to the invention. The generation of these clock signals is therefore not described in detail here, but only insofar as it is essential to the invention.

Referring to Fig. 15, the control signals CCM 22-29 (from Fig. 18) are decoded in a decoder 138 to determine whether the central processing unit memory operation is a write or a read. If the operation is a read, the control signals, after decoding, produce a "read" signal indicating that the central processing unit memory operation is a read to be cached. This signal is required in the cache 24 to allow the generation of a cache miss signal, as will be explained.

If the central processing unit memory operation is a write (to main memory), the control signals CCM 22-29, after decoding, result in the write signals WRITE 8 (ie bits), WRITE 32 and WRITE 64, which perform the operations of writing a byte, a word or a double word. (In contrast to the peripheral processors, the central processing unit does not write a half-word; therefore the WRITE 16 signal is not generated by the central processing unit control signals.) The signals BAC 0-2 (memory access control signals) from the bus adapter 22 become similar in one Operations decoder 139 decodes to obtain read or write signals for input to circuit 138 . The bus adapter write signals can be WRITE 8, WRITE 16, WRITE 32 or WRITE 64. The MRBA (bus adapter memory request) signal is also input from the bus adapter 22 .

The CP / BA input signals (of FIG. 16) represent the priority allocation for main memory access. (CP is high if the central unit has priority; BA is high if a peripheral processor has priority.) The delete-miss- Signal is generated in cache memory 24 in a manner to be described when the cache miss by a main memory operation has been resolved and the requested data has been fed into central unit memory data register 56 ( FIG. 3). As can be seen from the figure, the signal "MOP" (store operation) represents either a bus adapter store operation (BBAC 1 , BBAC 2 and BA priority) or a central unit store operation (MCM 24 and 25 as well as CP priority) .

Circuit 138 generates appropriate memory control and clock signals from the specified input signals. The generation of the control signals "WRITE 8", "WRITE 16", "WRITE 32" and "WRITE 64" has already been described; "READ 64 B" determines the operation of reading a double word. The signal R / (read / write: R is high for read, W is high for write) and the write pulse are conventional inputs to main memory 16 . The memory clock signals include CAS (column address scan), CEN (column enable) and RAS (row address scan), all of which are conventional and are input to main memory 16 to be in itself address in a known manner.

The signals C 1 , C 2 and C 3 are intended for internal use in the cache and follow the three instruction cycles (160 ns each) required for a main memory operation. Their use is explained below. The signal LC (last cycle) is 160 ns long and is basically synchronized with the last cycle of the memory operation. Signal LC is input to reset flip-flop 141 , which delays the CP priority signal (of FIG. 16) to give a stored CP signal (LCP), the use of which will be explained. A flip-flop 137 is used to delay the cache miss signal during a CPU read operation by providing a "MISS EXT" (inverse) output signal, the use of which will be explained.

The cache miss inverse signal is typically high and typically holds the stop central processor (STCP) inverse signal issued by flip-flop 135 . The STCP inverse signal is input to the master clock ( Fig. 11); it is also entered into the central processing unit memory address register 58 ( FIG. 3). As long as the STCP inverse signal remains high, the central unit is not stopped; the clock pulses TA, T 0 , T 1 , T 2 are generated and the central processing unit memory addresses are extracted from the memory address register. When a cache miss signal is generated, in a manner to be explained with reference to Fig. 14, the cache miss inverse signal goes low and the next L 1 clock pulse (L 0 inverse is low) the output signal STCP inverse low. This signal stops the generation of T-pulses for the central processing unit and also prevents the next memory address from being switched to the cache memory.

In FIG. 13 now to be explained, that part of the cache memory 24 is shown which relates in particular to the cache addressing and the main memory addressing. This circuit divides the cache cycle and maps alternate cache sub-cycles to specific functions. The first cache sub-cycle is associated with processing a CPU read address; the second cache subcycle is associated with either processing a bus adapter read address to perform a cache check or writing to the cache. Writing to the cache may include either writing the invalid bit of a particular cache entry after a cache check (also performed in a previous cycle) shows that an identifier match condition exists, or writing to the Cache data store and tag to update cache after completing cache miss by main memory 16 or after a CPU main memory write.

The circuit of Fig. 13 receives addresses from two sources. One address (MA 0-23) is received by CPU 12 for a store operation (read or write) and another address (BMA 0-23) is received by bus adapter 22 for cache check or invalidation. Operation (resulting from a bus adapter main memory write operation) received. The circuit of FIG. 13 determines which address is to be compared in the comparator of FIG. 14 and which address enters main memory 16 for the memory operation. Basically, this circuit has multiplexers 102 and 104 to select the index and tag to be fed into the cache and comparator of Figure 14; Latches 110 and 108 store the central processor address entered for injection into main memory 16 in the event of a cache miss; and a multiplexer 112 selects the address to be entered into main memory 16 for a memory operation.

It should be noted that the circuit of FIG. 13 operates without reference to whether the CPU store operation is a read or a write. The "read" signal of Fig. 15 is input to Fig. 14 where the cache miss signal is only generated for a read operation. For a CPU write operation, all operations are performed until the cache miss signal is generated, but no miss signal is generated. Because this sub-cycle is associated with processing a central processing unit memory operation address, no other operations could be performed during this sub-cycle, so these "wasted" operations did not take time.

As further shown in FIG. 13 can be seen, the bus of the central processing unit 26 address lines MA 0-23 from the memory address register 58 12 (Fig. 3) that is locked in L 0, the central processing unit unless stopped is (STCP- Inverse is high). The bus 32 leads address lines BMA 0-23 from the bus adapter 22 . The address of the bus adapter 22 is stored in a signal memory 100 which (at the time TA) is switched through by the BA enable signal from FIG. 17.

Lines 9-20 (which carry the signals corresponding to the index, cf. FIG. 8) are fed from the incoming central unit address bus 26 to the input of the index selection multiplexer 102 , whereas lines 0-8 (corresponding to the identifier) are supplied , see FIG. 8) the input of the identifier dial multiplexer 104 . The incoming adapter address bus 32 is passed through the buffer 106 , which is released by the bus adapter 22 by a signal "BA WRITE" (BBAC 1 ) and is then divided in a similar manner: lines 0-8 (corresponding to the identifier) go to the identifier select multiplexer 104 , lines 9-20, on the other hand, to the index select multiplexer 102 .

The inputs to multiplexer 102 are selected by clock signal T 12 , while the inputs to multiplexer 104 are selected by clock signal T 12 -inverse. Thus, the multiplexers 102 and 104 are switched simultaneously, but in the opposite sense; the CPU index is transmitted by multiplexer 102 when the bus adapter identifier is transmitted by multiplexer 104 . From the signal-time diagram of Fig. 12 it can be seen that T 12 is high during T 1 and T 2 ; therefore T 12 is an 80 ns pulse.

Multiplexers 102 and 104 are thus switched twice during each cache access (160 ns). During the first half of the cycle, the A (central unit index) inputs are transferred to the index select multiplexer 102 to the cache address latch 114 ; the B inputs are transmitted during the second half of the cycle. The B inputs can be either the bus adapter address from buffer 106 for a cache check (at BA priority while a peripheral processor is writing to main memory); the same bus adapter address (stored in buffer 106 ) for invalidation bit writing (after a previous cache check resulted in an identifier match condition); or a previously entered CPU address (from latch 108 ). The previously entered CPU address is either one for a read operation that caused a cache miss or one for a CPU write operation; in both cases the address must now be used as the address for a cache update-write operation.

During the first half of the cycle, the B inputs are transmitted to the tag select multiplexer 104 to select an tag latch 116 to drive the tag comparator ( Fig. 14); during the second half of the cycle, the A inputs to multiplexer 104 are transferred to latch 116 . The purpose of this timing arrangement will be explained below.

The cache address latch 114 is latched by the "address clock" signal (L 1 LA); the dial tag latch 116 is latched by the "on tag clock" signal (L 1 LA inverse).

For each main memory operation (including updating the cache after a miss), an address to be fed into main memory 16 must be selected for the memory operation. For each CPU operation, whether a store operation or other operation, the CPU address (MA 0-23) is latched through by latch 110 through clock signal T 2 (provided CPU 12 is not stopped and GT 2 is high) and fed to main memory address multiplexer 112 and latch 108 . If the operation is not a store operation or a store read and there is a cache hit, the contents of latch 108 are never used. If there is a cache miss, the signals CP (CPU memory access cycle of Fig. 16), T 1 and C 1 (of Fig. 15; cycle 1, the first cycle of the memory operation to meet the misses) switch. the address through latch 108 to multiplexer 102 to index the file location in cache data store 124 for the update write after the memory cycle is complete. The tag portion of the address is output as TW0-8 for writing to the cache, as will be explained.

Since the central processing unit is paused for a cache miss after the clock interval T 0 of its cycle, it may have already (during TA, T 0 ) given another address to the cache for a memory read before going through the cache - Missing signal has been stopped (as will be described). This address is not lost because it is retained in latch 110 , which is not gated before the next T 2 clock signal after the cache miss signal has been cleared. Therefore, during a main memory operation to meet a cache miss, latch 110 stores the address for the next store operation, while latch 108 stores the address that caused the miss and is just being entered into main memory for the current operation has been. When the store operation has finished and the data is to be written to the cache, the index for writing to the cache is obtained from the cache address latch 108 . The identifier is issued as TW0-8 (identifier writing) to be written into the cache identifier memory 120 at the same time.

The alternate inputs to main memory address multiplexer 112 are selected by the BA (high or low) signal from the priority circuit of FIG. 16. The selected address signals (BMAR 3-20) with module selection signals not essential to the invention are output in order to address the main memory 16 ( FIG. 19) and the memory control unit 18 (DMA 0-23). The memory control unit uses the address signals to maintain a bus transaction log and for other purposes that are not essential to the invention.

It now will be explained in Fig. 14, showing the memory portion of the cache memory. Fig. 14 is to that extent simplified, the actual division is not shown of the cache memory in odd and even part than what is operably not essential to the invention. In fact, only half of the memory part is shown. To imagine the even / odd arrangement of the cache memory, Fig. 14, except for flip-flop 130 , can be thought of as representing either the even or the odd part of the cache memory; the remainder would then be formed by other similar circuitry, not shown, the output of which is also input to the 1-bit flip-flop 130 to provide a single cache miss signal.

Data memory 124 is a random access memory (RAM) that stores the cache entries, while tag memory 120 stores the associated 9-bit tags and invalidate bit memory 122 stores the associated invalid bits. The assemblies 124, 122 and 120 are all addressed by the 12-bit index from the cache address latch 114 ( FIG. 13) into which the "address clock" timing signal (L 1 LA) is input ( Fig. 13). The identifier portion of the cache entry is read into an identifier latch 134 . The word portion of the cache entry is simultaneously read into a data latch 126 .

The tag latch 134 is controlled by the "tag latch enable" signal (timing signals L 0 + L 2 with the pulse trailing edge active) to transfer the stored tag to an tag comparator 132 . The address identifier part, which is controlled by the multiplexer 104 , represented as CWA 0-8, is in the identifier comparator 132 from the signal memory 116 ( FIG. 13) by the signal "in identifier clock" (L 1 LA- Inverse) entered for a comparison. The comparator miss / hit output is low if the identifiers are the same or high if the identifiers are not. This output signal is input to a 1-bit flip-flop 130 which is output by the "miss clock" (LA inverse) signal for a CPU read-only operation, as indicated by the "read" signal of FIG controlled. 15,. No cache miss or cache miss inverse signal is generated in a CPU write or BA address subcycle. The miss / hit bit from comparator 132 is ORed with the stored invalid bit from memory 122 before it is input to flip-flop 130 . Therefore, in a CPU read, either a no match status or an invalid bit results in a cache miss represented by the cache miss signal (status signal).

The miss / hit signal is fed into flip-flop 137 of FIG. 15, as previously described, which produces an "extended miss" inverse signal (only during a read operation).

The data from data memory 124 is switched from data latch 126 through the "data latch enable" signal (L 1 L 2 ) to buffer 128 . If the identifiers are the same and the bit from memory 122 indicates that the entry is valid, then the data from buffer 128 goes directly on bus 40 to memory data register 56 of CPU 12 ( Fig. 3); the extended miss inverse signal from flip-flop 137 enables latch 54 ( FIG. 2) and blocks buffer 128 .

The miss / hit bit from tag comparator 132 is also input to set flip-flop 146 . During a subsequent cache cycle, as will be explained in more detail with reference to FIG. 22, the invalidate output signal is fed into the data in port of the cache invalidate memory 122 to be currently being fed into the memory from the cache address latch 108 Address to be registered.

Since the data latch enable signal is only high during the first cache operation cycle sub-cycle, no data is sent to CPU 12 during the second sub-cycle for cache check, invalidate write, or cache data write - Operation switched through.

Referring now again to FIG. 11 received, after which, as already described, the cache Verfehlen- signal holding the central unit by inverting GT 2, which the timing pulses T 1 and T 2 is turned off. The central unit is therefore stopped after the timing pulse T 0 . If no bus adapter requests main memory access, the priority circuit of FIG. 16 generates the CP / (BA inverse) signal. The cache miss can be addressed immediately.

In order to meet the CPU read request in the event of a cache miss, the module drive bits (not shown) and the address signals BMAR 3-20 (of FIG. 13) are combined into main memory 16 ( FIG. 19) with the timing and control signals of Fig. 15 to select the addressed double word. Three instruction cycles are required to complete main memory access. The double word is passed through memory controller 18 on bus 44 and then entered on bus 52 into CP data latch 54 ( FIG. 2); the extended miss signal switches the data into the memory data register 56 ( Fig. 13).

The cache miss signal is cleared ( Fig. 14) at L 0 when the memory clock circuit of Fig. 15 has determined that the last cycle of the three required main memory operation cycles has been reached for a memory read. Operation belonging to the central processing unit (LC, LCM 24 and LCP; LCM 24 is the switched-on memory control signal CM 24 of FIG. 18, which is always high for a read operation). These input signals are collectively called the "miss erase" signal, which is also input to the circuit of Fig. 15 where it erases the read signal.

In response to the cleared cache miss signal (miss inverse goes high), the "STCP"("Stop Central Processor", ie stopping the central unit) is inverted at L 0 (flip-flop 135 , FIG. 15). It should again Fig. Tightened. 11 When the miss-inverse signal goes high, GT 2 allows the pulses T 1 , T 2 to be delivered to the central unit, which cause the central unit to restart in the middle cycle. GT 1 then allows the pulses TA, T 0 to be output. The CPU then continues to operate until another cache miss signal occurs (unless a write main memory operation occurs but is not essential to the invention).

More specifically, cf. now the time signal diagram of Fig. 23, the signal STCP inverse is normally high. It goes low either in the case of a CPU write to main memory, not described here, or upon the miss signal from flip-flop 130 ( FIG. 14), as shown in FIG. 15. The STCP inverse signal goes low at time L 1 . Is evidenced by Fig 11, the signal STCP inverse the input signal of the flip-flop 61 for erasing GT. 1; if the signal STCP-Invers goes low, the signal GT 1 -Invers is also lowered, so that the next pulses TA, T 0 to the central unit 12 are blocked and the signal GT 1 goes high.

In the absence of the cache miss signal (ie, in the case of a CPU main write operation), the GT 1 signal is input to D of the GT 2 flip-flop 63 ; then, at the next pulse L 0 , the signal GT 2 inversely low, so that the next pulses T 1 , T 2 to the central unit 12 are blocked. When the STCP inverse signal goes high again (after the write operation has been initialized) at pulse L 1 , the GT 1 inverse signal goes high at pulse L 2 (the timing pulses TA, T 0 are passed) and becomes the signal GT 2 inversely high at the next pulse L 0 (the timing pulses T 1 , T 2 are passed). Therefore, in the case of main memory writing, the central processing unit 12 is stopped at TA and started up again at this pulse.

If the central processing unit stops due to a cache miss, the cache miss signal is not generated until L 0 , in the middle of the pulse TA. Therefore, a different stop time (and resumption time of the operation) must be provided in this case. For this purpose, the cache miss inverse signal is ANDed with GT 1 for input to D of the GT 2 flip-flop 63 , and the cache miss inverse signal is also ANDed with the GT 2 inverse. Output signal of the flip-flop 63 . Therefore, the switching signal GT 2 goes high when the cache miss-inverse signal goes low, so that the pulses T 1 and T 2 are inhibited and the CPU is stopped in the middle command cycle. The GT 1 inverse signal is then made low (at L 1 ) by STCP.

After the cache update is finished writing to the cache data memory (as will be explained) at time TA of the second cache sub-cycle within the last main memory cycle, the cache miss signal is cleared by the flip-flop 130 ( Fig. 14). The signal cache miss inverse goes high at L 0 ; the STCP inverse signal goes high at L 1 ( Fig. 15). The transition of the cache miss-inverse signal makes the GT 2 signal low at L 0 so that the timing pulses T 1 , T 2 can be delivered to the CPU 12 ; then the signal GT 1 inversely high at L 2 so that it passes the pulses TA, T 0 . The CPU command cycle therefore continues in the middle cycle where it left off.

The cache memory is updated after a cache miss or during a central unit Main memory write operation by a write Cache operation.

Fig. 20 will now be explained. The cache write circuit 150 controls the writing of the cache content after a cache miss and also controls the reading of the cache invalid bit after an identifier match on a BA address comparison. To write the invalid bit, the invalid (inverse) bit (from flip-flop 146 , Fig. 14) is input to circuit 150 . The control signals LCM 24 and MCM 24 as well as the write control signals WRITE 8, WRITE 16, WRITE 32 or WRITE 64 (from FIG. 15) are input for writing into the cache memory data memory.

The write to the cache memory is done at different times for a main memory write or read operation, as shown in FIG. 23. All write operations occur at time TA, that is, during sub-cycle B of the cache operation cycle. For a main memory write operation, the write pulses are given at the time TA of the memory cycles C 1 and C 2 ( FIG. 15), while for a main memory read (update of the cache memory) the write pulse is given at the time TA of memory cycle 3 (LC, last cycle) is released. Invalid bits are also written at time TA during each cycle of the main memory cycle. Because all writes occur during the second subcycle of the cache operation cycle, the cache write operations cannot interfere with the acceptance of a CPU read request during the first cache subcycle.

The write cache pulses are input to tag memory 120 , invalidate memory 122, and data memory 124 ( Fig. 14) when appropriate.

The assignment of the cache sub-cycles to specific ones Functions as described, in particular the assignment of the first subcycle, assuming only one CPU read request, entails that a central processing unit address for a memory read Operation is always accepted, once in each Cache cycle to its identifier to compare with the cache content. If a cache If there is a meeting, the requested ones Data on the central unit within the period TA of the next CPU microinstruction cycle left behind. The central unit can therefore continue to work without a break.

If there is a cache miss, the central processing unit stopped and there may be several Cycles waits for them to access main memory receives, which only occurs if no bus adapter has access  demands. When the data is received from main memory , they are immediately fed to the central unit, and during the second subcycle of the cache cycle, and when the central unit starts up again because that Cache Missing Inverse signal starts high the central unit in an operational phase, like when there was a cache meeting. In the cache Data storage is made during the second cache Subcycle registered after the central unit has started again.

The cache is checked for bus adapter tag matches only during a second subcycle of the cache operation cycle. In an identifier match state, flip-flop 146 is set, and in the next second sub-cycle (after the CPU has had an opportunity to enter a read memory request), the invalidate bit at the match address is cleared by the cache write. Logic 150 ( Fig. 20) is written. Each subsequent attempt by the CPU to read the cache location results in the generation of a cache miss signal and the cache is updated as explained.

As a result of this allocation of cache operation sub-cycles is the cache write (either writing an invalid bit, updating a double word for a cache miss, or updating the cache memory after a central processing unit Main memory write) "transparent" for the read Central unit memory operations. The central unit never have to wait while writing takes place. In particular, in contrast to many data processing systems with a cache memory no "allocated"  Cache cycle to update the cache Memory required after a cache miss, before the central unit starts operating again can. In addition, the central unit can immediately read a file location (on your next microinstruction cycle), which just updated after a cache miss has been. If the central unit tries to read a file location that is just the file location of a Main memory write operation can become anomalies occur, however, easily by taking suitable precautions avoided when micro-programming the central unit can be.

The operation of the data processing system according to the invention will now be explained with reference to the signal-time diagrams of FIGS. 21, 22 and 23.

First, reference is made to Fig. 21 which shows the events of a CPU read / store operation.

The central processing unit read-memory microinstruction begins at time TA and lasts up to and including T 2 . On the positive edge of LA inverse, the address is made available to cache memory 24 by memory address register 58 ( Fig. 3). While T 12 is low, the A inputs of index multiplexer 102 ( FIG. 13) are driven so that the central unit index arrives at the cache address latch 114 . The "address clock" (L 1 , LA) goes high at L 1 and transfers the central processing unit index from latch 114 to address the cache memory portion ( Fig. 14). In response, data is output from data store 124 and gated through from data latch 126 during L 1 , L 2 (80 ns). This data is switched into the central processing unit memory data register 56 ( FIG. 3) at TA. In the event of a cache hit, the CPU continues with its next microinstruction cycle without a pause.

When T 12 goes high, T 12 inverse goes low, and the A inputs (central unit identifier) of the dial identifier multiplexer 104 are selected and transferred to the dial identifier latch 116 . The "one identifier clock" (L 1 inverse, LA inverse) switches the identifier to comparator 132 ( FIG. 14). The stored identifier is released from the identifier memory 120 at the same time as the stored data, in response to the entered index from the latch 114 ; the negative-going edge of the "identifier-latch enable" signal (L 0 , L 2 ) transfers the stored identifier to comparator 132 . The miss-hit output of comparator 132 is input to flip-flop 130 , sampled LA inverse ("miss clock"). In the event of a cache miss, the cache miss signal input to flip-flop 132 ( FIG. 15) causes the STCP signal to be inverted at L 0 inverse.

As can be seen from Fig. 21, the cache miss signal is generated only after the cache data has already been transferred to the central unit 12 memory data register. If there is no missing, the central processing unit continues to work with this data. If a miss occurs, the CPU is stopped after T 0 (as will be explained with reference to Fig. 23); the data is replaced by the main memory read operation before the central unit resumes the operation.

Referring now to Figure 22, the cache checking and invalidation operations are shown. These operations are only triggered when an operation of a bus adapter (peripheral processor) is written to the main memory. For such an operation, the bus adapter outputs the MRBA signal to the circuits of FIGS . 16 and 17, which generate the BA priority signal and the BA enable signal. The BA release signal goes high at TA. A main memory operation is triggered by the circuit of Fig. 15 starting with cycle 1 (C 1 ) at T 0 . The memory access control signal BAC 1 is turned on as BBAC 1 when the memory operation begins. When T 1 , T 2 is high, the B inputs (BA index) of multiplexer 102 are selected and switched through to the cache address latch 114 . The "address clock" (L 1 , LA) outputs the BA index to the cache memory section ( Fig. 14). No data is transferred to the central unit.

The B inputs (BA identifier) of multiplexer 104 are selected when T 1 , T 2 inverse goes up; the BA identifier is transferred to the dial identifier latch 116 . The "one identifier clock" (L 1 inverse, LA inverse) switches the identifier through to the comparator 132 . The stored identifier is switched from the identifier latch 134 through the "Identifier latch enable" signal (L 0 , L 2 ) to the comparator 134 . The miss / hit bit is input to invalidation flip-flop 146 ( FIG. 14) which is sampled by the "invalidation clock" at L 2 . In the event of an identifier match condition, the INV inverted (usually high) output signal goes low.

The INV inverse signal is input to the cache write circuit of Fig. 20 where it causes a write cache pulse to be asserted at TA. The output signal INV of the flip-flop 146 is the data input signal of the invalid bit memory 122 ( FIG. 14) when the write cache pulse is input. The address at which the signal INV is written is the same address at which the identifier match state was determined, since the address in the buffer 106 is maintained during the entire BA main memory write operation (no further BA- Address can be entered until the store operation is complete, which may be the case after a few cache operation cycles). The invalidation write operation can in fact be repeated during each cache cycle at the entire time of the main memory operation, which causes no problems. It should be noted that throughout the BA main memory operation, including the invalidate write operation, the CPU continues to have the opportunity to read the cache every cycle of the cache. If any of the CPU read operations result in a cache miss, the CPU must be stopped until the BA main memory operation is complete; if no other BA memory operation is pending, then the central processing unit is given memory priority by the circuit of Fig. 16 and main memory read and cache update can proceed.

Referring now to Fig. 23, the cache miss and update events are shown. The cache miss inverse signal goes low at L 0 ( Fig. 14); the STCP inverse signal goes low at L 1 ( Fig. 15). The central processing unit 12 is stopped after T 0 . The main memory operation is triggered with cycle 1 (C 1 ) at T 0 . The main memory operation involves three cycles; memory is written during cycles 1 and 2 and read during cycle 3. The cache write pulse to update the cache memory portion after a miss is generated during the last cycle (C 3 ) because the main memory must be read before the cache memory portion can be written. The cache miss-inverse signal goes high again at L 0 during the last main memory cycle; the STCP inverse signal goes high at L 1 . The central unit starts again at pulse T 1 .

For a CPU write, the cache write pulses at TA are issued during cycles 1 and 2; the CPU will restart after the store operation has started. The CPU 12 can therefore read the cache memory during each sub-cycle A, while the write cache operation continues during the sub-cycle B.

It is also expressed in the disclosure of the invention included the summary.

Claims (7)

1. Data processing system ( 10 ) ( Fig. 1) with

• - a main memory ( 16 )
  • - for data with commands for controlling plant operations,
• - a processor ( 12 ) for data processing,
• - A cache memory ( 24 ) with
  • - a storage unit
    • - For the copy of part of the data in the main memory ( 16 ) and
  • - a cache control unit and
• - a memory control unit ( 18 ),

characterized in that

• - The cache memory ( 24 ) has:
• - a cache facility with
  • - the storage unit
    • - for copying part of the data in the main memory ( 16 ),
  • - The cache control unit, trained for
    • - Receive read and write requests from the processor ( 12 ) and
    • - Delivery of addresses according to certain requirements to the memory control unit ( 18 ), and
  • a cache transmission unit,
    which is responsive to the operation of the cache controller for data transfer from the memory controller ( 18 ) to the cache memory ( 24 ) and from the cache memory ( 24 ) to the processor ( 12 ), and
• - The memory control unit ( 18 ) has:
  • - a control unit control unit that
    • - Responds to the addresses for emitting output signals for controlling the operation of memory control unit ( 18 ), cache memory ( 24 ) and main memory ( 16 ), and
    • - Has a clock ( 20 )
      for a cache operation cycle with first and second sub-cycles, and
  • - A control unit transmission device for transmissions from
    • - Read data from the main memory ( 16 ) into the cache memory ( 24 ) and
    • - Write data directly from the processor ( 12 ) into the main memory ( 16 ), and
• - The cache control unit and the control unit control unit
  • - Respond to the clock ( 20 )
    • - for accepting only read requests from the processor ( 12 ) during the first sub-cycles and
    • for accepting and resolving competitions between all other cache and store operations requests during the second sub-cycle.

2. Installation according to claim 1, characterized in that the cache control unit responds to a data write request received by the processor ( 12 ) during a first sub-cycle for delivery of a corresponding write address to the memory control unit ( 18 ) for triggering a data write operation of the processor ( 12 ) directly from the processor ( 12 ) into the main memory ( 16 ) via the memory control unit ( 18 ) during a subsequent second subcycle. 3. Installation according to claim 1, characterized in that the cache control unit responds to a read request received by the processor ( 12 ) during a first subcycle of data not contained in the copy in the cache memory ( 24 ) for the purpose of issuing a corresponding read Address to the memory control unit ( 18 ) for triggering a corresponding read operation from the main memory ( 16 ) and via the memory control unit ( 18 ) into the cache memory ( 24 ) during a subsequent second subcycle. 4. Plant according to claim 3, characterized in that the control unit transmission device has:
a device responsive to the operation of the control unit control unit, also for direct transmission of the data read in the corresponding read operation from the main memory ( 16 ) into the cache memory ( 24 ) to the processor ( 12 ). 5. Plant according to claim 1,

• - With at least one peripheral processor, characterized in that
• - The cache memory ( 24 ) has:
• - in the cache control unit
  • - A device which responds to peripheral processor read / write addresses, for issuing peripheral processor addresses to the memory control unit ( 18 ), and
• - In the control unit transmission device, a device for data transmission between the peripheral processor and main memory ( 16 ), and
• - The control unit control unit responds to peripheral processor addresses for corresponding data transmission between the peripheral processor and main memory ( 16) .

6. Plant according to claim 5, characterized in that

• - the cache control unit responds to peripheral addresses relating to data in the cache memory ( 24 ),
  for outputting an output signal to the control unit control unit in order to initiate the reading in of a new copy of the data from the main memory ( 16) into the cache memory ( 24 ).