DE1188123B - Electronic encryptor with an arrangement that delivers each plaintext letter to be encrypted in the form of a group of binary signals - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

H04k

German class: 21 al-21

Number:
File number:
Registration date:
Display day:

C 29023 VIII a / 21 al
January 29, 1963
March 4, 1965

The invention relates to an electronic encryptor with an arrangement which each to encrypting plain text letters in the form of a group of binary signals, one electronic Key generator for generating key letters in the form of groups of binary Signals, consisting of binary main counters, scrambling arrangements with logical decryption circuits, which are connected to the outputs of the main meters, with permutator circuits, which are connected to the outputs of the decryption circuits, and with OR circuits, which are connected to the outputs of the permutator circuits, from binary auxiliary counters that are connected to the outputs of the OR circuits are connected, and from a clock generator for further switching the main counter and the auxiliary counter, and with a computing arrangement which consists of the plain text letters signal groups representing and from the signal groups representing the key letters the ao forms encrypted letters in the form of groups of binary signals.

Such electronic encryptors, which correspond to an older proposal, are particularly suitable for the encryption of clear messages in the form of binary encrypted signal groups, for example Telex characters are available. The key generator generates a sequence of key letters with such a long repetition period that it can be considered almost accidental. The encryption the plain text letters are made in that the arithmetic system according to a predetermined Law assigns certain key letters to the plaintext letters, which are then transmitted. For example, during each encryption cycle for a plaintext letter from the sequence of the key letter a key alphabet is selected, and the plain text letter is replaced by the Key letter encrypted, which takes the same place in the key alphabet as the plain text letter in plain alphabet. The decryption on the receiving side takes place with a principle similar arrangement, the key generator of which generates the same sequence of key letters.

Such encoders give a very high decipherability because the structure of the key generators ensures that the sequence of key letters has an extraordinarily long period, although each of these key letters is only represented by a group of binary signals with a small number of digits, for example five digits at Telex characters. The auxiliary electronic encryptor with a
Arrangement which each to be encrypted
Provides plain text letters in the form of a group of binary signals

Applicant:

CSF-Compagnie Generale de Telegraphic
sans FiI, Paris

Representative:

Dipl.-Ing. E. Prince,

Dr. rer. nat. G. Hauser and Dipl.-Ing. G. Quieter,

Patent attorneys,

Munich-Pasing, Ernsbergerstr. 19th

Named as inventor:
Jean Pierre Vasseur, Paris

Claimed priority:

France January 31, 1962 (886467)

counters have the effect that the key letters are generated with practically the same probability in the Episode appear.

Nevertheless, with this older encryptor, the sequence of the key letters is completely through the internal structure of the key generator set what is in the face of modern deciphering methods is not cheap.

The aim of the invention is to further increase the decipherability of an encryptor of the specified type Art.

The trained according to the invention electronic encryptor contains a logic circuit which forms groups of binary signals from the signal groups representing the plain text letters, which in conjunction with the scrambler outputs and the clock signals control at least a part of the binary auxiliary counter in such a way that each generated key letter depends on one or more of the preceding plaintext letters.

In the case of the encryptor designed according to the invention, the sequence generated depends on the key letters except for the internal structure of the keystone »517/151

generator also depends on the plain text previously transmitted. Because this plain text is completely arbitrary and is unpredictable, the result is a practically completely random sequence of the key letters, as a result of which the decipherment is made almost impossible.

The invention is explained by way of example with reference to the drawing, which is a block diagram of a according to the invention executed Encoder shows.

This encryptor contains a key generator consisting of binary main counters C ₁ to C ₅ , a first stage of scrambling arrangements ^ ₁ to A ₆ , the structure of which will be explained later, a first stage of binary auxiliary counters K ₁ to K ₆ , a second stage of scrambling arrangements A ₁ to A ₉ , a second stage of binary auxiliary counters K ₁ to K ₉ and an arrangement A ₁₀ , the structure of which will also be explained later and which, in the embodiment described here, supplies five-digit binary key letters to an arithmetic unit. The encryptor also contains a memory M, which supplies the arithmetic unit B with plain text letters in the form of five binary digits , a decryptor D to which these five binary digits are fed, a pennutator P, four logical OR circuits O ₁ to O ₄ and a clock H .

The binary main counters C ₁ to C ₅ are incremented under the effect of a first periodic pulse train which are supplied by the clock generator H and are denoted by I _c. The binary digits tapped at the individual levels of the counters are divided into six groups, as indicated in the drawing by a few connections. Each of these groups is fed to one of the scrambling devices.

These scrambling arrangements can contain OR circuits (which are not shown here are), which have the task of reducing the number of outputs of the scrambling devices (which in the example shown have three outputs for four inputs), which increases the decipherability is enlarged.

Each of the binary auxiliary counters K ₁ to K ₈ has only one input to which one, two or three incremental pulses (I _Kl , I _K2 , I _K3 ) are fed by the clock generator H , depending on the excited output of the scrambling arrangements A ₁ to A ₆ . AND circuits, not shown, distribute the incremental pulses and the output pulses of the scrambling devices to the counters, so that a specific counter is only incremented when it is simultaneously supplied with an output signal from a scrambling device and an incremental pulse coming from the clock.

This ensures that the output signals of all auxiliary counters occur with the same probability.

The second stage of scrambling arrangements A ₁ to A ₉ and the second stage of binary auxiliary counters K ₁ to K ₉ work in the same way, and it can be shown that this gives an equal probability for pairs of output signals from these last counters, i.e. ultimately an equal probability for pairs of two consecutive key letters at the output of the key generator.

In a corresponding manner, μ levels of binary auxiliary counters can be used, whereby an equal probability is obtained for groups of η consecutive key letters at the output of the key generator. The arrangement A ₁₀ can contain various logical decryption circuits, permutation circuits, logical encryption circuits, OR circuits and so on. Since this arrangement does not form part of the invention, it is not explained in more detail here.
For the same reason, the arithmetic unit B is not explained in more detail, the structure of which is apparent to a person skilled in the art and which has the task of generating _{encrypted letters at the outputs C 1} to C ₅ based on the plain text letters coming from the memory M and those from the arrangement A. _{Deliver 10} upcoming key letters.

The main feature of the invention is that the switching of one or of several of the binary auxiliary counters are made dependent on the preceding plaintext letter.

In the example shown, this principle is only applied to the counter K ₇ . The outputs of the three OR circuits O ₁ , O ₂ and O ₃ are connected to three outputs of three OR circuits, not shown, which in turn are connected to the inputs of the aforementioned AND circuits. The three other inputs of these OR circuits are connected to three outputs of the scrambling arrangement A ₇ .

During normal operation, the incrementing of the counter K ₁ takes place as a function of the coincidences between the incremental pulses and the output signals of the scrambling arrangement A ₇ , which is determined in the AND circuits. At the end of the encryption cycle for a plain text letter, the circuit O ₁ , 0 ₂ or O ₃ supplies a pulse which causes an additional increment of the counter K ₁ through coincidence between this pulse and one of the groups of incremental pulses.

It is thereby achieved that each key alphabet generated by the key generator during an encryption cycle by one or depends on several of the preceding plaintext letters, which significantly increases the decipherability.

It can be seen that this property of the establishment is obtained in a very simple manner.

In the case of the decryptor, the initial phase is carried out in the same way before decrypting a letter changed by one or more of the auxiliary counters by the previously deciphered plain text letters. Obviously, when a transmission error occurs, the decrypted plaintext letter is not more right.

At the beginning of the decryption of the following letter, the initial state is then that of the auxiliary counters affected by the additional increments are generally no longer correct, and that the same also applies to the key alphabet generated by the key generator. The following deciphered The letter is therefore also wrong, and the resulting error continues to call for a particular one Wrong decryption.

Since during this period in which the decryption is wrong, the decrypted letters and the additional increments given to the auxiliary counters at the end of each decryption cycle are random

occur, one obviously finally comes to the state that at the beginning of the decryption of a letter the relevant auxiliary counters are in the correct position, d. H. the same position that they would have if no transmission error had occurred. From that moment on, the Decryption correct again, and the disturbance caused by the transmission error has disappeared.

The probability calculation also shows that an increase in the decipherability of the described System (i.e. an increase in the period and randomness of the generated key) is accompanied by a proportional increase in error sensitivity. So you can for any case choose the most favorable compromise.

The simplest way to apply the principle explained above is that the plaintext letters can be divided into four groups, which have approximately the same probability and additional groups Cause increments by zero, one, two or three steps on one of the auxiliary counters.

With regard to the encryption, it is not a matter of indifference whether the counters K ₁ to K _{e of} the first stage or the counters K ₇ to If _{9 of} the second stage are acted upon, because the last-mentioned counters are incremented under the influence of the first-mentioned counters. The action on the counters K ₁ to K ₆ results in greater confusion of the key alphabet, but also greater sensitivity to errors.

In principle, it would also be possible to act on the main update counter, but then the The propagation time of a fault is extremely long.

If you want to act on two auxiliary counters K , you can subdivide the plaintext letters in two different ways into four roughly equally probable groups, each of which causes the counter concerned to be incremented by zero, one, two or three steps, and this process can be omitted can also be generalized to the case that one wishes to act on an arbitrary number of counters K.

Finally, if a certain amount of effort is accepted, it is also possible to store the last two plain text letters and to use these stored values to determine the additional increments of one or more counters K.

Claims (4)

Patent claims: 1. Electronic encryptor with an arrangement that supplies each plaintext letter to be encrypted in the form of a group of binary signals, an electronic key generator for generating key letters in the form of groups of binary signals, consisting of binary main counters, scrambling arrangements with logical decryption circuits that are connected to the outputs of the main counters, with permutator circuits that are connected to the outputs of the decoding circuits, and with OR circuits that are connected to the outputs of the permutator circuits, from binary auxiliary counters that are connected to the outputs of the OR circuits, and from a clock for advancing the main counter and the auxiliary counter, and with a computation arrangement, which from the signal groups representing the plain text letters from the signal groups representing the key letters, the encrypted letters in the form of groups en of binary signals, characterized by a logic circuit (D ₃ P, O ₁ to O ₄ ), which forms groups of binary signals from the signal groups representing the plaintext letters, which in connection with the output signals of the scrambling circuits (^ ₁ to A ₉ ) and the signals of the clock generator (H) control at least a part of the binary auxiliary counters (K ₁ to K _a ) in such a way that each generated key letter depends on one or more of the preceding plain text letters. 2. Encoder according to claim 1, characterized in that a second stage of binary auxiliary counters (K ₇ to K ₉ ) via a second stage of scrambling arrangements (A ₇ to A ₉ ) to the outputs of the first stage of binary auxiliary counters (K ₁ to K ₆ ) is connected and that the signals generated by the logic circuit (D, P, O ₁ to O ₄ ) act on at least one auxiliary counter (K ₇ ) of the second stage. 3. Encoder according to claim 1 or 2, characterized in that the logic circuit contains a decryption circuit (D), the inputs of which are supplied to the signal groups representing the plain text letters, that a permutation circuit (P) is connected to the outputs of the decryption circuit (D), that to the outputs of the permutation circuit (P) OR circuits (O ₁ , O ₂ , O ₃ , O ₄ ) are connected, and that the outputs of the OR circuits (O ₁ , O ₂ , O ₃ , O ₄ ) with at least some outputs of OR circuits in the scrambling arrangements (A ₁ to A ₉ ) are connected. 4. Encoder according to claim 3, characterized in that in each case an output of the OR circuits (O ₁ , O ₂ , O ₃ , O ₄ ) and an output of the OR circuits of the scrambling arrangements is connected to an input of an AND circuit, the other input of which is connected to an output of the clock generator (H) and the output of which is connected to the input of one of the auxiliary counters (K ₁ to K ₉ ) . 1 sheet of drawings 509 517/151 2.65 © Bundesdruckerei Berlin