DE102020105581A1 - ONE-TIME PROGRAMMABLE MEMORY - Google Patents

Abstract

Various one time programmable (OTP) memory cells are disclosed. An OTP memory cell contains an additional doping region that extends at least partially under the gate of a transistor such as an antifuse transistor. The additional doping area provides an additional current path for a read current. Alternatively, an OTP memory cell contains three transistors; an antifuse transistor and two selection transistors. The two selection transistors can be configured as a cascaded selection transistor or as two separate selection transistors.

Description

BACKGROUND

Many modern electronic devices contain electronic memory. Electronic memory is a device configured to store bits of data in respective memory cells. A memory cell is a circuit configured to store a bit of data, typically using one or more transistors. One type of electronic memory is one-time programmable memory (OTP). An OTP memory is a read-only memory that can only be programmed (e.g. written) once.

Figure list

• 1 ein Blockdiagramm einer Speichervorrichtung veranschaulicht, in der Aspekte der Offenbarung gemäß einigen Ausführungsformen praktiziert werden können;
• 2 ein schematisches Diagramm einer ersten OTP-Speicherzelle gemäß einigen Ausführungsformen zeigt;
• 3 eine beispielhafte Implementierung der ersten, in 2 gezeigten, OTP-Speicherzelle veranschaulicht.
• 4 ein Layout erster OTP-Speicherzellen gemäß einigen Ausführungsformen zeigt;
• 5 ein schematisches Diagramm der ersten, in 4 gezeigten, OTP-Speicherzellen veranschaulicht;
• 6 eine beispielhafte Implementierung einer zweiten OPT-Speicherzelle gemäß einigen Ausführungsformen zeigt;
• 7 ein schematisches Diagramm einer dritten OTP-Speicherzelle gemäß einigen Ausführungsformen veranschaulicht;
• 8 ein Layout dritter OTP-Speicherzellen gemäß einigen Ausführungsformen zeigt;
• 9 ein schematisches Diagramm der dritten, in 8 gezeigten, OTP-Speicherzellen veranschaulicht;
• 10 eine Speicheranordnung mit dritten OTP-Speicherzellen gemäß einigen Ausführungsformen zeigt; und
• 11 beispielhafte Vorspannungen für die in 10 gezeigten OTP-Speicherzellen veranschaulicht.

The disclosure can be easily understood from the following detailed description in conjunction with the accompanying drawings, wherein the same reference numerals indicate the same structural elements, and wherein:

• 1 illustrates a block diagram of a memory device in which aspects of the disclosure can be practiced in accordance with some embodiments;
• 2 FIG. 3 shows a schematic diagram of a first OTP memory cell in accordance with some embodiments; FIG.
• 3 an exemplary implementation of the first, in 2 OTP memory cell shown.
• 4th Figure 11 shows a layout of first OTP memory cells in accordance with some embodiments;
• 5 a schematic diagram of the first, in 4th OTP memory cells shown in FIG.
• 6th Figure 11 shows an example implementation of a second OPT memory cell in accordance with some embodiments;
• 7th illustrates a schematic diagram of a third OTP memory cell in accordance with some embodiments;
• 8th Figure 12 shows a layout of third OTP memory cells in accordance with some embodiments;
• 9 a schematic diagram of the third, in 8th OTP memory cells shown in FIG.
• 10 Figure 12 shows a memory array with third OTP memory cells in accordance with some embodiments; and
• 11 exemplary preloads for the in 10 illustrated OTP memory cells.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing different elements of the presented subject matter. Concrete examples of the components and arrangements are described below in order to simplify the present disclosure. These are of course only examples and are not intended to be limiting. Formation of a first element over or on a second element in the description that follows may include, for example, embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are between the first and the second member are formed so that the first and second members may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition is for the purpose of simplification and clarity and does not per se dictate a relationship between the various embodiments and / or configurations discussed.

Furthermore, spatially relative terms such as "below", "below", "lower", "above", "above", "below", "upper", "upper side", "lower side", "front", " back ”and the like may be used, for convenience of description, to describe a relationship of one element or feature to one or more other element (s) or feature (s) as illustrated in the figure (s). It is provided that the spatially relative terms include different orientations of the device in use or in operation in addition to the orientation shown in the figures. Because components in various embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only and is in no way limiting. When used in connection with layers of an integrated circuit, semiconductor device, or electronic device, the directional terminology is intended to be interpreted broadly and therefore should not be interpreted as excluding the presence of one or more interlayers or other intervening features or elements . Thus a given Layer which is described herein as being formed on, above or below another layer or arranged on, above or below another layer may be separated from the latter layer by one or more additional layers.

Embodiments described herein provide various one-time programmable (OTP) memory cells. In one embodiment, the OTP memory cell contains an additional doping region that extends under the gate of a transistor. In one embodiment, the additional doping region extends under the gate of a word line program of an antifuse transistor in the OTP memory cell. The additional doping area can minimize the diode effect, which in turn enables the memory cell current to be tightened.

In another embodiment, the OTP memory cell contains three transistors, one antifuse transistor and two selection transistors. The selection transistors can relax the voltage load on the selection transistors in the unselected OTP memory cells during programming. Additionally or alternatively, the transistors in the OTP memory cells can have shorter gate lengths due to the higher tolerance to the voltage loads. The two selection transistors can be configured as a cascaded selection transistor or as two different selection transistors.

These and other embodiments are discussed below with reference to FIG 1 until 11 discussed. However, it will be readily appreciated by those skilled in the art that the detailed description given herein with respect to these figures is for exemplary purposes only and is not to be construed as limiting.

1 FIG. 11 illustrates a block diagram of a memory device in which aspects of the disclosure can be practiced in accordance with some embodiments. In the illustrated embodiment, the storage device includes 100 Storage cells 102 arranged in rows and columns to form a memory array 104 to build. The storage device 100 can contain any suitable number of rows and columns. A memory device contains, for example, a number R of rows and a number C of columns, where R is an integer greater than or equal to or one and C is a number greater than or equal to two. As will be described in more detail later, the memory cells are 102 in one embodiment, OTP memory cells that contain an antifuse transistor and one or more selection transistors.

Each row of memory cells 102 is operational with one or more word lines (collectively word line 106 ) tied together. The word lines 106 are operative with one or more row selection circuits (collectively as a row selection circuit 108 designated) connected. The line selection circuit 108 selects a specific word line 106 based on an address signal sent from signal line 110 Will be received.

Each column of the memory cells 102 is operative with one or more bitlines (collectively bitline 112 ) tied together. The bit lines 112 are operative with one or more column selection circuits (collectively as a column selection circuit 114 designated) connected. The column selection circuit 114 selects a particular bit line 112 based on a selection signal sent by signal line 116 Will be received.

A processing device 118 is operative with the memory array 104 , the line selection circuit 108 and the column selection circuit 114 tied together. The processing device 118 is operable to perform one or more operations of the memory array 104 , the line selection circuit 108 and the column selection circuit 114 to control. Any suitable processing device can be used. Exemplary processing devices include, but are not limited to, a central processing unit, a microprocessor, an application specific integrated circuit, a graphics processing unit, a field programmable gate array, or combinations thereof.

A power supply 120 is at least with the memory array 104 and the processing device 118 operationally connected. As will be described in more detail later, the processing device 118 cause one or more bias voltages to be applied to the memory cells 102 in the memory array 104 is or will be created.

The processing device 118 and / or the power supply 120 can be in the same circuit arrangement (eg the same integrated circuit) as the memory arrangement 104 be arranged, or the processing device 118 and / or the power supply 120 can be arranged in circuitry separate from the memory device 104 and operative with the memory array 104 connected is. The storage device 100 , the processing device 118 and the power supply 120 are in an electronic device 122 contain. Exemplary electronic devices include, but are not limited to, a computing device, a television, a camera, and a portable device.

When data is in a memory cell 102 are to be written (e.g. the memory cell 102 programmed) or from a memory cell 102 will be read on signal line 110 receive an address for the memory cell. The line selection circuit 108 activates or declares the word line 106 assigned to the address. A selection signal is on the signal line 116 received and the bit line 112 associated with the selection signal is explained or activated. The data is then stored in the memory cell 102 written or read from it.

2 FIG. 3 shows a schematic diagram of a first OTP memory cell in accordance with some embodiments. The OTP memory cell 102 is with a first transistor 200 formed with a second transistor 202 is connected in series. The first transistor 200 is an antifuse transistor that is a word line program ( WLP ) Receives signal at the gate of the antifuse transistor. The second transistor 202 is a select transistor that receives a word line read (WLR) signal on the gate of the select transistor. Any suitable type of transistor can be used. In one embodiment, the first and second are transistors 200 , 202 Metal Oxide Semiconductor (MOS) transistors.

The OTP memory cell is used during programming 102 permanent oxide breakthrough as the unique programming mechanism. With conventional or known OTP memory cells, a diode effect can occur in the read current path after the breakdown. As will be described in more detail later, an additional doping area is produced in the OTP memory cell 102 an additional current path 204 , which reduces or minimizes the occurrence of the diode effect.

3 illustrates an exemplary implementation of the first, in 2 OTP memory cell shown. The WLP, WLR, and BL signal lines are included for clarity in FIG 3 left out. The first transistor 200 (e.g. the antifuse transistor) contains a gate 300 and the second transistor 202 (e.g. the selection transistor) contains a gate 302 . In one embodiment, the gates are 300 , 302 Metal gates. Along the sides of the gates 300 , 302 are dielectric sidewalls 304 positioned around the gates 300 , 302 electrically isolate. In the dielectric sidewalls 304 any suitable dielectric material can be used. The dielectric material can be, for example, an oxide, hafnium oxide or zirconium oxide.

A first gate dielectric 306 is under every gate 300 , 302 arranged, and a second gate dielectric 308 is under the first gate dielectric 306 and arranged on a substrate. The first gate dielectric 306 is for example a Hi-K dielectric (a dielectric with a high dielectric constant κ) and the second gate dielectric 308 a silicon dioxide material.

A first doping area 310 and a second doping region 312 are in the substrate 307 next to the gate 300 educated. The second doping area 312 and a third doping region 314 are in the substrate 307 next to the gate 302 arranged. The first, second and third doping regions 310 , 312 , 314 are the source and drain regions of the first and second transistors 200 , 202 . An additional fourth doping area 316 extends from the first doping region 310 and under the gate 300 of the first transistor 200 (e.g. the antifuse transistor). In some embodiments, the fourth doping region is located 316 only under part of the gate 300 . In some embodiments, the additional fourth doping region becomes 316 formed in a separate implantation process after the first, the second and the third doping region 310 , 312 , 314 were formed. The dopant or dopants in the first, second and third doping regions 310 , 312 , 314 and in the fourth doping region 316 have a first conductivity type (eg N conductivity type).

The fourth doping area 316 is used to make the additional current path 204 to form for the reading stream. The fourth doping area 316 enables the current path 204 the pn diode to avoid coming from the first doping area 310 (e.g. N conductivity type) and the second halo area 319 (e.g. P conductivity type) can result. This can increase the cell current and improve the read margin.

A first halo area 318 will be in the substrate 307 next to the second doping area 312 formed and a second halo area 319 will be in the substrate 307 next to the first doping area 310 and the additional fourth doping region 316 educated. The first and second halo areas 318 , 319 are formed with a dopant or dopants with a second conductivity type (eg P conductivity type), which is the first conductivity type of the first doping regions 310 , 312 is opposite. The first and second halo areas 318 , 319 can be the lateral diffusion of the dopant or dopants in the first and in the second doping region 310 , 312 limit each. In some embodiments, the first and second halo regions 318 , 319 formed after the gates 300 , 302 defined and before the first, the second and the third Doping area 310 , 312 , 314 were formed.

In the illustrated embodiment, the first, second, and third are doping regions 310 , 312 , 314 and the additional fourth doping region 316 formed with one or more N-type dopants and the first and second halo regions 318 , 319 are formed with one or more P-type dopants, although other embodiments are not limited to this implementation. An exemplary N-type dopant is phosphorus or arsenic and an exemplary P-type dopant is boron or gallium. The first, second and third doping regions 310 , 312 , 314 and the additional fourth doping region 316 can have a higher dopant concentration (eg N ⁺ ). Similarly, the first and second halo regions 318 , 319 in some embodiments have a higher dopant concentration (eg P ⁺ ).

4th shows a layout of first OTP memory cells in accordance with some embodiments. 5 FIG. 11 illustrates a schematic diagram of the first, in FIG 4th OTP memory cells shown. FIG. is used in conjunction with the 5 described. The layout 400 represents four OTP memory cells 102a , 102b , 102c , 102d . The first OTP memory cell 102a contains the first transistor 200a ( 5 ), the one with the second transistor 202a is connected in series ( 5 ). As described above, the first is transistor 200a in one embodiment, an antifuse transistor and the second transistor 202a is a selection transistor. The gate of the first transistor 200a receives a word line program 0 ( WLP0 ) Signal and the gate of the second transistor 202a receives a wordline read 0 (WLR0) signal.

The second OTP memory cell 102b contains the first transistor 200b ( 5 ) and the second transistor 202b ( 5 ) connected in series. The gate of the first transistor 200b receives a wordline read 1 ( WLR1 ) Signal and the gate of the second transistor 202b receives a word line program 1 ( WLP1 ) Signal. The second OTP memory cell 102b is with the first OTP memory cell 102a connected in series ( 5 ).

The third OTP memory cell 102c contains the first transistor 200c ( 5 ) and the second transistor 202c ( 5 ) connected in series. The gate of the first transistor 200C receives a word line program- 2 ( WLP2 ) Signal and the gate of the second transistor 202c receives a word line read 2 ( WLR2 ) Signal.

The fourth OTP memory cell 102d contains the first transistor 200d ( 5 ) and the second transistor 202d ( 5 ) connected in series. The gate of the first transistor 200d receives a word line read 3 ( WLR3 ) Signal and the gate of the second transistor 202d receives a word line program- 3 ( WLP3 ) Signal. The fourth OTP memory cell 102d is with the third OTP memory cell 102c connected in series ( 5 ).

One bit line 112 ( 5 ) extends along the first, second and third doping regions (eg the source / drain regions 310 , 312 , 314 in 3 ) of the first and the second transistor 200a , 202a , 200b , 202b , 200c , 202c , 200d , 202d and is connected to it. A dummy area 402 is between the second OTP memory cell 102b and the third OTP memory cell 102c educated. A dummy area 402 is also next to the first OTP memory cell 102a and next to the fourth OTP memory cell 102d educated. The dummy areas 402 contain polysilicon spacers that cover the floating areas 500 ( 5 ) that form with a source / drain region (e.g. the first doping region 310 in 3 ) of the first memory cell 102a and with a source / drain region (e.g. the first doping region 310 in 3 ) of the fourth OTP memory cell 102d are connected. The dashed line 404 defines a one-bit OTP memory cell (e.g. OTP memory cell 102b) .

The additional four doping areas 316a , 316b , 316c are formed under part of the gates that receive the word line program signals ( WLP0 , WLP1 , WLP2 , WLP3 ) receive and overlap or extend to a source / drain region (eg first doping region 310 in 3 ) of every first transistor 200a , 200b , 200c , 200d . We above in connection with 3 described, the additional fourth doping region extends 316 on or overlaps the first doping region 310 (the source / drain area of the first transistor 200 ). The second doping area 316a creates the additional current path 502 for the read current (in 5 shown). The second doping area 316b generates the additional current paths 504 , 506 . The second doping area 316c creates the additional current path 508 . When reading an OTP memory cell 102a , 102b , 102c , 102d can be an additional current path 502 , 504 , 506 , 508 reduce or minimize the occurrence of the diode effect for the read current.

6th FIG. 11 shows an exemplary implementation of a second OTP memory cell in accordance with some embodiments. The OTP memory cell 102 is the in 3 shown memory cell 102 similar, but with the addition of the additional conductive element 600 and the first and second contacts 602 , 604 between the conductive element 600 and the first and second doping regions, respectively 310 , 312 of the first transistor 200 (e.g. the source and drain areas of the first transistor 200 ).

The first contact 602 , through the via 603 , is used to add the Current path 204 to activate by the additional fourth doping area 316 was generated. The additional current path 204 is activated when an initial bias is applied to the first contact 602 is created. The second contact 604 , through the via 605 , is used to create a second rung 606 in the first transistor 200 activate when the first bias on the second contact 604 is created. A breakthrough to the top end 608 of the second doping region 312 forms a low-resistance connection between the gate of the first transistor 200 and the second doping region 312 . The low-resistance connection creates the second current path 606 (e.g. a high current antifuse element).

In one embodiment, there is only the first contact 602 contained in each OTP memory cell and is used to activate the additional current path 204 used. In another embodiment, both are the first contact 602 as well as the second contact 604 contained in each memory cell and are used to activate the additional current path 204 and the second current path 604 used. In other embodiments only the second contact is 604 contained in each OTP memory cell and is used to activate the second current path 604 used.

The second rung 606 is on the side of the first transistor 200 that the second contact 604 assigned. In the illustrated embodiment, the additional current path is located 204 due to the additional fourth doping region 316 is generated on the left side of the first transistor 200 and the second rung 606 is on the right side of the first transistor 200 . This is the current path for the first transistor 200 doubled (right and left sides). In addition, the cell current can be based on the additional fourth doping region 316 which in turn increases the read margin for the OTP memory cell 102 improved.

In some embodiments, the selection transistors (eg 202) may be in the unselected OTP memory cells 102 Experienced voltage stress when the biases on the gates (e.g. 300, 302 in 3 ) and / or the bit lines 112 be applied when a memory cell 102 programmed (e.g. written). The inclusion of a third transistor in the OTP memory cells 102 can relax the tension. 7th FIG. 11 illustrates a schematic diagram of a first OTP memory cell in accordance with some embodiments. The OTP memory cell 102 contains the first transistor 200 , the second transistor 202 and a third transistor 700 . In the illustrated embodiment, the second transistor 202 and the third transistor 700 with the word line read (WLR) signal line 702 connected in parallel (with the gates of the second and third transistor 202 , 700 tied together). The second and the third transistor 202 , 700 essentially form a cascaded transistor 706 . In one embodiment, the cascaded transistor is 706 a cascaded selection transistor and the first transistor 200 is an antifuse transistor. The cascaded transistor 706 is with the first transistor 200 connected in series. In other embodiments, the signal lines are connected to the gates of the second transistor 202 and the third transistor 700 are connected, different signal lines (e.g. not connected to each other).

The cascaded transistor 706 can relax the tension, which in turn reduces the effects of tension. The voltage drop in a single second transistor 202 (eg a selection transistor) can be five volts, for example. With a cascaded transistor 706 can be the voltage drop in the second transistor 202 in the cascaded transistor 706 2.5 volts and the voltage drop in the third transistor 700 in the cascaded transistor 706 can be 2.5 volts.

8th shows a layout of third OTP memory cells according to some embodiments. 9 FIG. 11 illustrates a schematic diagram of the third, in FIG 8th described, OTP memory cells. 8th will be used in conjunction with 9 described. The layout 800 represents four OTP memory cells 102a , 102b , 102c , 102d . The first OTP memory cell 102a contains the first transistor 200a , the one with the cascaded transistor 706a is connected in series. As described above, in one embodiment, the first transistor is an antifuse transistor and the cascaded transistor is a cascaded select transistor. The gate of the first transistor 200a receives a word line program 0 ( WLP0 ) Signal and the gate of the cascaded transistor 706a receives a wordline read 0 (WLR0) signal.

The second OTP memory cell 102b contains the first transistor 200b and the cascaded transistor 706b connected in series. The gate of the first transistor 200b receives a word line program 1 ( WLP1 ) Signal and the gate of the cascaded transistor 706b receives a wordline read 1 ( WLR1 ) Signal. The second OTP memory cell 102b is with the first OTP memory cell 102a connected in series.

The third OTP memory cell 102c contains the first transistor 200c and the cascaded transistor 706c connected in series. The gate of the first transistor 200c receives a word line program- 2 ( WLP2 ) Signal and the gate of the cascaded transistor 706c receives a word line read 2 ( WLR2 ) Signal.

The fourth OTP memory cell 102d contains the first transistor 200d and the cascaded transistor 706d connected in series. The gate of the first transistor 200d receives a word line program- 3 ( WLP3 ) Signal and the gate of the cascaded transistor 706d receives a word line read 3 ( WLR3 ) Signal. The fourth OTP memory cell 102d is with the third OTP memory cell 102c connected in series.

One bit line 112 extends along the source / drain regions of the first and second transistors 200a , 202a , 200b , 202b , 200c , 202c , 200d , 202d and is related to it, as in 9 shown. A dummy area 402 is between the second OTP memory cell 102b and the third OTP memory cell 102c educated. A dummy area 402 is also next to the first OTP memory cell 102a and next to the fourth OTP memory cell 102d educated. As described above, the dummy areas form 402 the floating areas 500 associated with the source / drain regions (e.g. first doping region 310 in 3 ) of the first and fourth OTP memory cells 102a , 102d (please refer 9 ) are connected. The dashed line 802 defines a one-bit OTP memory cell (e.g. OTP memory cell 102b) .

10 shows a memory arrangement with third OTP memory cells in accordance with some embodiments. Even though 10 9 shows nine OTP memory cells, other embodiments may include any number of OTP memory cells in a memory array. In addition, the biases BL1 , BL2 , BL3 , WLP , WLR1 and WLR2 for the bit lines 1006a , 1006b , 1006c and the word lines 1008a , 1010a , 1012a , 1008b , 1010b , 1012b , 1008c , 1010c , 1012c shown. Any suitable bias voltages can be used and 11 Figure 3 illustrates exemplary bias voltages for the OTP memory cells. In general, the bias voltages are determined based on power domains assigned to the OTP memory cells. Examples of power domains include, but are not limited to, a programming voltage, an intermediate voltage, a nominal voltage, and a ground voltage. The programming voltage is used to program an OTP memory cell and is applied to the WLP signal line. Non-limiting examples of the various voltages include, but are not limited to, a programming voltage in the range of two to six volts and an intermediate voltage that is between a nominal voltage and the programming voltage. The nominal voltage is typically a normal or standard voltage for a transistor and is determined by the process technology; an example of a nominal voltage is 0.75 volts. The ground voltage is similar to VSS, and in some embodiments the ground voltage is plus or minus several hundred millivolts for controlling leakage or voltage stresses.

In some situations, a higher programming voltage can be used to reduce the time spent programming the OTP memory cells. However, too high a voltage can lead to some undesirable side effects, such as transistor stress for the selected OTP memory cell (e.g. OTP memory cell 1002 ) and the half-selected OTP memory cells (e.g. OTP memory cells 1004 ), high performance, and greater difficulty in designing the memory array circuits (e.g., voltage generator, BL-MUX circuits, etc.). To reduce the voltage stress, the intermediate voltage is applied to the signal line during programming WLR1 created. The intermediate voltage reduces the voltage stress on the selection transistor (s) (for example the second transistor) 202 and the third transistor 700 ) for the selected OTP memory cell (e.g. OTP memory cell 1002 ) and for the half-selected OTP memory cells (e.g. OTP memory cells 1004 ).

In 10 are the WLR signal lines for the second transistor (e.g. second transistor 202 ) and the third transistor (e.g. third transistor 700 ) separate signal lines (not connected to each other). The transistors in each OTP memory cell are connected in series (for example the antifuse transistor and the first and second selection transistors).

The storage arrangement 1000 contains a selected OTP memory cell 1002 . The remaining OTP memory cells are not selected. The selected OTP memory cell 1002 is achieved by applying a programming voltage to the word line program ( WLP ) Signal line 1008a connected to the first transistor (e.g. antifuse transistor), an intermediate voltage to the WLR1 signal line 1010a, which is connected to the second transistor (e.g. first selection transistor), and a nominal voltage to the WLR2 signal line 1012a, which is connected to the third transistor (e.g. second selection transistor) is connected, selected. A ground voltage is applied to the BL2 signal line 1006b created with the selected OTP memory cell 1002 connected is. In one non-limiting example, the programming voltage is 5 volts, the intermediate voltage is 1.2 volts, the nominal voltage is 0.75 volts, and the ground voltage is 0 volts. In this example, the second and third biases create an increased WLR.

In the case of the unselected OTP memory cells, the ground voltage is applied to the WLP signal lines 1008b , 1008c connected to the first transistor, the WLR1 signal line 1010b , 1010c connected to the second transistor and the WLR2 signal line 1012b , 1012c of the third transistor. The nominal voltage is also applied to the BL1 and BL3 Signal lines 1006a , 1006c created.

11 illustrates exemplary preloads for the in 10 OTP memory cells shown. Some of the exemplary bias voltages may reduce the voltage stress on the transistors in the circled areas 1004 , 1005 relax. Five different bias voltages are shown for a programming process. The five exemplary biases have different properties of the biases.

The first (1) biases 1100 for the selected and unselected OTP memory cells are those related to 10 programming, intermediate, nominal and ground voltages. The second (2) biases 1102 apply a negative bias voltage of -0.5 volts to the BL2 Signal line 1006b with the selected OTP memory cell 1002 connected, apply a programming voltage (e.g. 5 volts) to the WLP signal line 1008a with the selected OTP memory cell 1002 connected, and apply an intermediate voltage (e.g. 1.2 volts) to the WLR1 and WLR2 Signal lines 1010a , 1012a with the selected OTP memory cell 1002 connected is. The negative bias on the BL2 signal line 1006b receives a sufficient programming bias for the selected OTP memory cell 1002 . A ground voltage (eg 0 volts) is applied to the WLP signal line for the memory cells that are not selected 1008b , the WLP signal line 1008c , the WLR1 signal lines 1010b , 1012b and the WLR2 signal lines 1010c , 1012c created. A nominal voltage (e.g. 0.75 volts) is applied to the BL1 and BL3 Signal lines 1006a , 1006c created.

The third (3) biases 1104 apply a programming voltage (e.g. 5 volts) to the WLP signal line 1008a with the selected OTP memory cell 1002 is connected, an intermediate voltage (e.g. 1.2 volts) to the WLR1 Signal line 1010a associated with the second transistor in the selected OTP memory cell 1002 and an increased WLR nominal voltage (e.g. 0.75 volts) to the WLR2 signal line 1012a, which is connected to the third transistor in the selected OTP memory cell 1002 connected is. A ground voltage (e.g. 0 volts) is applied to the BL2 signal line 1006b created with the selected OTP memory cell 1002 connected is. The increased WLR nominal voltage relaxes the voltage stress on the transistors in the unselected OTP memory cells. A ground voltage (eg 0 volts) is applied to the WLP signal line for the memory cells that are not selected 1008b , the WLP signal line 1008c , the WLR1 signal lines 1010b , 1012b and the WLR2 signal lines 1010c , 1012c created. A nominal voltage (e.g. 0.75 volts) is applied to the BL1 and BL3 Signal lines 1006a , 1006c created.

The fourth (4) biases 1106 apply a higher blocking voltage (eg an intermediate voltage (1.2 volts)) to the BL1 and BL3 signal lines 1006a, 1006c and a higher blocking voltage (eg a nominal voltage (0.75 volts)) to the WLR2 signal lines 1012b , 1012c connected to the third transistors of the unselected OTP memory cells. A ground voltage (e.g. 0 volts) is applied to the WLP signal lines 1008b , 1008c and to the WLR1 signal lines 1010b , 1010c of the unselected OTP memory cells. A programming voltage (eg 5 volts) is applied to the WLP signal line for the selected OTP memory cell 1008a connected to the first transistor, an intermediate voltage (e.g. 1.2 volts) is applied to the WLR1 signal line 1010a, which is connected to the second transistor, a nominal voltage (e.g. 0.75 volts) is applied to the WLR2- Signal line 1012a connected to the third transistor is applied, and a ground voltage (e.g., 0 volts) is applied to the BL2 signal line 1006b created with the selected OTP memory cell 1002 connected is.

The fifth (5) biases 1108 combine the second and third biases 1102 , 1104 . A negative bias is applied to the BL2 signal line 1006b created with the selected OTP memory cell 1002 and the increased nominal WLR voltage (e.g. 0.75 volts) is applied to the WLR2 signal line 1012a, which is connected to the third transistor in the selected OTP memory cell 1002 connected is.

In 11 are exemplary biases for a read operation 1110 shown. An intermediate voltage (e.g. 1.4 volts) is applied to the WLP signal line 1008a of the selected OTP memory cell 1002 and a nominal voltage (e.g. 0.75 volts) is applied to the WLR1 and WLR2 signal lines 1010a, 1012a associated with the selected OTP memory cell 1002 connected. A ground voltage (e.g. 0 volts) is applied to the BL2 signal line 1006b created with the selected OTP memory cell 1002 connected is. A ground voltage (eg 0 volts) is applied to the WLP signal line for the memory cells that are not selected 1008b , the WLP signal line 1008c , the WLR1 signal lines 1010b , 1012b and the WLR2 signal lines 1010c , 1012c and a nominal voltage (eg, 0.75 volts) is applied to the BL1 and BL3 signal lines 1006a, 1006c.

An overview of the features of several embodiments has been given above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to accomplish the same purpose and / or achieve the same advantages as the embodiments presented herein. It should also be recognized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and changes can be made therein without departing from the spirit and scope of the present disclosure.

In one aspect, a one-time programmable (OTP) memory cell includes an antifuse transistor connected in series with a select transistor. The antifuse transistor contains a first gate, a first doping region which forms a first source / drain region, and a second doping region which forms a second source / drain region. The selection transistor includes a second gate, the second doping region, which forms a third source / drain region, and a third doping region, which forms a fourth source / drain region. An additional fourth doping region is connected to the first doping region and extends partially under the first gate of the antifuse transistor. The additional fourth doping region forms an additional current path for a read current.

In another aspect, an OTP memory cell includes an antifuse transistor, a first selection transistor operatively connected to the antifuse transistor, and a second selection transistor operatively connected to the first selection transistor. A first word line read signal line is connected to a first gate of the first selection transistor. A second word line read signal is connected to a second gate of the second selection transistor and the first word line read signal line in such a way that the first and the second selection transistor form a cascaded selection transistor.

In yet another aspect, an electronic device includes a memory array and a processing device operatively connected to the memory array. The memory arrangement contains a one-time programmable (OTP) memory cell which contains an antifuse transistor which is connected in series with a selection transistor. The antifuse transistor contains a first gate, a first doping region which forms a first source / drain region, and a second doping region which forms a second source / drain region. The selection transistor includes a second gate, the second doping region, which forms a third source / drain region, and a third doping region, which forms a fourth source / drain region. An additional fourth doping region is connected to the first doping region and extends partially under the first gate of the antifuse transistor. A first contact is connected to the first doping region. A second contact is connected to the second doping region. The processing device is operable to cause a bias voltage to be applied to the first contact to activate an additional current path created by the additional fourth doping region for a read current and to the second contact to activate a second current path for the Activate read current.

The description and illustration of one or more aspects provided in this application are not intended to limit or limit the scope of the disclosure as claimed in any way. The aspects, examples, and details provided in this application are believed sufficient to impart ownership and enable others to make and make optimal use of the claimed disclosure. The claimed disclosure is not to be construed as limited to any aspect, example, or detail provided in the application. Regardless of whether shown and described in combination or separately, it is intended that the various features (both structural and methodological) be selectively included or omitted in order to create an embodiment having a particular set of features. Having described and illustrated the present application, those skilled in the art can envision variations, modifications, and alternative aspects that come within the spirit of the broader aspects of the general inventive concept embodied in this application and that do not depart from the broader scope of the disclosure as claimed.

Claims (20)

A one-time programmable (OTP) memory cell comprising: an antifuse transistor having a first gate, a first doping region forming a first source / drain region, and a second doping region forming a second source / drain region, includes; a selection transistor connected in series with the antifuse transistor, the selection transistor having a second gate, the second doping region, which forms a third source / drain region, and a third doping region, which is a fourth source / drain region forms, includes; and an additional fourth doping region that is connected to the first doping region and extends partially under the first gate of the antifuse transistor, wherein the additional fourth doping region creates an additional current path for a read current. OTP memory cell after Claim 1 , further comprising: a first contact with the first doping region; and a second contact with the second doping region; and a conductive element connecting the first and second contacts. OTP memory cell after Claim 2 wherein the additional current path is activated with a first bias applied to the first contact and a second current path activated when the bias is applied to the second contact. OTP memory cell according to one of the preceding claims, further comprising a halo region arranged between the first and the second doping region and next to the first doping region and the additional fourth doping region. OTP memory cell according to one of the preceding claims, further comprising a halo region between the second and the third doping region and next to the second doping region. OTP memory cell according to one of the preceding claims, wherein the first doping region, the second doping region, the third doping region and the additional fourth doping region are formed with a dopant or dopants of a first conductive type. OTP memory cell according to one of the preceding claims, wherein the OTP memory cell is contained in a plurality of OTP memory cells in a memory arrangement. One time programmable (OTP) memory cell comprising: an antifuse transistor; a first selection transistor operatively connected to the antifuse transistor; and a second selection transistor operatively connected to the first selection transistor, wherein: a first word line read signal line is connected to a first gate of the first selection transistor; and a second word line read signal is connected to a second gate of the second selection transistor and the first word line read signal line in such a way that the first and the second selection transistor form a cascaded selection transistor. OTP memory cell after Claim 8 , wherein the cascaded selection transistor is connected in series with the antifuse transistor. OTP memory cell after Claim 8 or 9 , wherein a drain / source region of the antifuse transistor is connected to a floating region. OTP memory cell according to one of the Claims 8 until 10 , further comprising a bit line connected to the antifuse transistor, the first selection transistor and the second selection transistor, wherein a negative bias voltage is applied to the bit line during a programming operation. OTP memory cell according to one of the Claims 8 until 11 wherein a first bias voltage is applied to a first word line read signal line connected to a first gate of the first selection transistor and a different second bias voltage is applied to a second word line read signal line connected to a second gate of the second selection transistor. An electronic device comprising: a processing device; a memory array operatively connected to the processing device, the memory array comprising: a one-time programmable (OTP) memory cell comprising: an antifuse transistor forming a first gate, a first dopant region forming a first source / drain region , and a second doping region forming a second source / drain region; a selection transistor connected in series with the antifuse transistor, the selection transistor having a second gate, the second doping region, which forms a third source / drain region, and a third doping region, which is a fourth source / drain region forms, includes; an additional fourth doping region connected to the first doping region and extending partially below the first gate of the antifuse transistor; a first contact connected to the first doping region; and a second contact connected to the second doping region, wherein the processing device is operable to cause that a bias is applied to the first contact to activate an additional current path generated by the additional fourth doping region for a read current, and to the second contact to activate a second current path for the read current. Electronic device according to Claim 13 wherein the OTP memory cell further comprises a conductive element connected to the first and second contacts. Electronic device according to Claim 13 or 14th wherein the OTP memory cell further comprises a conductive element connected to the first contact or the second contact. Electronic device according to one of the Claims 13 until 15th wherein the OTP memory cell further comprises a halo region which is formed between the first and the second doping region and next to the first doping region and the additional fourth doping region. Electronic device according to one of the Claims 13 until 16 wherein the OTP memory cell further comprises a halo region which is formed between the second doping region and the third doping region and next to the second doping region. Electronic device according to one of the Claims 13 until 17th wherein the first doping region, the second doping region, the third doping region and the additional fourth doping region are formed with a dopant or dopants with a first conductive type. Electronic device according to one of the Claims 13 until 18th , wherein a drain / source region of the antifuse transistor is connected to a floating region. Electronic device according to one of the Claims 18 until 19th , further comprising: a row select circuit operatively connected to one or more word lines in the memory array; and a column selection circuit operatively connected to one or more bit lines in the memory array.

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