DE102011055018A1 - Semiconductor package for use in e.g. electronic system, has upper semiconductor device comprising conductive bumps that connect pads on upper surface of interposer to corresponding terminal on lower surface of device - Google Patents

Abstract

The package (1) has an interposer (120) formed from a semiconductor material or a glass material and comprising pads (124) formed on its upper surface. A lower semiconductor chip (130) is attached at the interposer. An upper semiconductor device (200) has a lower surface on which terminals (270, 280) are formed. The device has conductive bumps with lower and upper sections arranged on the upper surface of the interposer and extending to the lower surface of the device. The bumps connect one of the pads to the corresponding terminal on the lower surface of the device. An independent claim is also included for a method for producing a semiconductor package.

Description

CROSS-REFERENCE TO A RELATED PATENT APPLICATION

This application claims under 35 USC § 119 the benefits of Korean Patent Application No. 10-2011-014145 filed on Feb. 17, 2011 with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The disclosure relates to semiconductor packages, and more particularly to a semiconductor package having an interposer with a through-substrate via (TSV), and a method of manufacturing the semiconductor package.

With the development of the electronics industry, lightweight, small, fast and high-performance electronic products can be provided at a low price. According to recent trends in the electronics industry, semiconductor devices in which a plurality of semiconductor chips or semiconductor packages are implemented in a single package attract much attention. Various researches and miniaturization and high integration of such semiconductor devices have been operated.

SHORT VERSION

A semiconductor package is disclosed herein comprising:
A lower semiconductor package having a lower base substrate; an interposer placed on the lower base substrate and having substrate through vias (TSVs); and a lower semiconductor chip mounted on the interposer and electrically connected to the interposer; an upper semiconductor package placed on the lower semiconductor package and having an upper semiconductor chip; and package interconnect components placed on the interposer and electrically connecting the top semiconductor package to the interposer.

A method for manufacturing a semiconductor package is also disclosed, the method comprising: providing an interposer having substrate via (TSVs); Attaching first package connection components to the interposer; Attaching a lower semiconductor chip to the interposer substrate; Forming a lower potting member that seals the lower semiconductor chip; Removing the lower Vergussbauteils, which is placed on the lower semiconductor chip. The method may further include attaching an auxiliary substrate on the lower semiconductor chip; exposing the TSVs by removing a lower portion of the interposer substrate; having a removal of the auxiliary substrate. The method may further include forming a plurality of interposers to which a plurality of the lower semiconductor chips are electrically connected by dicing the interposer wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

1 FIG. 4 is a plan view of an interposer wafer according to some embodiments; FIG.

2 a cross-sectional view of the interposer wafer of 1 taken along a line II-II of 1 is;

3 an enlarged cross-sectional view of a portion III of the interposer wafer, which in 2 is illustrated is;

4 an enlarged cross-sectional view of a portion III of the interposer wafer, which in 2 is illustrated, according to another embodiment;

The 5 and 6 Top views of a case in which semiconductor chips on the interposer wafer, which in 1 is illustrated attached;

7 FIG. 3 is a cross-sectional view of a semiconductor package according to some embodiments; FIG.

8th is a conceptual view showing an electrical connection of the semiconductor package of 7 illustrated;

The 9 to 22 Cross-sectional views illustrating a method of forming the semiconductor package of 7 according to some embodiments;

The 23 to 28 are enlarged views illustrating cases in which a lower Vergussbauteil which in the semiconductor package of 7 included, varies;

29 FIG. 3 is a cross-sectional view of a semiconductor package according to some embodiments; FIG.

30 FIG. 3 is a cross-sectional view of a semiconductor package according to some embodiments; FIG.

The 31 to 33 Cross-sectional views illustrating a method of forming the semiconductor package of 30 according to some embodiments;

34 FIG. 3 is a cross-sectional view of a semiconductor package according to some embodiments; FIG.

The 35 and 36 Are cross-sectional views of semiconductor packages according to some embodiments;

37 FIG. 3 is a cross-sectional view of a semiconductor package according to some embodiments; FIG.

The 38 to 42 Are cross-sectional views of semiconductor packages according to some embodiments;

The 43 to 46 Cross-sectional views illustrating a method of forming a semiconductor package according to some embodiments;

The 47 to 53 Cross-sectional views illustrating a method of forming a semiconductor package according to some embodiments;

54 to 57 Are cross-sectional views of semiconductor packages according to some embodiments;

The 58 to 62 Cross-sectional views illustrating a method of forming semiconductor packages according to some embodiments;

63 Fig. 10 is a block diagram of a memory card according to an embodiment;

64 Fig. 10 is a schematic block diagram of a system according to an embodiment; and

65 a perspective view of an electronic device with semiconductor devices, which are manufactured according to embodiments, is.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments will now be fully described with reference to the accompanying drawings.

However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments discussed herein. Rather, these embodiments are provided so that this disclosure will be thorough and thorough. In the drawings, the thicknesses or sizes of layers may be exaggerated for clarity and convenience of explanation.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" to another element, it will directly abut or may be directly extending to the other element, or intervening elements may be present. In contrast, when an element is referred to as "directly on" or "directly extending to" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Like reference numerals refer to like elements throughout the description. As used herein, the wording "and / or" includes any and all combinations of one or more of the associated listed items.

It will be understood that although the wording first, second, third, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, or regions Layers and / or sections should not be limited by these words. These words are only used to distinguish one element, one component, one region, one layer, and / or section from another (another) element, component, region, layer, and / or section. For example, a first (first / first) element, component, area, layer and / or section could be used as a second (second / second) element, constituent, region, layer and / or section, without departing from the teachings of the present inventive concept.

Spatially relative terms, such as "over," "upper," "lower," and the like, may be used herein to describe the relationship of one element or feature to another element (s) or feature (s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "under" may include both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

The terminology or terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. As used herein, the singular forms "one, one, one," and "the, the, the" are intended to include plural forms as well, unless the context clearly indicates otherwise. It will further be understood that the words "having" and / or "having" when used in this specification, the presence of specified features, numbers, steps, operations, elements and / or components and / or or groups thereof, but does not preclude the presence or addition of one or more features, numbers, steps, operations, elements, components, and / or groups thereof.

Changes in the forms of the illustrations may result, for example, from manufacturing techniques and / or acceptable tolerances. Accordingly, unless expressly claimed, the invention should not be construed as limited to the particular shapes of areas illustrated herein, but may include variations in shapes, for example, resulting from manufacture. For example, a rim or corner area, illustrated as having sharp edges, may have rounded or curved features. Similarly, elements that are illustrated as circular or spherical may be oval in shape or may have certain straight or flattened portions. As another example, the wording "same / same / same" as used herein, when referring to shapes, sizes, quantities, or other units of measurement, does not necessarily mean the same / same / same, but is intended to include nearly identical measures within acceptable variations that may occur, for example, due to manufacturing operations.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms such as these defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant area and they will not be in an idealized or unless otherwise expressly defined herein.

1 is a plan view of an interposer wafer 10 according to some embodiments. 2 is a cross-sectional view of the interposer wafer 10 taken along a line II-II of 1 ,

Referring to the 1 and 2 can the interposer wafer 10 have a wafer accessible to standard semiconductor manufacturing operations. For example, the wafer interposer 10 a 200 mm (8 inch), 300 mm (12 inch) or 450 mm (18 inch) wafer. The wafer interposer 10 may be formed of a semiconductor such as silicon (which may be crystalline silicon), glass or other such substrate (eg, silicon on insulator which may be amorphous, polycrystalline or crystalline silicon formed on glass). Alternatively or additionally, the wafer interposer 10 be formed of a rigid material having a modulus of elasticity (Young's modulus) of 100 GPa or more. The interposer 10 may have a smooth or flat and / or flat surface. As one example, the root mean square surface roughness of the surface may be 1.5 nm or less. The interposer wafer 10 can be a plurality of interposer elements 20 which, when coming from the interposer 10 separated by subsequent processing, individual interposer chips 20 build up or can constitute.

The majority of interposer elements 20 can be by scribing lines or scribed lines 12 separated and defined or limited. Alternatively, the interposer elements / chips 20 may be replaced by semiconductor integrated circuit dies (for example, still combined on a wafer) or semiconductor integrated circuit chips (eg, integrated switching dies that are separate from the wafer).

The interposer wafer 10 can be a lower section 30 , an upper section 40 , which is on the lower section 30 is placed, and a wiring section 50 , which is on the upper section 40 is placed. The upper section 40 can vias 42 which are in the upper section 40 buried or buried. The vias or vias 42 can not get into the lower section 30 extend. The lower section 30 may during an operation of manufacturing a semiconductor package 1 like the one with reference to 7 is described, for example, be removed during a thinning or thinning process. With the removal of the lower section 30 will be the vias 42 through the upper section 40 extend and substrate vias (TSVs) 42 the interposer 10 constitute. The substrate vias 42 may be silicon vias if the interposer base section 32 is formed of silicon.

The thickness of the combination of the upper section 40 and the lower section 30 , can for the interposer 10 and / or interposer chips 20 be sufficient to serve as a carrier substrate.

The lower section 30 and the top section 40 can have a base section 32 which acts as a substrate for the interposer 10 can serve. The base section 32 may be formed of a wafer formed of a semiconductor material or an insulating material, for example, silicon, germanium, silicon germanium, gallium arsenide (GaAs), glass, ceramics, silicon on insulator, or the like. The base section 32 can be an undoped material.

The wiring section 50 can be an insulating layer 52 and wiring pattern 54 which is inside the insulating layer 52 are placed. The wiring pattern 54 can be electrically connected to the vias 42 be connected. The insulating layer 52 may comprise oxide, nitride, or oxynitride, for example, silicon oxide, silicon nitride or silicon oxynitride. The wiring pattern 54 may comprise a metal, they may comprise at least one material which is used to the vias 42 , as described above, or they may be the same material as the TSVs 42 exhibit. The wiring pattern 54 can be rewiring patterns. In some embodiments, some or all of the vias 42 be formed around the wiring section 50 to penetrate. The vias 42 can from the top surface of the interposer 10 be exposed.

3 FIG. 12 is an enlarged cross-sectional view of a region III of the interposer wafer. FIG 10 which is in 2 is illustrated, according to one embodiment. 4 FIG. 12 is an enlarged cross-sectional view of a region III of the interposer wafer. FIG 10 which is in 2 is shown, according to another embodiment.

Referring to 3 can the upper section 40 of the interposer wafer 10 upper pads 58 and the vias 42 exhibit. The wiring section 50 of the interposer wafer 10 can the wiring pattern 54 and wiring pattern pads 56 exhibit. The upper pads 58 can electrically and / or physically with the vias 42 be connected. The wiring pattern pads 56 can also be electrically and / or physically with a semiconductor chip 130 (please refer 7 ), which on the interposer wafer 10 attached, be connected. The wiring pattern 54 can electrically change the wiring pattern pads 56 with the upper pads 58 Connect or electrically connect the wiring pattern pads 56 with the vias 42 connect. The wiring pattern pads 56 may be more dense than the upper pads 58 or the vias 42 , For example, a distance d1 between the wiring pattern pads 56 less than a distance d2 between the upper pads 58 and may be less than a distance d3 between the vias 42 , In this case, the wiring patterns 54 serve as a rewiring pattern.

At least some of the wiring pattern pads 56 can have smaller sizes than the upper pads 58 , The wiring pattern pads 56 and the upper pads 58 may include a conductive material or may include a material that is used to form the wiring patterns 54 For example, the same material as that of the wiring patterns 54 ,

Each of the vias 42 may have a structure in which an insulating layer 43 , a seed layer 44 and a conductive layer 45 are formed sequentially or sequentially. The insulating layer 43 can the conductive layer 45 from the base section 32 electrically isolate. The insulating layer 43 may comprise oxide, nitride or oxynitride, for example silicon oxide, silicon nitride or silicon oxynitride. The conductive layer 45 can comprise a conductive material, for example a metal. The germ layer 44 and / or the conductive layer 45 For example, they may have at least one selected from the group consisting of aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium (In ), Manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), renium (Re), lutetium (Ru), tantalum (Ta ), Tellurium (Te), titanium (Ti), tungsten (W), zinc (Zn) and zircon (Zr). The insulating layer 43 , the germ layer 44 and the conductive layer 45 which each via 42 By chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), High Density Plasma CVD (HDP-CVD), sputtering, organometallic vapor deposition, and so on Vapor deposition (Metal Organic CVD = MOCVD) or Atomic Layer Deposition (ALD).

Referring to 4 can the upper section 40 of the interposer wafer 10 the vias 42 and may or may the upper pads 58 do not have. In this case, the wiring patterns 54 , which in the wiring section 50 of the interposer wafer 10 are physically included with the vias 42 be connected and therefore be electrically connected to it. Although the area of the upper section of each feedthrough 42 is the same as that of the lower portion of each wiring pattern 54 covering the upper portion of each via 42 in the 3 and 4 contacted, the invention is not limited thereto. For example, the area of the upper portion may be any via 42 be less than or greater than that of the lower portion of each wiring pattern 54 covering the upper portion of each via 42 contacted.

The 5 and 6 FIG. 10 are plan views illustrating the cases in which semiconductor chips on and on the interposer wafer 10 are attached.

Referring to 5 is a single semiconductor chip 60 on each of the interposer elements 20 of the interposer wafer 10 appropriate. As in the enlarged section of the 5 is a plurality of package connection components 70 on or on the interposer wafer 10 appropriate. The package connector components may include bumps, pads, etc., and may have the various configurations as further described herein. Each package connection component 70 For example, an electrical connection may be made to a corresponding TSV (or via, which is later formed in a TSV) in the interposer wafer 10 have formed. Each of these electrical connections can be via the wiring pattern 50 of the interposer wafer 10 be formed or become.

Referring to 6 are several discrete devices, here semiconductor chips 60a . 60b and 60c on or on each of the interposer elements 20 of the interposer wafer 10 appropriate. As in the enlarged section of the 6 are shown are a plurality of package connection components 70 on or on the interposer wafer 10 appropriate. The package connector components may include bumps, pads, etc., and may have the various configurations as further described herein. Each package connection component 70 For example, an electrical connection may be made to a corresponding TSV (or via which is to be formed later in a TSV) in the interposer wafer 10 is formed. Each of these electrical connections can be via the wiring pattern 50 of the interposer wafer 10 be formed or be.

In an example, the semiconductor chips 60 . 60a . 60b and 60c Be logic semiconductor chips or memory semiconductor chips. The logic semiconductor chips may be microprocessors, for example central processing units (CPUs), controllers, application specific integrated circuits (ASICs) or the like. The memory semiconductor chips may be volatile memories such as DRAMs (Dynamic Random Access Memories) and / or SRAMs (Tripod Random Access Memories) and / or nonvolatile memories such as flash memory. For example, the semiconductor chips 60a . 60b and 60c a combination of at least one logic semiconductor chip and at least one DRAM chip.

7 is a cross-sectional view of a semiconductor package 1 according to some embodiments.

Referring to 7 can the semiconductor package 1 a lower semiconductor package 100 , an upper semiconductor package 200 and package connector components 260 exhibit.

The lower semiconductor package 100 can be a lower base substrate 110 , an interposer 120 which is on the lower base substrate 110 is placed and TSVs 122 has, and a lower semiconductor chip 130 which is on the interposer 120 attached and electrically with the interposer 120 is connected.

The upper semiconductor package 200 can on the lower semiconductor package 100 be placed and can be an upper semiconductor chip 230 exhibit. The upper semiconductor package 200 may be an upper casting component 250 comprising the upper semiconductor chip 230 seals.

The package connection components 260 can on the interposer 120 be placed and can the upper semiconductor package 200 with the interposer 120 connect electrically. The package connection components 260 for example, outside the lower semiconductor chip 130 be placed. The semiconductor package 1 can continue an external or external Vergussbauteil 170 which is the interposer 120 seals.

The lower semiconductor package 100 will now be described in detail.

The lower base substrate 110 can be glass, ceramic or plastic. The lower base substrate 110 may be a substrate for semiconductor packages, for example, a printed circuit board (for example, polyamide, FR-4, etc.), a ceramic substrate, or a tape wiring substrate. Upper pads 112 can on the upper surface of the lower base substrate 110 be placed and lower pads 114 can be on the lower surface of the lower base substrate 110 be placed.

External connection components 116 can on the lower pads 114 of the lower base substrate 110 be placed to electrically and / or physically with the lower pads 114 to be connected. The lower base substrate 110 can via the external connection components 116 be electrically connected to the outside. As a result, the lower semiconductor package 100 the upper semiconductor package 200 and both of them electrically outward via the external connection components 116 be connected. The external connection components 116 may be, for example, solder balls. Alternatively, the external connection components 116 form a flip-chip interconnect structure having a grid array such as a pin grid array, a ball grid array, or a land grid array. In some embodiments, the lower base substrate 110 and external connection components 116 the package substrate and package connectors for the semiconductor package 1 exhibit. For example, the external connection components 116 the package connections form all external communications for the chips within the semiconductor package 1 and a printed circuit board of the system on which the semiconductor package 1 is mounted (for example, a motherboard of a computer, a printed circuit board of a portable electronic device, etc.) to provide or provide. In one example, the lower base substrate 110 composed of only two PCB layers (an upper PCB layer stacked on a lower PCB layer) and only three wiring layers. The first wiring layer may include a redistribution layer on an upper surface of the lower base substrate 110 The second wiring layer may be a redistribution layer on the lower surface of the lower base substrate, and the third wiring layer may be a redistribution layer formed between the two PCB layers. The two PCB layers of the lower base substrate 110 may have vias connecting wiring of the wiring layers at their opposite surfaces to form desired electrical connections as further discussed herein, for example.

The interposer 120 may be at the lower base substrate 110 be placed. The interposer 120 can be the interposer element 20 which, with reference to the 1 and 2 is described. The interposer 120 can be a base layer 121 , TSVs 122 , first pads 123 , second pads 124 , an insulating layer 125 and a wiring pattern layer 126 exhibit.

The first pads 123 can be on the bottom surface of the base layer 121 be placed and the second pads 124 can on the upper surface of the base layer 121 be placed. The second pads 124 can the upper pads 58 which, with reference to 3 are described. The base layer 121 may comprise an insulating material as described with reference to FIG 2 is described.

The TSVs 122 can be part of the base layer 121 penetrate. The TSVs 122 may be a conductive material as with reference to the base portion 32 of the 2 is described. The TSVs 122 can electrically the first pads 123 with the second pads 124 connect each. In other words, the TSVs 122 electrical connection paths or electrical connection paths between the first pads 123 to the second pads 124 provide.

The insulating layer 125 can be on the base layer 121 be placed. The insulating layer 125 may be a wiring pattern layer 126 having a wiring pattern. The wiring pattern layer 126 can be electrically and / or physically with the second pads 124 the interposer 120 be connected. As a result, the wiring pattern layer 126 electrically with the TSVs 122 be connected. The wiring pattern layer 126 can also be electrically and / or physically with the lower semiconductor chip 130 and the package connection components 260 be connected. The wiring pattern layer 126 can the wiring pattern 54 which have been described above with reference to 3 are described. The wiring pattern layer 126 may act as and / or have a redistribution pattern as above with reference to the wiring portion 50 of the 3 is described.

Interposer connecting members 128 can be under the base layer 121 be placed. The interposer connection components 128 can be electrically and / or physically with the first pads 123 the interposer 120 be connected. The interposer connection components 128 can be electrically and / or physically with the upper pads 112 of the lower base substrate 110 be connected. As a result, the TSVs 122 electrically with the lower base substrate 110 via the interposer connection components 128 be connected. The interposer connection components 128 may be, for example, solder balls. Alternatively, the interposer connection components 128 a flip-chip interconnect structure comprising a grid array, such as a pin grid array, a ball grid array, or a land grid array.

The lower semiconductor chip 130 can on the interposer 120 be placed. The lower semiconductor chip 130 may be a logic semiconductor chip or a memory semiconductor chip as described above. Lower connection components 140 can under the lower semiconductor chip 130 be placed. The lower semiconductor chip 130 may be electrically connected to the wiring pattern layer 126 the interposer 120 over the lower connecting components 140 be connected. The lower semiconductor chip 130 can be in a face-down configuration with the interposer 120 be connected. The lower semiconductor chip 130 can also be electric with the TSVs 122 over the lower connecting components 140 be electrically connected. Although the lower connecting components 140 Can be solder balls, the invention is not limited thereto. For example, the lower connection components 140 Be bonding wires. Alternatively, the lower connecting components 140 form a flip-chip interconnect structure that includes a grid array, such as a pin grid array, a ball grid array, or a land grid array.

The lower connecting components 140 may be more dense than the interposer connection components 128 , For example, a distance d4 between centers of the lower connecting components 140 less than a distance d5 between centers of the interposer connection components 128 , The lower connecting components 140 can be smaller in size than the interposer connector components 128 , In this case, the wiring pattern layer 126 which has a wiring pattern corresponding to the wiring pattern 54 , which is described above with reference to 3 has functioned as a rewiring pattern.

The lower semiconductor chip 130 can through the lower Vergussbauteil 150 be sealed and therefore it can be protected from external shocks or influences. An upper surface of the lower semiconductor chip 130 can from the lower Vergussbauteil 150 be exposed.

The lower casting component 150 can the package connection components 260 exhibit. The package connection components 260 will now be described in detail.

The lower casting component 150 can be an incompletely filled component 151 (please refer 23 to 28 ), which under the lower semiconductor chip 130 is placed, ie a space between the lower connecting components 140 fills and a lateral Seitenvergussbauteil 152 (please refer 23 to 28 ), which on the incompletely filled component 151 is placed and the lateral side of the lower semiconductor chip 130 seals. The lower casting component 150 can be formed by a Molded Underfilling technique (MUF = Molded Underfilling). The lower casting component 150 may have an insulating material. The upper casting component 250 and the lower casting component 150 can be made of the same material or of different materials. The lower casting component 150 will be described in detail below with reference to the 23 to 28 to be discribed.

The interposer 120 , the lower semiconductor chip 130 and the package connector components 260 can through the external Vergussbauteil 170 be sealed and therefore they may be protected from external or external shocks. The outer casting component 170 can be a lateral side of the interposer 120 caulk. The external or external casting component 170 can extend to a space below the interposer 120 to fill, ie he can spaces between the interposer connection components 128 to fill. The outer casting component 170 may also extend to the lateral side of the lower Vergussbauteils 150 and a part of the upper portions of the package connection components 260 to seal or seal. The outer casting component 170 may continue to extend to the upper semiconductor package 200 to contact or touch. For example, the outer Vergussbauteil 170 extend to further a contact portion 172 to show which the lower surface of an upper base substrate 210 contacted or touched. The outer casting component 170 can also be formed by a MUF technique. The outer casting component 170 can be constructed of an insulating material. The outer Vergussbauteil 170 may be a resin or a plastic or mainly composed of a combination of silica and resin or plastic. The outer casting component 170 may be a homogeneous integral material. The outer casting component 170 and the lower casting component 150 may have the same material or different materials.

The upper semiconductor package 200 will now be described in detail. The upper semiconductor package 200 can the upper base substrate 210 and the upper semiconductor chip 230 exhibit. The upper semiconductor chip 230 can on the upper base substrate 210 be placed.

The upper base substrate 210 may have glass, a ceramic or plastic or plastic. The upper base substrate 210 may be a substrate for semiconductor packages, such as a printed circuit board, a ceramic substrate, or a ribbon wiring substrate. Upper pads 212 which electrically and / or physically with the upper semiconductor chip 230 can be connected in an upper portion of the upper base substrate 210 be placed and lower pads 214 electrically and / or physically with the package connector components 260 can be connected in a lower portion of the upper base substrate 210 be placed.

The upper semiconductor chip 230 is on the upper base substrate 210 placed. The upper semiconductor chip 230 may be a logic semiconductor chip or a memory semiconductor chip as described above. Upper connecting components 240 can be below the top semiconductor chip 230 be placed. The upper semiconductor chip 230 can be electrically connected to the upper base substrate 210 over the upper connecting components 240 be connected. For example, the upper connection components 240 electrically and / or physically with the upper pads 212 be connected. Although the upper connecting components 240 Can be solder balls, the inventive concept is not limited thereto. For example, the upper connection components 240 Bonding wires or bonding wires be. Alternatively, the upper connecting components 240 form a flip-chip interconnect structure having a grid array, such as a pin grid array, a ball grid array, or a land grid array.

The upper semiconductor chip 230 can through the upper Vergussbauteil 250 be sealed and protected from the environment. The upper casting component 250 may be an incompletely filled or underfilled component, which under the upper semiconductor chip 230 is placed, ie which spaces between the upper connecting components 240 and a cover member having the upper portion of the lower semiconductor chip 230 seals. The upper casting component 250 can be formed by a MUF technique. The upper casting component 250 may have an insulating material. The upper casting component 250 and the lower casting component 150 may have the same material or different materials. The upper casting component 250 and the outer Vergussbauteil 170 can be constructed of the same material or different materials. In an alternative embodiment, the upper package may 200 have no upper Vergussbauteil and the upper semiconductor chip 230 may be exposed after the formation of the upper package (though subsequent processes such as those used to package the semiconductor 1 to form the upper semiconductor chip 230 to encapsulate).

The upper semiconductor package 200 can on the lower semiconductor package 100 be placed. The lower semiconductor package 100 and the upper semiconductor package 200 can be electrically connected to each other via the package connection components 260 be connected.

The package connection components 260 will now be described in detail. The package connection components 260 can on the interposer 120 be placed and can be electrically connected to the interposer 120 be connected. An underbump metallization layer (UBM layer - not shown) may be the only element that exists between the interposer 120 and the package connection components 260 is arranged in between. The package connection components 260 can inside openings 160 be placed below with reference to 19 be described and the openings 160 may extend downwardly to have a uniform width or narrowing width. The package connection components 260 can be solder balls.

The package connection components 260 may be a plurality of package connection components. For example, the package connector components 260 first package connection components 270 which electrically and / or physically with the interposer 120 (for example, through a UBM layer) and second package connection components 280 which electrically and / or physically with the upper semiconductor package 200 (For example, by a UBM layer) are connected. The first package connection components 270 and the second package connection components 280 may have the same shape, for example a spherical shape. Attached upper and lower surfaces of the spherical shape may be slightly flattened. The first package connection components 270 and the second package connection components 280 can be the same sizes to have. The first package connection components 270 and the second package connection components 280 may be connected to each other using a thermal compression process and / or a reflow process, and accordingly transformed into a one-body structure. Each of the first package connection components 270 and the second package connection components 280 may have a shape other than the spherical shape and / or they may have different shapes from each other. The first package connection components 270 and the second package connection components 280 can have different sizes. For example, the first package connection components 270 larger or smaller sizes than the second package connector components 280 , Exemplary Package Connection Components 260 will be described in detail below with reference to FIGS 38 to 42 to be discribed.

An air gap 180 can be between the upper semiconductor package 200 and the lower semiconductor package 100 be placed. The air gap 180 can over the lower semiconductor chip 130 be placed and, consequently, thermal expansion due to an operation of the lower semiconductor chip 130 compensate. A height of each package connector 260 regarding the interposer 120 is greater than a sum of the heights of the lower semiconductor chip 130 and the lower connecting member 140 to get through the air gap 180 to extend and with the lower surface of the upper package 200 to make a connection. The height of the uppermost surface of the lower semiconductor chip 130 may be formed at a location which is lower than the height of the upper of the package connection components 260 ,

The lower semiconductor chip 130 and the upper semiconductor chip 230 can be the same size or different sizes. For example, the lower semiconductor chip 130 have a larger size than the upper semiconductor chip 230 , The lower semiconductor chip 130 and the upper semiconductor chip 230 can have the same function or different functions. For example, the lower semiconductor chip 130 a logic semiconductor chip as described above and the upper semiconductor chip 230 For example, a memory semiconductor chip may be as described above. For example, the lower semiconductor chip 130 a driver chip for driving a mobile device or the like as described above and the upper semiconductor chip 230 may be a DRAM chip passing through the lower semiconductor chip 130 driven or operated. As another example, the upper semiconductor chip 230 a flash memory chip capable of functioning as an external storage device of a mobile device. The lower semiconductor chip 130 may be a master chip, such as a stand-alone driver master chip (eg, receiving, buffering, and driving without a memory array), or a memory chip acting as a master chip, and the top semiconductor chip 230 may be a slave chip, such as a slave memory chip.

The semiconductor package 1 may be a package-on-package (POP) in which a plurality of semiconductor packages are stacked and integrally formed, or the semiconductor package 1 may be a system in package (SIP = System In Package) in which a logic semiconductor chip and a memory semiconductor chip are integrated into a single package.

The semiconductor package 1 may be reduced in size by including the interposer 120 , For example, the semiconductor package 1 the air gap 180 which has a thickness of the opening of 50 μm or less, the lower semiconductor chip 130 has a thickness of about 50 μm or less, and wherein the lower connecting members 140 have a height of about 30 μm or less or a height of 20 μm or less. Here are the lower connecting components 140 Be connecting components, which are typically referred to as μ-bumps (microbumps) or C4 bumps. As a result, a sum of the thicknesses of the air gap 180 of the lower semiconductor chip 130 and each of the lower connection components 140 about 0.13 mm or less or 0.12 mm or less. Thus, the height is from an upper surface of the interposer 120 to the lower surface of the upper package 200 about 0.13 mm or less, or 0.12 mm or less. A distance from the top surface of the interposer 120 to the upper surface of the lower semiconductor chip 130 is 80 μm or less, or 70 μm or less.

In addition, the total thickness of the package can be reduced. If the interposer 120 from the wafer interposer 10 is formed, the wiring section 50 and vias / TSVs 42 can be fabricated using a wafer level process (such as a photolithography process) with fine wiring sizes. For example, a wiring portion of at least some of the adjacent conductors of the wiring pattern layer 126 10 μm or less, or 5 μm or less.

The use of the wiring section 50 the interposer 120 allows a redistribution or rewiring of the signal of the upper and lower chip 230 and 130 , This can be a designer's freedom to get rid of Wiring layers from the lower base substrate 110 which is desired or needed, reducing the thickness of the package. For example, the lower base substrate 110 have only two or less redistribution layers and / or have a thickness of 220 μm or less.

In addition, backward grinding of the lower semiconductor chip reduces 130 the total height of the package. If the interposer 120 is formed of a material having a CTE (Coefficient of Thermal Expansion = CTE) equal to or close to that of the lower semiconductor chip 130 has, the lower semiconductor chip 130 be made even thinner with a minimum concern for a subsequent break due to a mismatch of the thermal expansion coefficients. For example, the thermal expansion coefficients (CTE) of the interposer 120 and the lower semiconductor chip 130 both less than 6 ppm / K, or less than 4 ppm / K. The thermal expansion coefficient of the interposer 120 may not be larger than twice the thermal expansion coefficient of the lower semiconductor chip 130 , In some embodiments, the thermal expansion coefficient and the interposer may be similar 120 not larger than about 1.3 times the thermal expansion coefficient of the lower semiconductor chip 130 , In some embodiments, the interposer may 120 and the lower semiconductor chip 130 have substantially the same thermal expansion coefficient (for example, they may be formed of the same material).

Additionally, if the interposer 120 is formed of a material having a thermal expansion coefficient which is the same as or almost that of the lower semiconductor chip 130 , lower connecting components 140 be made smaller with a minimal risk of damage (such as breaking or peeling). For example, the lower connection components 140 have a height of 20 microns or less.

With a reduced height between the top surface of the interposer 120 to the lower surface of the upper package 200 can be the size of the package connection components 260 can also be reduced, both vertically and horizontally. With a reduction in the horizontal size (for example, width in 7 ) can be the distance of the package connector components 260 be made smaller. For example, the distance of the package connector components 260 less than or equal to 0.4 mm, or less than or equal to 0.3 mm. With a small gap size, the total area of the package can be made small or small. As an example, with reference to the enlarged portion of FIG 5 a small gap between package connector components 70 a reduced size of each interposer 20 ,

On the other hand, a semiconductor package containing the interposer 120 not having an air gap having a thickness of about 50 μm, a lower semiconductor chip having a thickness of about 100 μm, and lower connecting members having a height of about 80 μm for a total pitch of 0.23 mm , In addition, a thicker package substrate may be needed to accommodate the desired redistribution.

8th is chic concept view showing exemplary electrical connections within the semiconductor package 1 of the 7 illustrated. Referring to 8th can the semiconductor package 1 have electrical paths or paths along paths or paths, which are indicated by a first arrow A, a second arrow B and a third arrow C, a fourth arrow D and a fifth arrow E. Each electrical path may include signal communications (eg, data, addresses, control, clock, etc.) and / or power (e.g., Vdd) and / or reference voltages (eg, Vss, Gnd) for respective signal communication chip pads and / or power supplies. Pads and / or reference voltage chip pads of the lower semiconductor chip 130 and / or upper semiconductor chips 230 provide. The signal communication chip pads of the lower semiconductor chip 130 may include data pads, address pads, control pads, and / or clock pads, each including a data buffer, an address buffer, a control buffer, and a clock buffer of the lower semiconductor chip 130 as it is known are connected. The signal communication chip pads of the upper semiconductor chip 230 may comprise data pads, address pads, control pads, and / or clock pads which are related to a data buffer, an address buffer, a control buffer, and a clock buffer of the upper semiconductor chip 230 connected as is known. The power supply chip pads and reference voltage chip pads of the lower semiconductor chip 130 can with an internal power supply circuit of the lower semiconductor chip 130 be connected. The power supply chip pads and reference voltage chip pads of the upper semiconductor chip 230 can with an internal power supply circuit of the upper semiconductor chip 230 be connected.

Along the way, which is indicated by the first arrow A, can the upper semiconductor chip 230 be electrically connected to the outside of the semiconductor package. For example, the upper semiconductor chip 230 electrically with the outer of the semiconductor package 1 over the upper connecting components 240 , the upper base substrate 210 , the package connection components 260 , the wiring pattern layer 126 , the TSVs 122 , the interposer connection components 128 , the lower base substrate 110 and the outer connecting member 116 be connected. The electrical path, which is indicated by a first arrow A, may be the upper semiconductor chip 230 be dedicated. The electrical path indicated by a first arrow A may be electrically isolated and / or may not be electrically connected at all to the lower semiconductor chip 130 , The electrical path indicated by arrow A may connect to data, address, control and / or clock pads of the top semiconductor chip 230 form.

Along the path, which is indicated by the second arrow B, the lower semiconductor chip 130 electrically with the outside of the semiconductor package 1 be connected. For example, the lower semiconductor chip 130 electrically with the outside of the semiconductor package 1 over the lower connecting components 140 , the wiring pattern layer 126 , the TSVs 122 , the interposer connection components 128 , the lower base substrate 110 and the external connection components 116 be connected. The electrical path indicated by the second arrow B may be the lower semiconductor chip 130 be dedicated. The electrical path indicated by arrow B may be electrically isolated and / or may not be electrically connected to the upper semiconductor chip 230 , The electrical path indicated by the arrow B may connect to data, address, control and / or clock pads of the lower semiconductor chip 130 produce.

Along the path, which is indicated by the third arrow C, the upper semiconductor chip 230 electrically with the lower semiconductor package 130 be connected. For example, the upper semiconductor chip 230 electrically to the lower semiconductor chip 130 over the interposer 120 be connected. For example, the upper semiconductor chip 230 electrically to the lower semiconductor chip 130 over the upper connecting components 240 , the upper base substrate 210 , the package connection components 260 , the wiring pattern layer 126 and the interposer connection components 140 be connected. The electrical path indicated by the third arrow C may be obtained by wiring the wiring pattern 126 the interposer 120 extend without any connection to any TSV of the interposer 120 to form (or otherwise a compound which extends through the interposer substrate 120 and / or to a lower side of the interposer substrate 120 to show). The electrical path indicated by the third arrow C may not electrically match an electrical path external to the semiconductor package 1 be connected. The electrical path indicated by the third arrow C may be dedicated to an electrical path (e.g., communication path) between the lower semiconductor chip 130 and the upper semiconductor chip 230 provide. The electrical path, indicated by the arrow C, may be data, address, control and / or clock pads of the upper semiconductor chip 230 and corresponding ones of data, address, control and / or clock pads of the lower semiconductor chip 130 connect. Along the path, which is indicated by the fourth arrow D, the upper semiconductor chip 230 electrically with the lower semiconductor package 130 be connected. For example, the upper semiconductor chip 230 electrically to the lower semiconductor chip 130 about the TSVs 122 the interposer 120 be connected. For example, the upper semiconductor chip 230 electrically to the lower semiconductor chip 130 over the upper connecting components 240 , the upper base substrate 210 , the package connection components 260 , the wiring pattern layer 126 , the TSVs 122 , the interposer connection components 128 , the lower base substrate 110 , the interposer connection components 128 , the TSVs 122 , the wiring pattern layer 126 and the lower connection components 140 be connected. The electrical path indicated by the fourth arrow D may not electrically match any electrical path external to the semiconductor package 1 be connected. The electrical path indicated by the fourth arrow D may be dedicated to an electrical path (e.g., a communication path) between the lower semiconductor chip 130 and the upper semiconductor chip 230 provide or provide. In another example, the electrical path indicated by the fourth arrow D may not be to and / or over a lower surface of the lower base substrate 110 extend beyond. The electrical path, indicated by the arrow D, may be data, address, control and / or clock pads of the upper semiconductor chip 230 and respective ones of data, address, control and / or clock pads of the lower semiconductor chip 130 connect. Alternatively, the path indicated by the fourth arrow D may further include a path indicated by the fifth arrow E (shown in a dotted line). In other words, along a combination of the path indicated by the fourth arrow D and the path indicated by the fifth arrow E, the upper semiconductor chip 230 electrically with the lower semiconductor package 130 be connected, and at the same time, the upper semiconductor chip 230 and the lower semiconductor chip 130 electrically with the outside of the semiconductor package 1 be connected. The electrical path indicated by the arrow E may be data, address, control and / or clock Pads of the upper semiconductor chip 230 with respective ones of data, address, control and / or clock pads of the lower semiconductor chip 130 and respective one of data, address, control and / or clock terminals (executed by corresponding external connection components 116 ) of the lower base substrate 110 connect.

Hereinafter, the semiconductor package will be described 1 which has the following exemplary electrical connections, with reference to FIG 8th described. It should be noted that each of the electric paths indicated by a first arrow A, a second arrow B, a third arrow C, a fourth arrow D, and a fifth arrow E, to which reference is made in the description or can constitute a plurality of ways having the respective characteristics described above. First, the lower semiconductor chip 130 a logic chip, and the upper semiconductor chip 230 may be a memory chip, such as a DRAM chip or flash memory chip. For example, the lower semiconductor chip 130 electrically to the upper semiconductor chip 230 be connected and can be designed to receive signals to and from the upper semiconductor chip 230 to transmit and receive.

One or more power paths, such as a Vdd path, may travel along the path indicated by the first arrow A to the top semiconductor chip 230 be provided. This power signal path is not electrically connected to the lower semiconductor chip 130 connected.

A signal path for transmitting a command from an external interface or the like may be provided via one or more paths indicated by the second arrow B. In other words, the lower semiconductor chip 130 receive a command from an external source. Power, such as Vdd, can also be used for the lower semiconductor chip 130 along one or more paths indicated by the second arrow B may be provided.

Along one or more paths indicated by the third arrow C may be a command for the upper semiconductor chip 230 from the lower semiconductor chip 130 be provided. This command may be a command which is external through the lower semiconductor chip 130 is received and transmitted to the upper semiconductor chip on. Alternatively or additionally, this command may be provided by the lower semiconductor chip 130 be generated. A signal may be from the upper semiconductor chip 230 to the lower semiconductor chip 130 along one or more paths indicated by the third arrow C. In other words, an input / output signal path between the lower semiconductor chip 130 and the upper semiconductor chip 230 along one or more paths indicated by the third arrow C may be provided.

A function similar to the path indicated by the third arrow C may be provided over the path indicated by the fourth arrow D. For example, an input / output signal path between the lower semiconductor chip 130 and the upper semiconductor chip 230 over the path indicated by the fourth arrow D may be provided. In particular, it may be because a wiring which is in the interposer 120 is formed finer than that which is in the lower base substrate 110 may be advantageous in that a signal sensitive to an RC delay may be transmitted through the wiring formed in the lower base substrate 110 is formed, instead of the wiring, which in the interposer 120 is formed. The wiring which is in the lower base substrate 110 is formed, may have a thicker width and / or a lower or higher conductivity than the wiring, which in the Interposer 120 is formed. Thus, an electric path indicated by the fourth arrow D may have a higher conductivity than an electric path indicated by the third arrow C.

By a combination of the paths indicated by the fourth and fifth arrows D and E, a Vss path and / or a ground path may be provided for each of the lower and upper semiconductor chips 130 and 230 be provided. In other words, if Vss and / or ground is provided from an external source, then the Vss and / or ground path in the interposer may be provided 120 be separated and therefore he likes for each of the lower and upper semiconductor chip 130 and 230 be provided. Alternatively, if Vss and / or the ground signal is provided from an external source, the Vss and / or ground path may be in the lower base substrate 110 be separated and to each of the lower and upper semiconductor chip 130 and 230 be transmitted. In one example, the lower and the upper chip share 130 and 230 one, several, or all Vss and / or ground connections to an external source (e.g., path (s) E) and each of the bottom and top chips 130 and 230 have at least one, several and / or all dedicated Vdd connections (for example, paths B and A).

In an example, the upper semiconductor chip 230 for example, be a flash memory such as a NAND flash memory. In another example, the lower semiconductor chip 130 through separate devices such as for example, be replaced several chips. In another example, the one or more lower semiconductor chip (s) may 130 to and from the upper semiconductor chip 230 no signals are transmitted and received. In another example, the upper semiconductor chip may be like 230 Commands received only directly from external sources.

The 9 to 22 FIG. 15 are cross-sectional views illustrating a method of forming the semiconductor package. FIG 1 of the 7 according to some embodiments. According to these embodiments, multiple semiconductor packages 1 simultaneously using the same wafer as an interposer 10 with several lower chips 130 , upper chips 230 and their connections formed at respective multiple locations of the wafer (e.g., on each interposer element 20 the interposer 10 of the 1 ) are formed. For the sake of clarity, however, below will be limited to the manufacture of only one semiconductor package 1 However, it will be appreciated that the description for the other semiconductor packages 1 , which are made of the wafer, relevant or authoritative.

Referring to 9 has the interposer wafer 10 a plurality of interposers 120 (just an interposer 120 is shown) on which the vias or vias 122 to have. The interposer wafer 10 can be a lower section 30 , an upper section 40 , which is on the lower section 30 is placed and a wiring section 50 , which is on the upper section 40 is placed. In the interposer wafer 10 , which in the 9 to 17 is only one area corresponding to a single semiconductor package 1 illustrated.

The lower section 30 and the top section 40 can the base section 121 build up. The upper section 40 can the vias 122 comprising a portion of the base portion 121 penetrate. The upper section 40 can the second pads 124 having, which electrically and / or physically with the vias 122 connected, and the second pads 124 can the upper pads 58 (please refer 3 ) correspond. As above with reference to 4 is described, the upper section likes 40 the second pads 124 do not have. Although the lower section 30 the vias 42 may not be illustrative, this is only an example, the vias may substitute through the entire interposer base section 121 pass. For example, the vias 42 be placed to go through both the upper section 40 as well as the lower section 30 to step through. The wiring section 50 can the insulating layer 125 and the wiring pattern layer 126 which is inside the insulating layer 125 is placed. The wiring pattern layer 126 can the above-mentioned wiring patterns 54 (please refer 3 ) correspond. The wiring pattern layer 126 may be a redistribution pattern.

Referring to 10 are the first package connector components 270 on the interposer wafer 10 appropriate. The first package connection components 270 can be at an upper external section of each of the interposer 120 which are in the interposer wafer 10 are included. The first package connection components 270 can be electrically connected to the wiring pattern layer 126 be connected. The first package connection components 270 can be solder balls and can be attached to the wiring pattern layer 126 be attached by use of a thermal compression process and / or a reflow process.

Referring to 11 is the lower semiconductor chip 130 on the interposer wafer 10 appropriate. The lower semiconductor chip 130 can be at a middle section of each of the interposer 120 of the interposer wafer 10 to be appropriate. The lower connecting components 140 can be below the lower semiconductor chip 130 be placed. The lower semiconductor chip 130 may be electrically connected to the wiring pattern layer 126 the interposer 120 over the lower connecting components 140 be connected. The lower semiconductor chip 130 can also with the TSVs 122 over the lower connecting components 140 be electrically connected. The lower connecting components 140 can be solder balls and can be attached to the wiring pattern layer 126 be attached by using a thermal compression process and / or a reflow process. A plurality of lower semiconductor chips 130 may be included.

An operation of attaching the first package connection components 270 and a process for mounting the lower semiconductor chip 130 may be performed in an order reverse to the above-described order, or they may be performed simultaneously.

Referring to 12 becomes the lower casting component 150 , which is the lower semiconductor chip 130 seals, formed. The lower casting component 150 can the insufficiently filled component 151 (please refer 23 to 28 ), which under the lower semiconductor chip 130 is placed and a space between the lower connecting components 140 fills, and the lateral Seitenvergussbauteil 152 (please refer 23 to 28 ), which on the insufficiently filled component 151 ( please refer 23 to 28 ) and the lateral side of the lower semiconductor chip 130 seals. The lower casting component 150 can the lower semiconductor chip 130 completely seal off. The underfilled component and the lateral side potting member may comprise the same material or different materials.

Referring to 13 becomes the lower casting component 150 which is on the lower semiconductor chip 130 is placed, partially removed. When removing an upper surface 132 of the lower semiconductor chip 130 be exposed. In addition, the removal may include a step of thinning the lower semiconductor chip 130 by removing an upper portion of the upper semiconductor chip 130 and the lower semiconductor chip 130 can be thin. For example, the thickness of the lower semiconductor chip 130 Be 50 microns or less. The removal may be performed by, for example, chemical mechanical polishing (CMP). The uppermost surface of the lower semiconductor chip 130 can flush or flush and / or coplanar with the top surface of the lower Vergussbauteils 150 be in some examples. Alternatively, the uppermost surface of the lower semiconductor chip 130 and the uppermost surface of the lower potting member is at a distance of not more than 5 μm from a first plane. The uppermost surface of the lower casting component 150 may have different configurations with respect to the uppermost surface of the lower semiconductor chip 130 to have. This will be explained in detail below with reference to FIGS 23 to 28 to be discribed.

Referring to 14 is an auxiliary substrate 134 on or on the lower semiconductor chip 130 appropriate. The attachment may include an operation of forming an adhesive layer 136 on the upper surface 132 of the lower semiconductor chip 130 and an operation of attaching an auxiliary substrate 134 on or on the adhesion or adhesive layer 136 exhibit. The auxiliary substrate 134 may have a size which extends over the lower Vergussbauteil 150 extends. The auxiliary substrate 134 may be formed of a rigid material and include a metal, glass, ceramic or the like. The adhesive layer 136 may be an adhesive tape or adhesive solution.

Referring to 15 becomes the lower section 30 of the interposer wafer 10 removed so that the vias / TSVs 122 are exposed. As a result, the TSVs 122 from a lower surface 129 of the interposer wafer 10 be exposed, which in the upper section 40 is placed. Each of the interposer 120 can the penetrated or penetrated TSVs 122 exhibit. The removal may be performed, for example, by mechanical polishing, by CMP, or by a method of forming and separating a weak layer within the interposer wafer 10 For example, a Smart Cut method. In the present operation, the auxiliary substrate 134 have such a sufficient thickness that the thinned interposer wafer 10 is not deformed and the interposer wafer 10 may act as a support substrate for movement to subsequent processing equipment or equipment.

Referring to 16 are the interposer connection components 128 at the interposer 120 attached to the TSVs electrically 122 to be connected. For example, the first pads 123 the interposer 120 which are electrically and / or physically with the TSVs 122 connected on the bottom surface 129 the interposer 120 educated. Then the interposer connection components 128 which are electrically connected to the TSVs 122 connected to the first pads 123 the interposer 120 which is on the lower surface 129 of the interposer wafer 10 is formed, attached. The interposer connection components 128 can be solder balls and can be attached to the first pattern 123 by using a thermal compression process and / or a reflow process. In the present operation, the auxiliary substrate 134 have such a sufficient thickness that the thinned interposer wafer 10 is not deformed and that the interposer wafer 10 can act as a carrier substrate for movement to subsequent processing equipment.

Referring to 17 becomes the auxiliary substrate 134 , which is on the upper surface 132 of the lower semiconductor chip 130 attached, removed. At this time, the adhesive layer can also be used 136 be removed. After that, the interposer wafer 10 along the division lines 12 as in the 1 and 2 is shown diced, creating a plurality of separate interposers 120 is formed, with which the lower semiconductor chip 130 electrically connected.

Referring to 18 becomes the interposer 120 on the lower base substrate 110 appropriate. The upper pads 112 may be on or on the upper surface of the lower base substrate 110 be placed and the lower pads 114 may be on or on the lower surface of the lower base substrate 110 to be placed. The lower base substrate 110 and the interposer 120 can be electrically connected to each other via the interposer connection components 128 get connected. The Interposer connecting members 128 can at the first patterns 112 of the lower base substrate 110 be attached by using a thermal compression process and / or a reflow process. The external connection components 116 can be on the lower surface of the lower base substrate 110 to be placed. The external connection components 116 may be, for example, solder balls. Alternatively, the external connection components 116 form a flip-chip interconnect structure having a grid array such as a pin grid array, a ball grid array, or a land grid array. As a result, the lower semiconductor package 100 be formed.

It may be understood by one skilled in the art that a case in which the external connection components 116 on the lower base substrate 120 be attached after the upper semiconductor package 200 on or on the lower semiconductor package 100 is attached or a case in which the external connection components 116 after the outer casting component 170 on the lower base substrate 110 attached are alternative embodiments. Other operations, which are not described in detail herein, will be apparent to those skilled in the art.

Referring to the 19 to 21 becomes the upper semiconductor package 200 which is the upper semiconductor chip 230 has, on or on the interposer 120 appropriate. The attachment can have the following steps:
Referring to 19 becomes the lower casting component 150 Optionally removed to the openings 160 to form each of which the first package connection components 270 uncover. The openings 160 can be formed by a lithographic etching or by using a laser. Each of the openings 160 may extend downwardly to have a uniform width or to have a narrowing width.

Referring to the 20 and 21 becomes the upper semiconductor package 200 containing the second package connection components 280 comprising the first package connection components 270 correspond, provided. The second package connection components 280 are below the upper base substrate 210 of the upper semiconductor package 200 placed. The upper semiconductor package 200 is on or on the lower semiconductor package 100 placed. Then the second package connection components 280 in the openings 160 introduced, so that the first package connection components 270 each electrically and / or physically with the second package connection components 280 are connected. As a result, a structure which is in 21 shown is formed. An air gap 180 can be between the lower semiconductor package 100 and the upper semiconductor package 200 be formed.

Referring to 22 becomes the outer casting component 170 which is the interposer 120 and the lower semiconductor chip 130 sealed formed. The outer casting component 170 can the spaces between the interposer connection components 128 fill in and can the lateral side of the interposer 120 caulk. For example, forming the outer Vergussbauteils 170 a step of insufficient filling or underfilling the interposer 120 exhibit the spaces between the interposer connection components 128 to fill and a step of sealing the lateral side of the interposer 120 and / or the lateral side of the package connection component 260 , The outer casting component 170 may extend to an upper surface of the lower base substrate 110 to contact or touch. The outer casting component 170 can continue the contact section 172 having the lower surface of the upper base substrate 210 contacted or touched. The contact section 172 may be towards the inner side of the package connector components 260 extend, and may the lower semiconductor chip 130 touch. As a result, the air gap 180 in an inner area between the package connection components 260 be placed. The air gap 180 must the outside atmosphere of the package after forming the outer Vergussbauteils 170 not be exposed.

Then electrical connections between the lower semiconductor package 100 to the upper semiconductor package 200 manufactured or improved to the formation of the semiconductor package of 7 to complete. This electrical connection can be achieved by electrically and / or physically connecting the first package connection components 270 with the second package connection components 280 , The first package connection components 270 and the second package connection components 280 must be connected together using the thermal compression process and / or the reflow process. The air gap 180 can be between the upper semiconductor package 200 and the lower semiconductor package 100 be placed.

The formation of the outer casting component 170 and the electrical connection between the lower semiconductor package 100 and the upper semiconductor package 200 may be performed in an order reverse to the order described above.

The 23 to 28 are enlarged views illustrating cases in which the lower Vergussbauteil 150 which is in the Semiconductor package 1 of the 7 is included, changes. As a result, duplicate descriptions will now be made between the embodiment of FIG 7 and the embodiments 23 to 28 be left out.

Referring to 23 may be a lower casting component 150a an insufficiently filled component 151a which defines a space between the lower connecting components 140 fills and a lateral Seitenvergussbauteil 152a have, which on the insufficiently filled component 151a is placed, and the lower semiconductor chip 130 seals. The insufficiently filled component 151a can a space between the lower connecting components 140 fill and may be a portion of the lateral surface (for example, side surface) of the lower semiconductor chip 130 caulk. The insufficiently filled component 151a can the package connection components 260 contact and may contact a portion of the area between the lower semiconductor chip 130 and the package connection components 260 and / or a portion of an area between the package connection components 260 caulk. The lateral Seitenvergussbauteil 152a can on the insufficiently filled component 151a be placed and can be the lateral side of the lower semiconductor chip 130 caulk. The lateral Seitenvergussbauteil 152a may be a portion of the area between the lower semiconductor chip 130 and the package connection components 260 and / or a portion of the area between the package connector components 260 caulk.

The uppermost surface of the lower semiconductor chip 130 may be coplanar with the top surface of the lateral potting component 152a , Alternatively, the uppermost surface of the lower semiconductor chip 130 at a distance of not more than 5 μm from a first plane. In the removal, which above with reference to 13 is described, the lower Vergussbauteil 150 be partially removed, so that the lower semiconductor chip 130 and the lower casting component 150a have the top surfaces at the same level.

The insufficiently filled component 151a and the lateral side casting member 152a can be formed from different materials or be. For example, the insufficiently filled components 151a be formed of a highly flowable material to the flow of insufficiently filled material 151a increase to lower connecting components 140 under the semiconductor chip 130 to surround. The lateral Seitenvergussbauteil 152a can be less flowable by comparison. The lateral Seitenvergussbauteil 152a may be made of a material having a higher CTE (coefficient of thermal expansion) than the insufficiently filled material 151a , The same qualities can also be applied to insufficiently filled materials 151 be applied and lateral Seitenvergussbauteile 152 which are described elsewhere in this disclosure. Alternatively, the insufficiently filled component 151a and the lateral side casting member 152a can be formed of the same material and can be formed using the same process or various operations. The insufficiently filled component 151a and the lateral side casting member 152a can be formed by a MUF technique.

Referring to 24 may be a lower casting component 150b an incomplete filled component 151b which defines a space between the lower connecting components 140 fills, and a lateral Seitenvergussbauteil 152b which is on the incompletely filled component 151b is placed and the lower semiconductor chip 130 seals. The incomplete filled component 151b can a space between the lower connecting components 140 fill and may be a portion of the lateral surface of the lower semiconductor chip 130 caulk. The incomplete filled component 151b can the package connection components 260 touch and may be a portion of the area between the lower semiconductor chip 130 and the package connection components 260 and / or a portion of the area between the package connector components 260 caulk. The lateral Seitenvergussbauteil 152b can on the incomplete filled component 151b be placed and may be the lateral surface of the lower semiconductor chip 130 caulk. The lateral Seitenvergussbauteil 152b may be a portion of the area between the lower semiconductor chip 130 and the package connection components 260 and / or a portion of the area between the package connection components 260 caulk.

The uppermost surface of the lateral casting component 152b can with respect to the uppermost surface of the lower semiconductor chip 130 be recessed and therefore can a recess 153b be formed. For example, the upper surface of the lateral Vergussbauteils 152b become lower and lower in a direction away from the upper surface of the lower semiconductor chip 130 (for example, to the right in 24 ). This recess may be made during the removal, which is described above with reference to FIG 13 is described, are formed. For example, when a material used to form the lower semiconductor chip 130 has a high wear resistance and / or a high chemical resistance compared to a material which is used to the lateral Seitenvergussbauteil 152b to form, the rate of removal of the lateral Seitenvergussbauteils 152b be higher than that of the semiconductor chip 130 , and the recess 153b can be made. The recessed lateral Seitenvergussbauteil 152b For example, a buffering operation may be more uniform in terms of heat generation (eg, distributing heat more uniformly to avoid hot spots) and / or stress (eg, the possibility that the lower semiconductor chip 130 to reduce or prevent this).

Referring to 25 may be a lower casting component 150c an incomplete filled component 151c which defines a space between the lower connecting components 140 fills and a lateral Seitenvergussbauteil 152c which is on the incompletely filled component 151c is placed and the lower semiconductor chip 130 seals. The incomplete filled component 151c can a space between the lower connecting components 140 fill and may be a portion of the lateral surface of the lower semiconductor chip 130 caulk. The incomplete filled component 151c can the package connection components 260 and may contact a portion of the area between the lower semiconductor chip 130 and the package connection components 260 and / or a portion of the area between the package connector components 260 caulk. The lateral Seitenvergussbauteil 152c can on the incomplete filled component 151c be placed and may be the lateral surface of the lower semiconductor chip 130 caulk. The lateral Seitenvergussbauteil 152c may also include a portion of the area between the lower semiconductor chip 130 and the package connection components 260 and / or a portion of the area between the package connection components 260 caulk.

The uppermost surface of the lateral casting component 152c can with respect to the uppermost surface of the lower semiconductor chip 130 stand out and therefore can be a head start 154c be formed. For example, the upper surface of the lateral Vergussbauteils 152c (which also the upper surface of the projection 154c can be higher and higher in a direction away from the surface of the lower semiconductor chip 130 (for example, to the right in 25 ). This protrusion may be formed during removal, which is described above with reference to FIG 13 is described. For example, when a material used to form the lower semiconductor chip 130 has a low wear resistance and / or low chemical resistance compared to a material used to form the lateral side casting member 152c to form, the rate of removal of the lateral Seitenvergussbauteils 152c lower than that of the lower semiconductor chip 130 , and the lead 154c can be made. The lateral Seitenvergussbauteil 152c which is the lead 154c can, the air gap 180 more reliably maintaining the lower semiconductor chip 130 from the upper semiconductor package 200 spaced away.

Referring to 26 may be a lower casting component 150d an incomplete filled component 151d which defines a space between the lower connecting components 140 fills and the lower semiconductor chip 130 seals, and a lateral Seitenvergussbauteil 152d have, which on the outer side of the incompletely filled component 151d is placed and the incompletely filled component 151d seals. The incompletely filled components 151d can a space between the lower connecting components 140 fill and can cover the entire lateral surface of the lower semiconductor chip 130 caulk. The incompletely filled component may be from the package connector components 260 through the lateral Seitenvergussbauteil 152d be spaced. The lateral Seitenvergussbauteil 152d may be on the outer side of the incompletely filled component 151d be placed and can cover the entire lateral surface of the incompletely filled component 151d caulk. The lateral Seitenvergussbauteil 152d can also seal a region between the incompletely filled component 151d and the package connection components and / or an area between the package connection components 260 ,

By the incompletely filled component 151d from the package connector components 260 through the lateral Seitenvergussbauteil 152d may be a difference between the thermal expansion coefficient of the incompletely filled component 151d and the lateral side casting member 152d can be reduced and the thermal destruction of the package connection component 260 can be reduced. Because the package connection components 260 only through the lateral Seitenvergussbauteil 152d The reliability of the adhesion between the package connection components can be limited 260 and the lateral side pouring member 152d increase. In an etching operation of forming openings for the package connection components 260 can only the lateral Seitenvergussbauteil 152d be etched. Thus, the etching reliability can be increased.

The topmost surface of the incompletely filled component 151d and / or the uppermost surface of the lateral Vergussbauteils 152d can coplanar with the top surface of the lower semiconductor chip 130 be. The topmost surface of the incompletely filled component 151d and / or the uppermost surface of the lateral Seitenvergussbauteils 152d may be at a distance of not more than 5 μm from a first plane. In the removal, which above with reference to 13 is described, the lower Vergussbauteil 150 partially removed, leaving the bottom Semiconductor chip 130 and the lower casting component 150d have top surfaces at the same level.

Referring to 27 may be a lower casting component 150e an incomplete filled component 151e which has a space between the lower connection components 140 fills and the lower semiconductor chip 130 seals, and a lateral Seitenvergussbauteil 152e which is on the outer side of the incompletely filled component 151e is placed and the incompletely filled component 151e seals. The incomplete filled component 151e can a space between the lower connecting components 140 fill and can cover the entire lateral surface of the lower semiconductor chip 130 caulk. The incompletely filled components 151e can from the package connector components 260 through the lateral Seitenvergussbauteil 152e be spaced. The lateral Seitenvergussbauteil 152e can on or on the outer side of the incomplete filled component 151e be placed and can cover the entire lateral surface of the incompletely filled component 151e caulk. The lateral Seitenvergussbauteil 152e can also be an area between the incomplete filled component 151e and the package connection components 260 and / or an area between the package connection components 260 caulk.

The topmost surface of the incompletely filled component 151e and / or the uppermost surface of the lateral Vergussbauteils 152e can with respect to the uppermost surface of the lower semiconductor chip 130 be recessed, and therefore can a recess 153e be formed or be. For example, the uppermost surface of the incompletely filled component 151e and / or the uppermost surface of the lateral Seitenvergussbauteils 152e down in a direction away from the lower semiconductor chip 130 tend. This recess may be made while referring to above 13 be formed described distance. For example, when a material used to form the lower semiconductor chip 130 has a high wear resistance and / or a high chemical resistance compared to materials which are used to the incompletely filled component 151e and / or the lateral Seitenvergussbauteil 152e to form the recess 153e be formed. The recessed incomplete filled component 151e and / or the recessed lateral Seitenvergussbauteil 152e may include a thermal concentration buffering operation and / or a load buffering operation for the lower semiconductor chip 130 carry out.

Referring to 28 may be a lower casting component 150f an incomplete filled component 151f which defines a space between the lower connecting components 140 fills and the lower semiconductor chip 130 seals, and a lateral Seitenvergussbauteil 152f have, which on the outer side of the incompletely filled component 151f is placed and the incompletely filled component 151f seals. The incompletely filled components 151f can a space between the lower connecting components 140 fill and can cover the entire lateral surface of the lower semiconductor chip 130 caulk. The incomplete filled component 151f can from the package connector components 260 through the lateral Seitenvergussbauteil 152f be spaced. The lateral Seitenvergussbauteil 152f can on or on the outer side of the incomplete filled component 151f be placed and can cover the entire lateral surface of the incompletely filled component 151f caulk. The lateral Seitenvergussbauteil 152f can also be an area between the incomplete filled component 151f and the package connection components 260 and / or an area between the package connection components 260 caulk.

The topmost surface of the incompletely filled component 151f and / or the uppermost surface of the lateral Vergussbauteils 152e can with respect to the uppermost surface of the lower semiconductor chip 130 stand out and therefore can be a head start 154f be formed. For example, the uppermost surface of the incompletely filled component 151f and / or the uppermost surface of the lateral Vergussbauteils 152 tilt upward with respect to a direction away from the lower semiconductor chip 130 , This projection may be during the removal, which with reference to above 13 is described, are formed. For example, when a material used to form the lower semiconductor chip 130 has low wear resistance and / or low chemical resistance compared to materials used to fill the incompletely filled component 151f and / or the lateral Seitenvergussbauteil 152f to form the lead 154f be formed. The incomplete filled component 151f and / or the lateral Seitenvergussbauteil 152f which is the lead 154f may include a thermal concentration buffering operation and / or a stress buffering operation for the lower semiconductor chip 130 carry out.

29 is a cross-sectional view of a semiconductor package 1a according to some embodiments of the inventive concept. Compared with the embodiment which is in 7 1, the embodiment shown in FIG 29 is shown on a case where the interposer 120 the second pads 124 does not have. As a result, duplicated descriptions between the Embodiments of 7 and 29 be left out now.

Referring to 29 indicates the semiconductor package 1a a lower semiconductor package 100 on which an interposer 120a and an upper semiconductor package 200 , As above with reference to 4 can be described, the interposer 120a the TSVs 122 and can be the second pads 124 do not have. In this case, wiring patterns formed in the wiring pattern layer 126 the interposer 120a are physically included with the TSVs 122 connected and therefore also be electrically connected to it.

30 is a cross-sectional view of a semiconductor package 1b according to some embodiments of the inventive concept. Compared with the embodiment which is in 7 1, the embodiment shown in FIG 30 is shown on an alternative outer Vergussbauteil 170a , As a result, duplicated descriptions between the embodiments of FIGS 37 be left out now.

Referring to 30 indicates the semiconductor package 1b a lower semiconductor package 100 which is an interposer 120 and an upper semiconductor package 200 on. The interposer 120 , the lower semiconductor chip 130 and portions of the package connector components 260 can through the outer Vergussbauteil 170a be sealed and therefore they can be protected from external shocks or influences. The outer casting component 170a can be a lateral side of the interposer 120 caulk. The outer casting component 170a can extend to a space below the interposer 120 it can fill spaces between the interposer connection components 128 , the interposer connection components 128 surrounding and encapsulating.

The outer casting component 170a can be formed by a MUF technique. The outer casting component 170a can touch and extend to the lower potting component 150 and a part of the lateral sides of the package connection components 260 seal. The outer casting component 170a may extend to and may contact the upper surface of the lower base substrate 110 , The outer casting component 170a can from the upper semiconductor package 200 be spaced. The uppermost surface of the lower casting component 150 can coplanar with the top surface of the outer grout 170a be. Alternatively, the uppermost surface of the lower semiconductor chip 130 Coplanar with the top surface of the outer Vergussbauteils 170a be. The uppermost surfaces of the lower casting component 150 , the outer Vergussbauteils 170a and the lower semiconductor chip 130 can all be at a distance of not more than 5 μm from a first plane.

The semiconductor package 1b can continue first and second air gaps 180a and 180b which is between the lower semiconductor package 100 and the upper semiconductor package 200 are placed. In other words, the semiconductor package 1b the first air gap 180a which is located in an inner area between the package connection components 260 is placed, and the second air gap 180b which outside of the package connector components 260 is placed. The first and the second air gap 180a and 180b can form a larger continuous or continuous air gap.

The 31 to 33 FIG. 15 are cross-sectional views illustrating a method of forming the semiconductor package. FIG 1b of the 30 illustrate, according to some embodiments of the inventive concept. In these examples, the operations described with reference to FIGS 9 to 18 are described in advance, and descriptions thereof will be omitted for simplicity.

Referring to 31 becomes the outer casting component 170a formed on or on a structure, as in 18 is illustrated. The outer casting component 170a can be a space between the interposer connection components 128 , the interposer connection components 128 surrounding and encapsulating, filling, and can be the lateral side of the interposer 120 caulk. The outer casting component 170a may also be a lateral side of the lower Vergussbauteils 150 caulk. The outer casting component 170a can be formed by a MUF technique. The uppermost surface of the lower semiconductor chip 130 can coplanar with the top surface of the outer grout 170a , The uppermost surface of the lower semiconductor chip 130 and the uppermost surface of the outer potting member 17a may be at a distance of not more than 5 μm from a first plane.

Referring to 32 is the lower casting component 150 partially removed to the openings 160 , respectively, the first package connector components 270 to uncover, to form. The openings 160 can be formed by lithography etching or using a laser. Each of the openings 160 may extend downwardly to have a uniform width or to have a narrowing or tapering width.

Referring to 33 becomes the upper semiconductor package 200 which is the second Package connection components 280 which are placed to the first package connection components 270 to correspond, provided or intended. The second package connection components 280 are below the upper base substrate 210 of the upper semiconductor package 200 placed. The upper semiconductor package 200 is placed on the lower semiconductor package. Then the second package connection components 280 each in the openings 160 introduced, so that the first package connection components 270 each electrically and / or physically with the second package connection components 280 get connected.

Then the lower semiconductor package 100 electrically with the upper semiconductor package 200 connected. This electrical connection can be achieved by electrically and / or physically connecting the first package connection components 270 with the second package connection components 280 , The first package connection components 270 and the second package connection components 280 can be connected together using the thermal compression process and / or the reflow process. As a result, the formation of the semiconductor package is 1b , what a 30 shown, completed.

34 is a cross-sectional view of a semiconductor package 1c according to some embodiments of the inventive concept. Compared with the embodiment which is in 7 1, the embodiment shown in FIG 34 is shown in a case where an outer Vergussbauteil 170c different from the outer Vergussbauteil 170 is included. As a result, duplicated descriptions between the embodiments of FIGS 7 and 34 be left out now.

Referring to 34 indicates the semiconductor package 1c a lower semiconductor package 100 on which an interposer 120 and an upper semiconductor package 200 , The outer casting component 170c can be a space between the interposer connection components 128 fill in and can the lateral side of the interposer 120 caulk. The lateral side of the lower casting component 150 may be exposed without passing through the outer casting component 170c to be sealed. As a result, a third air gap 180c be bigger than the second air gap 180b in the embodiment described above. The first, the second and the third air gap 180a . 180b and 180c can form a larger continuous air gap.

The 35 and 36 are cross-sectional views of semiconductor packages 1d and 1e according to further embodiments. The embodiments of the 35 and 36 have a plurality of lower semiconductor chips 130 compared with the embodiments of 7 and 30 on. As a result, duplicated descriptions between the embodiments 35 and 36 and the embodiments of 7 and 30 be left out.

Referring to 35 indicates the semiconductor package 1d a plurality of lower semiconductor chips 130d on which on or at the interposer 120 are placed. The semiconductor package 1d has a plurality of upper semiconductor chips 230d which are in the upper semiconductor package 200 included or included. The semiconductor package 1d can the outer Vergussbauteil 170 , which with reference to 7 is described. The lower semiconductor chips 130d may be a logic semiconductor chip, a memory semiconductor chip or a combination of the logic semiconductor chip and the memory semiconductor chip. The upper semiconductor chips 230d may be a logic semiconductor chip, a memory semiconductor chip or a combination of the logic semiconductor chip and the memory semiconductor chip. Alternatively, a single lower semiconductor chip 130 (please refer 7 ) or more than two lower semiconductor chips 130d in place of the two lower semiconductor chips 130d be used. Alternatively or additionally, a single upper semiconductor chip 230 (please refer 7 ) or more than two upper semiconductor chips 230 in place of the upper semiconductor chip 230d be used. Implementing multiple chips as related to 35 may also be implemented in other alternative embodiments described herein.

For example, with reference to FIG 36 , the semiconductor package 1e a plurality of lower semiconductor chips 130e on which on or on the interposer 120 are placed. The semiconductor package 1e has a plurality of upper semiconductor chips 230e which are in the upper semiconductor package 200 are included. The semiconductor package 1e can the outer Vergussbauteil 170a , which with reference to 30 is described. The lower semiconductor chips 130e may be a logic semiconductor chip, a memory semiconductor chip or a combination of the logic semiconductor chip and the memory semiconductor chip. The upper semiconductor chips 230e may be a logic semiconductor chip, a memory semiconductor chip or a combination of the logic semiconductor chip and the memory semiconductor chip. Alternatively, a single lower semiconductor chip 130 (please refer 7 ) or more than two lower semiconductor chips 130e in place of the two lower semiconductor chips 130e be used. Alternatively or additionally, a single upper semiconductor chip 230 (please refer 7 ) or more than two upper semiconductor chips 230e in place of the upper semiconductor chips 230e be used. 37 is a Cross-sectional view of a semiconductor package 2 according to some alternative embodiments. Compared with the embodiment which is in 7 is shown, the embodiment, which in 37 shown is an alternative interposer 120a compared to the interposer 120 of the 7 on. As a result, duplicated descriptions between the embodiments of FIGS 7 and 37 be left out. It can be understood by a person skilled in the art that a combination of the present embodiment of the 37 and any of the features of alternative embodiments described herein are also included.

Referring to 37 can the semiconductor package 2 the interposer 120a exhibit. The interposer 120a can be a passive component or a passive component 129a , an active component 129b or both of them. The passive component 129a For example, it may include a passive electronic device and a resistor, an inductor, a capacitor, or a switch. The active component 129b or the active ingredient 129b may for example comprise an operational amplifier, a diode or a transistor. The passive component 129a and / or the active component 129b can be on, under or inside the interposer 120 be placed.

The 38 to 24 are cross-sectional views of semiconductor packages 3a . 3b . 3c . 3d and 3e according to some alternative embodiments. The embodiments included in the 38 to 42 are different from the embodiment shown in FIG 7 is shown, concerning the package connection components 260a . 260b . 260c and 260e , As a result, duplicated descriptions between the embodiments of FIGS 38 to 42 and the embodiments of 7 be left out. The package connection components 260a . 260b . 260c . 270d and 270e , what a 38 to 42 can be deformed by the thermal compression process and / or a reflow process and within the openings 160 be filled.

Referring to 38 can the semiconductor package 3a Package connection components 260a which the interposer 120 with the upper semiconductor package 200 connect. The package connection components 260a can first package connection components 270a which are electrically connected to the interposer 120 and second package connection components 280a electrically connected to the upper semiconductor package 200 are connected. The first package connection components 270a and the second package connection components 280a can all have spherical shapes. The adherent upper and lower surfaces of the spherical shape may be slightly flattened. The first package connection components 270a and the second package connection components 280a may be connected to each other using a thermal compression process and / or a reflow process, and thus they may be converted into a single-body structure. The first package connection components 270a and the second package connection components 280a can have different sizes. For example, the first package connection components 270a smaller sizes than the second package connector components 280a ,

Referring to 39 can the semiconductor package 3b the package connection components 260b which the interposer 120 with the upper semiconductor package 200 connect. The package connection components 260b can first package connection components 270 which are electrically connected to the interposer 120 and second package connection components 280b electrically connected to the upper semiconductor package 200 are connected. The first package connection components 270b , the second package connection components 280b or both of these may have spherical or hemispherical shapes. For example, the first package connection components 270b have spherical shapes and the second package connection components 280b can have hemispherical shapes. Alternatively, the adhered upper and lower surfaces of the hemispherical and spherical shapes may be slightly flattened. The first package connection components 270b and the second package connection components 280b may be connected to each other using a thermal compression process and / or a reflow process, and accordingly, they may be converted into a one-body structure. The first package connection components 270b and the second package connection components 280b can have different sizes. For example, the first package connection component 270b smaller sizes than the second package connector components 280b to have. Alternatively, the first package connection components 270b larger sizes than the second package connector components.

Referring to 40 can the semiconductor package 3c the package connection components 260c which the interposer 120 with the upper semiconductor package 200 connect. The package connection components 260c Can first Paekage connection components 270c which are electrically connected to the interposer 120 and second package connection components 280c electrically connected to the upper semiconductor package 200 are connected. The first package connection components 270c , the second package connection components 280c or both of these may have cylindrical or polyprismatic shapes. The first package connection components 270c and the second package connection components 280c may be connected to each other using a thermal compression process and / or a reflow process, and thus may be converted into a single-body structure. The first package connection components 270c can be smaller sizes than the second package connector components 280c to have. Alternatively, the first package connection components 270c larger sizes than the second package connector components 280c ,

Referring to 41 can the semiconductor package 3 the package connection components 260d which the interposer 120 with the upper semiconductor package 200 connect. The package connection components 260d can first package connection components 270d which are electrically connected to the interposer 120 connected, second package connection components 280d electrically connected to the upper semiconductor package 200 and third package connection components 290d which is between the first package connection components 270d and the second package connection components 280d are placed. The first package connection components 270d , the second package connection components 280d or both of these may have spherical or hemispherical shapes. The third package connection components 290d may have spherical shapes, hemispherical shapes, cylindrical shapes or polyprismatic shapes. The first package connection components 270d and the second package connection components 280d may be connected to each other using a thermal compression process and / or a reflow process, and thus may be converted into a one-body structure. The first package connection components 270d can be smaller in size than the second package connector components 280d , The third package connection components 290d can be smaller in size than the first package connector components 270d , the second package connection components 280d or both of these. Alternatively, the first, second, and third package connector components 270d . 280d and 290d a size relationship is different than described herein.

Referring to 42 can the semiconductor package 3e the package connection components 260e which the interposer 120 with the upper semiconductor package 200 connect. The package connection components 260e can first package connection components 270e which are electrically connected to the interposer 120 and second package connection components 280e electrically connected to the upper semiconductor package 200 are connected. The first package connection components 270e and the second package connection components 280e can all have spherical shapes. The adherent lower and upper surfaces of the spherical shape may be slightly flattened. The first package connection components 270e and the second package connection components 280e may be connected to each other using a thermal compression process and / or a reflow process, and thus may be converted into a one-body structure. The first package connection components 270e and the second package connection components 280e can have different sizes. For example, the first package connection components 270e larger sizes than the second package connector components 280e ,

The 43 to 46 FIG. 15 are cross-sectional views illustrating a method of forming a semiconductor package. FIG 4 according to some embodiments. In the present embodiment, the operations described with reference to FIGS 9 to 12 are described in advance, and descriptions thereof will be omitted for simplicity.

Referring to 43 becomes the lower casting component 150 , which on or on the lower semiconductor chip 130 is placed, partially removed, after the lower Vergussbauteil 150 , which is the lower semiconductor chip 130 seals, is formed. When removing the upper surface 132 of the lower semiconductor chip 130 be exposed. In addition, the removal may include an operation of thinning the lower semiconductor chip 130 by removing an upper portion of the lower semiconductor chip 130 exhibit. When removing an upper surface 272 of the first package connection component 270 be exposed. The removal can be carried out for example by CMP. Then the operations which are described with reference to the 14 to 16 are described, and descriptions thereof will be omitted for simplicity. As a result, the interposer wafer becomes 10 thinned, the TSVs 122 passing through the interposer wafer 10 pass through, are formed, and the interposer connection components 128 which at the interposer 120 are made to be electrically connected to the TSVs 122 to be connected.

Referring to 44 becomes the interposer wafer 10 into a plurality of interposers 120 subdivided or cube-shaped, with which the lower semiconductor chip 130 electrical connected is. Then, the process described with reference to 18 is described performed. As a result, the interposer 21 on or on the lower base substrate 120 be attached and the lower base substrate 110 and the interposer 120 can through the interposer connection components 128 be electrically connected to each other. The external connection components 116 may be on the lower surface of the lower base substrate 110 be formed. As a result, the lower semiconductor package 100 be formed.

Referring to 45 becomes the upper semiconductor package 200 provided or provided. First conductive protrusions 274 can continue each on top surfaces 272 the first package connection components 270 of the lower semiconductor package 100 be formed. The first conductive protrusions 274 can with regard to the upper surface 132 of the lower semiconductor chip 130 protrude. The first conductive protrusions 274 may comprise a conductive material and may be formed using, for example, solder balls, a plating method or solder paste.

The upper semiconductor package 200 can second conductive protrusions 284 which are placed to the first package connection component 270 correspond to. The second conductive protrusions 284 are below the upper base substrate 210 of the upper semiconductor package 200 placed. The second conductive protrusions 284 can respect the lower pads 214 of the upper semiconductor chip 230 protrude. The second conductive protrusions 284 may comprise a conductive material and may be formed, for example, using solder balls, a plating method or solder paste.

The upper semiconductor package 200 is on the lower semiconductor package 100 placed. Then the lower semiconductor package 100 electrically with the upper semiconductor package 200 connected. For example, the first conductive protrusions 274 each electrically and / or physically with the second conductive protrusions 284 connected. The first conductive protrusions 274 can with the second conductive protrusions 284 can be connected using the thermal compression process and / or the reflow process, and thus package connection components 260 (please refer 46 ) are formed. An air gap 180 (please refer 46 ) can be between the lower semiconductor package 100 and the upper semiconductor package 200 be formed.

Referring to 46 becomes the outer casting component 170 which is the interposer 120 and the lower semiconductor chip 130 seals, formed, and thus is the formation of the semiconductor package 4 completed. The process of forming the outer molding member 170 may be similar to that described with reference to FIGS 22 is described, and a description thereof will be omitted for the sake of simplicity. The formation of the outer casting component 170 and the electrical connection between the lower semiconductor package 100 and the upper semiconductor package 200 may be performed in an order reverse to the order described above.

The 47 to 53 FIG. 15 are cross-sectional views illustrating a method of forming a semiconductor package. FIG 5 according to some embodiments. Duplicated descriptions between the embodiments of the 47 to 53 and the embodiments of 9 to 22 will be left out.

Referring to 47 becomes the interposer wafer 10 containing a plurality of interposers 120 which the TSVs 122 have provided or intended. The lower semiconductor chip 130 is on the interposer wafer 10 appropriate. The lower connecting components 140 can be below the lower semiconductor chip 130 to be placed. The lower semiconductor chip 130 may be electrically connected to the wiring pattern layer 126 the interposer 120 over the lower connecting components 140 get connected. The lower semiconductor chip 130 Can also be electrically powered with the TSVs 122 over the lower connecting components 140 get connected. Then the lower Vergussbauteil 150 , which is the lower semiconductor chip 130 seals, formed.

Referring to 48 becomes the lower casting component 150 , which on or on the lower semiconductor chip 130 is placed, partially removed. When removing the upper surface 132 of the lower semiconductor chip 130 be exposed. In addition, the removal may include one operation of thinning the semiconductor chip 130 by removing an upper portion of the lower semiconductor chip 130 and the lower semiconductor chip 130 can be made thin. Then the operations which are described with reference to the 14 to 16 and descriptions thereof will be omitted for simplicity. As a result, the interposer wafer becomes 10 thinned, the TSVs 122 passing through the interposer wafer 10 pass through are formed and the interposer connection components 128 which at the interposer 120 are made to be electrically connected to the TSVs 122 to be connected.

Referring to 49 becomes the interposer wafer 10 into a plurality of interposers 120 divided or cube-shaped split. Everyone interposer 120 can be one or more semiconductor chips 130 attached and electrically connected (one is in 49 shown). Then, the process described with reference to 18 is described performed. As a result, the interposer 120 on the lower base substrate 110 be attached, and the lower base substrate 110 and the interposer 120 can be electrically connected to each other via the interposer connection components 128 get connected. The external connection components 116 can be on the lower surface of the lower base substrate 110 be formed. As a result, the lower semiconductor package 100 be formed.

Referring to 50 becomes the lower casting component 150 partially removed to openings 160a to form the interposer 120 uncover. The openings 160a can be formed by lithography etching or using a laser. Each of the openings 160a may extend down to have the same width or to have a narrowing width in the downward direction.

Referring to 51 be the openings 160a filled with a conductive material, creating first package connection components 570 be formed. First conductive protrusions 574 can on the first package connection components 570 be formed. The first conductive protrusions 574 can with regard to the upper surface 132 of the lower semiconductor chip 130 protrude. The first conductive protrusions 574 may comprise a conductive material and may be formed using, for example, solder balls, a plating method or solder paste.

Referring to 52 becomes the upper semiconductor package 200 provided or provided. The upper semiconductor package 200 can second conductive protrusions 584 which are placed around the first package connection components 570 correspond to. The second conductive protrusions 584 are below the lower base substrate 210 of the upper semiconductor package 200 placed. The second conductive protrusions 584 can respect the lower pads 214 of the upper semiconductor chip 230 protrude. The second conductive protrusions 584 may comprise a conductive material and may for example be formed using solder balls, a plating method or solder paste.

The upper semiconductor package 200 is on the lower semiconductor package 100 placed. Then the lower semiconductor package 100 electrically with the upper semiconductor package 200 connected. For example, the first conductive protrusions 574 electrically and / or physically with the second conductive protrusions 584 connected. The first conductive protrusions 574 can with the second conductive protrusions 584 can be connected using the thermal compression process and / or the reflow process, and thus package connection components 560 (please refer 53 ) are formed. The air gap 180 (please refer 53 ) can be between the lower semiconductor package 100 and the upper semiconductor package 200 be formed.

Referring to 53 becomes the outer casting component 170 which is the interposer 120 and the lower semiconductor chip 130 seals, formed, and thus is the formation of the semiconductor package 5 completed. The process of forming the outer molding member 170 may be similar to that described with reference to 22 is described, and a description thereof will be omitted for simplicity. The formation of the outer casting component 170 and the electrical connection between the lower semiconductor package 100 and the upper semiconductor package 200 may be executed in an order reverse to the order described above.

The 54 to 57 are cross-sectional views of semiconductor packages 6a . 6b . 6c and 6d according to further embodiments. Duplicate descriptions between the embodiments 54 to 57 and the embodiment of the 7 will be left out.

Referring to 54 can the semiconductor package 6a a base substrate 610 , an interposer 620 and a semiconductor chip 630 exhibit. The semiconductor package 6a can the base substrate 610 have, wherein the interposer 620 on the base substrate 610 is placed and the TSVs 622 has, and wherein the semiconductor chip 630 on or on the interposer 620 is attached and electrically with the interposer 620 connected is. The semiconductor package 6a can continue a Vergussbauteil 670 which is the interposer 620 seals.

The base substrate 610 may have glass, a ceramic or plastic or plastic. The base substrate 610 may be a substrate for semiconductor packages, for example, a printed circuit board, a ceramic substrate, or a ribbon wiring substrate. Upper pads 612 can on the top surface of the base substrate 610 be placed, and lower pads 614 may be on or on the lower surface of the base substrate 610 be placed.

External connection components 616 can on or on the lower pads 614 of the base substrate 610 be placed to electrically and / or physically with the lower pads 114 to be connected. The lower base substrate 610 can be electrically connected to the outside or to the outside via the external connecting members 616 be connected. The external connection components 616 may be, for example, solder balls. Alternatively, the external connection components 616 form a flip-chip interconnect structure having a grid array such as a pin grid array, a ball grid array, or a land grid array. The external connection components 616 can not be included.

The interposer 620 can on the base substrate 610 be placed. The interposer 620 can be a base layer 621 , the TSVs 622 , first pads 623 , second pads 624 , an insulating layer 625 and a wiring pattern layer 626 exhibit. The interposer 620 can the interposer 20 , which with reference to 7 is described correspond.

The first pads 623 may be on or at the bottom surface of the base layer 621 be placed, and the second pads 624 can on the upper surface of the base layer 621 be placed. The TSVs 622 can be part of the base layer 621 penetrate. The TSVs 622 can the first pads 623 each electrically with the second pads 624 connect.

The insulating layer 625 can be on the base layer 621 to be placed. The insulating layer 625 may be the wiring pattern layer 626 exhibit. The wiring pattern layer 626 can be electrically and / or physically with the second pads 624 the interposer 620 be connected. As a result, the wiring pattern layer 626 electrically with the TSVs 622 be connected.

Interposer connecting members 628 can be under the base layer 621 to be placed. The interposer connection components 628 can be electrically and / or physically with the first pads 623 the interposer 620 be connected, and electrically and / or physically with the second pads 612 of the base substrate 610 be connected. As a result, the TSVs 622 electrically with the base substrate 610 via the interposer connection components 628 be connected. The interposer connection components 628 may be, for example, solder balls. Alternatively, the interposer connection components 628 form a flip-chip interconnect structure having a grid array such as a pin grid array, a ball grid array, or a land grid array.

The semiconductor chip 630 can on the interposer 620 to be placed. The semiconductor chip 630 may be a logic semiconductor chip or memory semiconductor chip as described above. Lower connection components 640 can under the semiconductor chip 630 be placed. The semiconductor chip 630 may be electrically connected to the wiring pattern layer 626 the interposer 620 over the lower connecting components 640 be connected. The semiconductor chip 630 can with the TSVs 622 also over the lower connecting components 640 be electrically connected. The lower connecting components 640 For example, solder balls or other types of connection components, such as alternative connection components, may be described elsewhere in this disclosure. For example, the lower connection components 640 Be bonding wires. Alternatively, the lower connecting components 640 form a flip-chip interconnect having a grid array such as a pin grid array, a ball grid array, or a land grid array.

The lower connecting components 640 may be more dense than the interposer connection components 628 , The lower connecting components 640 can have smaller sizes than the interposer connectors 628 , In this case, the wiring patterns 626 serve as a rewiring pattern. Relative arrangements and sizes of the lower connecting components 640 and the interposer connection components 628 should be recognized as exemplary.

The semiconductor chip 630 can through a first Vergussbauteil 650 be poured and accordingly it can be protected from external influences. The first casting component 650 may extend to the lateral side and a top side of the semiconductor chip 630 seal. The first casting component 650 can be a first incomplete filled component 651 which is below the semiconductor chip 630 is placed, ie which spaces between the lower connecting components 640 the lower connecting components 640 surrounding and encapsulating, and a first covering component 652 , which on or on the first incomplete filled component 651 is placed and a lateral surface and a top surface of the semiconductor chip 630 seals. The first casting component 650 can be formed by a MUF technique. The first casting component 650 can be made of an insulating material.

The interposer 620 can through the second Vergussbauteil 670 be sealed and thus protected from external influences. The second casting component 670 can extend to a space under the interposer 620 to fill. The second casting component 670 can spaces between the interposer connection components 628 fill and can the interposer connection components 628 surround and encapsulate. The second casting component 670 may extend to the lateral side of the first Vergussbauteils 650 to touch or contact and / or seal. The semiconductor chip 630 Can with an extra package protection by the second casting component 670 be provided. The second casting component 670 can be formed by a MUF technique. The second casting component 670 can be made of an insulating material. The first casting component 650 and the second Vergussbauteil 670 may have the same material or different materials.

As an alternative to the in 54 In the embodiment shown, the embodiment shown in FIG 55 is shown, first and second Vergussbauteile 650a and 670a ready.

Referring to 55 can the semiconductor package 6b a base substrate 610 , an interposer 620 and a semiconductor chip 630 exhibit. The semiconductor package 6b can the base substrate 610 , the interposer 620 which is on the base substrate 610 is placed and TSVs 622 has, and the semiconductor chip 630 which is on the interposer 620 is attached and electrically with the interposer 620 is connected. The semiconductor package 6b can continue the Vergussbauteil 670a which is the interposer 620 encapsulates and / or seals and may interposer connection components 628 exhibit.

The semiconductor chip 630 can through a first Vergussbauteil 650a therefore it can be protected from external influences and / or the environment. The first casting component 650a may extend to the lateral side of the semiconductor chip 630 to touch or contact and / or seal. The top surface of the semiconductor chip 630 can through the first Vergussbauteil 650a can not be sealed and with respect to the first Vergussbauteils 650a be exposed. The top surface of the semiconductor chip 630 can be coplanar with the top surface of the first casting component 650a be. Alternatively, the uppermost surface of the semiconductor chip 630 and the uppermost surface of the first potting member 650a at a distance of not more than 5 μm from a first plane. The interposer 620 and the interposer connection components may pass through the second encapsulation component 670a As a result, they can be protected against external influences and / or the environment. The second casting component 670a can extend to a space under the interposer 620 it can fill spaces between the interposer connection components 628 to fill. The second casting component 670a may extend to the lateral side of the first Vergussbauteils 650a to touch or contact and / or seal and therefore the semiconductor chip 630 additional protection by the second casting component 670a Experienced. The second casting component 670a can also be formed by a MUF technique. The top surface of the semiconductor chip 630 can through the second Vergussbauteil 670a not be sealed and therefore can with regard to the second Vergussbauteils 670a be exposed. The top surface of the semiconductor chip 630 may coplanar with the top surface of the second grout 670a be. Alternatively, the uppermost surface of the semiconductor chip 630 and the uppermost surface of the second potting member 670a at a distance of not more than 5 μm from a first plane.

The embodiments of the 56 and 57 refer to a case where a plurality of semiconductor chips 630 is included, compared with the embodiments of 54 and 55 , As a result, duplicated descriptions between the embodiments 56 and 57 and the embodiments of 54 and 55 be left out.

Referring to 56 indicates the semiconductor package 6c a plurality of lower semiconductor chips 630a on which on or on the interposer 620 are placed. The semiconductor package 6c has the first and second Vergussbauteile 650 and 670 which are described above with reference to 54 are described. In other words, the semiconductor chips 630a through the first casting component 650 and / or the second Vergussbauteil 670 be sealed. The first casting component 670 may extend to the lateral sides and uppermost sides of the semiconductor chips 630a to touch or touch and / or seal. The semiconductor chips 630a may be a logic semiconductor chip, a memory semiconductor chip or a combination of the logic semiconductor chip and the memory semiconductor chip.

Referring to 57 indicates the semiconductor package 6d the plurality of lower semiconductor chips 630a on which on the interposer 620 are placed. The semiconductor package 6d has the first and second Vergussbauteile 650a and 670a which are described above with reference to 55 are described. In other words, the semiconductor chips 630a through the first casting component 650a and / or the second Vergussbauteil 670 be sealed. The first casting component 670a may extend to the lateral sides of the semiconductor chips 630a seal. The semiconductor chips 630a may be a logic semiconductor chip, a memory semiconductor chip or a combination of the logic semiconductor chip and the memory semiconductor chip. The top surfaces of the semiconductor chips 630a can through the first casting component 650a not be sealed and therefore can with regard to the first Vergussbauteils 650a be exposed. The top surfaces of the semiconductor chips 630a can coplanar with the top surface of the first casting component 650a be. Alternatively, the uppermost surface of the semiconductor chip 630a and the top surface of the first Vergussbauteils 650a at a distance of not more than 5 μm from a first plane. The top surfaces of the semiconductor chip 630a can through the second Vergussbauteil 670a not be sealed and therefore they can with regard to the second Vergussbauteils 670a be exposed. The top surfaces of the semiconductor chips 630a may coplanar with the top surface of the second grout 670a be. Alternatively, the uppermost surface of the semiconductor chips 630a and the uppermost surface of the second potting member 670a at a distance of not more than 5 μm from a first plane. The semiconductor chips 630a may be a logic semiconductor chip, a memory semiconductor chip or a combination of the logic semiconductor chip and the memory semiconductor chip.

The 58 to 62 FIG. 15 are cross-sectional views illustrating a method of forming a semiconductor package. FIG 7 according to some embodiments. Duplicated descriptions between the embodiments of the 58 and the embodiments of 9 to 22 and 47 and 48 will be left out.

When manufacturing the semiconductor package 7 For example, the process steps described above with reference to FIGS 47 and 48 have been completed previously completed. Accordingly, referring to 58 starting with a structure which is in 48 shown is openings 160b in a casting component 150 be formed. The openings 160b may be Vergussdurchkontaktierungen (TMVs), which are through the Vergussbauteil 150 extend. The openings 160b can be formed by photolithographic etching and / or laser cutting. A conductive layer, such as a metal layer, is deposited and planarized around each of the openings 160b with a conductive plug 770 to fill. The upper surfaces of the casting component 150 , the conductive plug 770 and the lower semiconductor chip 130 may be coplanar and / or within 5 μm of a first plane.

Referring to 59 then becomes a redistribution layer 780 on the upper surfaces of the casting 150 , the conductive plug 770 and the lower semiconductor chip 130 educated. The redistribution layer may be formed by depositing an insulating layer 781 , a pattern of the insulating layer 781 (for example, by photolithography) to upper portions of conductive plugs 770 expose by depositing a conductive layer 782 and patterning the conductive layer 782 to pads 782a and a plurality of wiring connections from the conductive plugs to pads 782a provide. The pads 782a may be formed of the same conductive layer as the wiring connections of the redistribution layer 780 , Although only a conductive layer 782 In this embodiment, alternative embodiments contemplate multiple conductive layers forming part of the redistribution layer 780 with respective insulating layers sandwiched between adjacent conductive layers.

Referring to 60 becomes an auxiliary substrate 134 on the upper surface of the redistribution layer 780 through an adhesive layer 136 appropriate. The auxiliary substrate 134 may be the same auxiliary substrate, which in terms of 14 is described.

Referring to 61 can the lower section 130 the interposer 120 be removed in a manner that respects 15 is described (for example by grinding, CMP and / or Smart Cut) and interposer connection components 128 are affixed in a manner that respects 16 is described.

Referring to 62 can the auxiliary substrate 134 and the adhesive layer 136 can be removed and the interposer attached to a lower base substrate 110 be attached, as regards the 17 and 18 is described. An external casting component 170a can, as regards 30 is added. The alternative outer potting components described herein or others may be added in the alternative. Then, electronic devices such as one or more top semiconductor packages 200 , one or more upper semiconductor chips 230a without a completely encapsulating package and / or one or more passive electronic components 730 with the pads 782 the redistribution or redistribution layer are connected. Alternatively or additionally, one or more of the passive electronic components 703 directly with conductive plugs or plugs 770 be connected without the use of a redistribution or rewiring layer 780 , The passive electronic components may include passive electronic devices such as resistors, inductors, and / or capacitors. Each of these electronic devices can work with the pads 782a through bumps 790 be connected. Each of these electronic devices can make electrical connections to the lower semiconductor chip 130 and / or having external package terminals in a similar manner to electrical paths A, C, D and / or E, which are discussed above with respect to 8th are described.

63 is a schematic block diagram of a map 5000 such as a memory card according to an embodiment of the inventive concept.

Referring to 63 can be a controller 5100 and a memory 5200 be arranged to exchange electrical signals with each other. For example, when a command is issued by the controller 5100 is output, the memory 5200 Transfer data. The controller 5100 and / or the memory 5200 may each comprise one or more semiconductor chips as part of a single semiconductor package according to any of the embodiments described herein. For example, the controller 5100 (a) lower semiconductor chip (s) 130 correspond and the memory 5200 can (an) upper semiconductor chip (s) 230 in the above embodiments described herein (shown, for example, in FIG 7 . 29 . 30 . 34 to 42 . 46 and 53 and their alternatives). The memory 5200 may include a memory array (not shown) or a memory array bank (not shown). The map 5000 may be a fixed memory card used in a larger system, or may be a removable memory card, such as a memory stick card, a smart media (SM) card, a secure digital (SD) card, a mini SD card, or a Multimedia Card (MMC).

64 is a schematic block diagram of a system 6000 according to an embodiment of the inventive concept.

Referring to 64 can the system 6000 a controller 6100 , an input / output (I / O) device 6200 , a store 6300 and an interface 6400 exhibit. The system 600 may be a mobile device that transmits or receives information. The mobile system may be a PDA, a portable computer, a web tablet, a wireless telephone, a mobile phone, a digital music player, or a memory card. The controller 6100 can run a program and a controller for the system 6000 provide. The controller 6100 may be a microprocessor, a digital signal processor, a microcontroller, or a device similar to these devices. The input / output device 6200 can be used to view the data of the system 6000 to enter or output. The system 6000 can with an external device, such as a personal computer or a network to use the input / output device 6200 be connected and therefore can exchange data with the external device. The input / output device 6200 can be a keypad, keyboard or display. The memory 6300 can be a code and / or data to operate the controller 6100 store and / or data by the controller 6100 be processed or were, save. The controller 6100 and the memory 6300 may each comprise one or more semiconductor chips as part of a single semiconductor package according to any of the embodiments disclosed herein. For example, the controller 6100 (a) lower semiconductor chip (s) 130 correspond and the memory 6300 can (an) upper semiconductor chip (s) 230 in the above embodiments described herein (shown, for example, in FIG 7 . 29 . 30 . 34 to 42 . 46 and 53 and their alternatives). The interface or the interface 6400 can be a data transfer path between the system 6000 and another external device. The controller 6100 , the input / output device 6200 , the memory 6300 and the interface or the interface 6400 can communicate with each other via a bus 6500 communicate. For example, the system can 6000 in a mobile phone, an MP3 player, a navigation system, a portable multimedia player (PMP), a solid state disk (SSD), or household appliances.

65 FIG. 12 is a perspective view of an electronic device to which semiconductor devices fabricated according to embodiments disclosed herein are applicable.

65 illustrates a mobile phone 7000 to which the electronic system 6000 of the 64 can be applied. The electronic system 6000 of the 64 Can be used in portable notebooks, MP3 players, navigation systems, SSDs, cars or household appliances.

While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• KR 10-2011-014145 [0001]

Claims (49)

Semiconductor package ( 1 ) comprising: a lower semiconductor package ( 100 ) comprising: an interposer formed of a semiconductor material or a glass material ( 20 . 20 . 120 . 120a ), which has a lower surface, an upper surface, lower connections ( 123 ) on a lower surface, upper connections ( 124 ) on an upper surface and substrate vias ( 42 . 122 ) which extends through at least one substrate of the interposer ( 20 . 120 . 120a ) and electrically each one of the lower terminals ( 123 ) of the interposer ( 20 . 120 . 120a ) with a corresponding one of the upper ( 124 ) Interposer connections ( 20 . 120 . 120a ) connect; a lower semiconductor chip ( 130 ), which at the Interposer ( 20 . 120 . 120a ), wherein the lower semiconductor chip ( 130 ) Has pads which are electrically connected to at least some of the upper terminals ( 124 ) of the interposer ( 20 . 120 . 120a ) are connected; and a potting material, which sides of the lower semiconductor chip ( 130 ) surrounds; one on the lower semiconductor package ( 100 ) stacked top semiconductor device ( 200 ), comprising: a lower surface; Connections ( 270 . 280 ) on the lower surface; and an integrated circuit electrically connected to at least some of the terminals ( 270 . 280 ) is connected on the lower surface; and conductive bumps located on the top surface of the interposer ( 20 . 120 . 120a ) and to the lower surface of the upper semiconductor device ( 200 ) and electrically each one of the upper terminals ( 124 ) on the upper surface of the interposer ( 20 . 120 . 120a ) with a corresponding one of the terminals on the lower surface of the upper semiconductor device ( 200 ), each of the conductive bumps having a lower portion and an upper portion. Semiconductor package ( 1 ) according to claim 1, further comprising: a passive device ( 129a ) having terminal pads connected to the conductive bumps. Semiconductor package ( 1 ) according to claim 2, wherein the passive device ( 129a ) has at least one capacitor, a resistor or an inductance. Semiconductor package ( 1 ) according to claim 1, further comprising: a dielectric layer on the lower semiconductor chip ( 130 ); and a wiring pattern on the dielectric layer, wherein the upper semiconductor device (FIG. 200 ) comprises an upper semiconductor package comprising: an upper package substrate ( 210 ) having a lower surface, an upper surface, lower terminals ( 214 ) on the lower surface, upper terminals ( 212 ) on the upper surface in electrical communication with the lower terminals ( 214 ); an upper semiconductor chip ( 230 ), which has the integrated circuit attached to the upper package substrate ( 210 ), wherein the upper semiconductor chip ( 230 ) Has chip pads electrically connected to at least some of the lower terminals ( 214 ) of the upper package substrate ( 210 ) are connected via the upper terminals; and wherein the upper portion of each of the conductive bumps is connected to a corresponding lower port ( 214 ) on the lower surface of the upper package substrate ( 210 ), wherein the upper portion of each of the conductive bumps is connected to a corresponding lower portion of the conductive bumps. Semiconductor package ( 1 ) according to claim 4, wherein a size of the upper portion of the conductive bump is greater than a size of the lower portion of the conductive bump. Semiconductor package ( 1 ) according to claim 1, wherein the interposer ( 20 . 120 . 120a ) has a wiring pattern which has upper terminals of the substrate vias ( 42 . 122 ) of the interposer ( 20 . 120 . 120a ) with corresponding chip pads of the lower semiconductor chip ( 130 ) connects. Semiconductor package ( 1 ) according to claim 1, further comprising: a printed circuit board having an upper surface and a lower surface; and package terminals attached to the bottom surface of the printed circuit board, wherein the interposer ( 20 . 120 . 120a ) is attached to the printed circuit board on the upper surface of the printed circuit board. Semiconductor package ( 1 ) according to claim 7, wherein the printed circuit board has a rewiring layer, comprising a first conductor which is electrically connected to a chip pad of the lower semiconductor chip ( 130 ) through a first substrate via ( 42 . 122 ) of the interposer ( 20 . 120 . 120a ), and which with a chip pad of the upper semiconductor chip ( 230 ) is connected by a second substrate via ( 42 . 122 ) of the interposer ( 20 . 120 . 120a ), but not connected with any conductive terminal on the lower surface of the printed circuit board, and also not connected to any of the package terminals on the lower surface of the printed circuit board. A semiconductor device according to claim 8, wherein the chip pad of the lower semiconductor chip ( 130 ) is a data pad which is connected to a data buffer of the lower semiconductor chip ( 130 ), and the chip pad of the upper semiconductor chip ( 230 ) is a data pad which is connected to a data buffer of the upper semiconductor chip ( 230 ) connected is. Semiconductor package ( 1 ) according to claim 8, wherein the chip pad of the lower semiconductor chip ( 130 ) is an address pad which is connected to an address buffer of the lower semiconductor chip ( 130 ), and the chip pad of the upper semiconductor chip ( 230 ) is an address pad which is connected to an address buffer of the upper semiconductor chip ( 230 ) connected is. Semiconductor package ( 1 ) according to claim 8, wherein the chip pad of the lower semiconductor chip ( 130 ) is a clock pad which is connected to a clock buffer of the lower semiconductor chip ( 130 ) and the chip pad of the upper semiconductor chip ( 230 ) is a clock pad which is connected to a clock buffer of the upper semiconductor chip ( 230 ) connected is. Semiconductor package ( 1 ) according to claim 7, further comprising a package potting material ( 250 ) extending at least from the top surface of the package substrate ( 110 ) of the printed circuit board to the lower surface of the upper package substrate ( 210 ). Semiconductor package ( 1 ) according to claim 7, further comprising a homogeneous potting on the outer surface of the lower package, at least from a lower surface of the upper package to the upper surface of the package substrate ( 110 ) of the printed circuit board. Semiconductor package ( 1 ) according to claim 7, wherein the substrate ( 110 ) of the printed circuit board is 220 μm or less. Semiconductor package ( 1 ) according to claim 7, wherein the substrate ( 110 ) of the printed circuit board has two redistribution layers or less. Semiconductor package ( 1 ) according to claim 1, wherein the lower semiconductor chip ( 130 ) on the interposer ( 20 . 120 . 120a ) is mounted with a face-down configuration. Semiconductor package ( 1 ) according to claim 16, wherein the conductive bumps are first conductive bumps, wherein the lower semiconductor chip ( 130 ) Chip pads on an active surface of the semiconductor chip ( 130 ), which the Interposer ( 20 . 120 . 120a ), and the semiconductor package ( 1 ) further comprises: second conductive bumps extending from the active surface of the semiconductor chip ( 130 ) to the interposer ( 20 . 120 . 120a ), which cover the chip pads of the lower semiconductor chip ( 130 ) each with a corresponding one of the upper terminals of the interposer ( 20 . 120 . 120a ), wherein the second conductive bumps have a height of 20 μm or less. Semiconductor package ( 1 ) according to claim 17, wherein the second conductive bumps the chip pads of the lower semiconductor chip ( 130 ) directly with a corresponding one of the upper connections of the interposer ( 20 . 120 . 120a ) connect. Semiconductor package ( 1 ) according to claim 1, wherein the lower chip ( 130 ) a first surface which the upper surface of the interposer ( 20 . 120 . 120a ), and has a second surface, opposite the first surface, and the package ( 1 ) further comprises: an air gap ( 180 ) between the second surface of the lower semiconductor chip ( 130 ) and the lower surface of the upper package substrate. Semiconductor package ( 1 ) according to claim 19, wherein the air gap ( 180 ) has a thickness of 50 μm or less. Semiconductor package ( 1 ) according to claim 1, wherein the conductive bumps extend from the upper surface of the interposer ( 20 . 120 . 120a ) to the lower terminals on the lower surface of the upper package substrate. Semiconductor package ( 1 ) according to claim 21, wherein the conductive bumps have a height of 120 μm or less. Semiconductor package ( 1 ) according to claim 1, wherein the upper surface of the interposer ( 20 . 120 . 120a ) has a root mean square surface roughness of less than 1.3 nm. Semiconductor package ( 1 ) according to claim 1, wherein the interposer ( 20 . 120 . 120a ) a redistribution layer ( 780 ) having. Semiconductor package ( 1 ) according to claim 24, wherein the redistribution layer ( 780 ) Has a redistribution pattern which has a first conductor which is electrically connected from the lower semiconductor chip ( 130 ) is isolated. Semiconductor package ( 1 ) according to claim 24, wherein the redistribution layer ( 780 ) has a rewiring pattern having a pitch between at least some of adjacent conductors of the rewiring pattern of 10 μm or less. Semiconductor package ( 1 ) according to claim 24, wherein the redistribution layer ( 780 ) has a rewiring pattern having a pitch between at least some of adjacent conductors of the rewiring pattern of 5 μm or less. Semiconductor package ( 1 ) according to claim 1, wherein the thermal expansion coefficient (CTE) of the interposer ( 20 . 120 . 120a ) is not greater than approximately twice the thermal expansion coefficient (CTE) of the lower semiconductor chip ( 130 ). Semiconductor package ( 1 ) according to claim 1, wherein the thermal expansion coefficient (CTE) of the interposer ( 20 . 120 . 120a ) is not greater than about 1.3 times the thermal expansion coefficient (CTE) of the lower semiconductor chip ( 130 ). Semiconductor package ( 1 ) according to claim 1, wherein the thermal expansion coefficient (CTE) of the interposer ( 20 . 120 . 120a ) substantially equal to the thermal expansion coefficient (CTE) of the lower semiconductor chip ( 130 ). Semiconductor package ( 1 ) according to claim 1, wherein the interposer consists of ( 20 . 120 . 120a ) Silicon, germanium, silicon germanium or gallium arsenide. Semiconductor package ( 1 ) according to claim 1, wherein a first conductive node comprises a first lower terminal of the interposer ( 20 . 120 . 120a ), a first substrate via ( 42 . 122 ) of the interposer ( 20 . 120 . 120a ), a first top port of the interposer ( 20 . 120 . 120a ), a first conductive bump which is placed on the interposer ( 20 . 120 . 120a ), a first lower terminal ( 214 ) on the lower surface of the upper package substrate ( 210 ) and a first upper port ( 212 ) of the upper surface of the upper package substrate ( 210 ) and a Vdd chip pad of the upper semiconductor chip ( 230 ), which is connected to a Vdd power supply for an internal power supply circuit of the upper semiconductor chip ( 230 ); wherein a second conductive node has a second lower terminal of the interposer ( 20 . 120 . 120a ), a second substrate via ( 42 . 122 ) of the interposer ( 20 . 120 . 120a ), a second upper port of the interposer ( 20 . 120 . 120a ), a second conductive bump which is placed on the interposer ( 20 . 120 . 120a ), a second lower terminal ( 214 ) on the lower surface of the upper package substrate ( 210 ), a second upper port ( 212 ) of the upper surface of the upper package substrate ( 210 ), a Vss chip pad of the upper semiconductor chip ( 230 ), which is connected to a Vss power supply for the internal power supply circuit of the upper semiconductor chip ( 230 ), and a Vss chip pad of the lower semiconductor chip ( 130 ), which is connected to a Vss power supply for an internal power supply circuit of the lower semiconductor chip ( 130 ), wherein a third conductive node has a third lower terminal of the interposer ( 20 . 120 . 120a ), a third substrate via ( 42 . 122 ) of the interposer ( 20 . 120 . 120a ) and a Vdd-chip pad of the lower semiconductor chip ( 130 ), which is connected to a Vdd power supply for an internal power supply circuit of the lower semiconductor chip ( 130 ), and wherein the first conductive node, the second conductive node and the third conductive node are each different from each other, wherein the first conductive node does not provide a Vdd power supply to the lower semiconductor chip ( 130 ), and wherein the third conductive node does not supply a Vdd power supply to the upper semiconductor chip ( 230 ). Semiconductor package ( 1 ) according to claim 1, wherein a solid material of the interposer ( 20 . 120 . 120a ) is made of a rigid material having a modulus of elasticity of 100 GPa or more. Semiconductor package ( 1 ), comprising: an upper semiconductor package ( 200 ); and a lower semiconductor package ( 100 ), wherein the upper semiconductor package ( 200 ) on the lower semiconductor package ( 100 ) is stacked, the lower package ( 100 ) Comprises: an interposer ( 20 . 120 . 120a ) formed of a semiconductor material or a glass material having a lower surface, an upper surface, lower terminals ( 123 ) on a lower surface, upper connections ( 124 ) at an upper surface and substrate vias ( 42 . 122 ) which extends through at least one substrate of the interposer ( 20 . 120 . 120a ) and electrically each one of the lower terminals ( 123 ) of the interposer ( 20 . 120 . 120a ) with one of the upper connections ( 124 ) of the interposer ( 20 . 120 . 120a ) connect; a lower semiconductor chip ( 130 ), which at the Interposer ( 20 . 120 . 120a ), wherein the lower semiconductor chip ( 130 ) Has chip pads electrically connected to at least some of the upper terminals ( 124 ) of the interposer ( 20 . 120 . 120a ) are connected; conductive bumps attached to the top surface of the interposer ( 20 . 120 . 120a ) adjacent to the lower semiconductor chip ( 130 ) and electrically connected to at least some of the upper terminals ( 124 ) of the interposer ( 20 . 120 . 120a ) are connected; a potting material ( 150 ), which sides of the lower semiconductor chip ( 130 ), wherein the upper semiconductor package ( 200 ) Comprises: an upper package substrate ( 210 ), which has a lower surface, an upper surface, lower connections ( 214 ) on the lower surface, upper connections ( 212 ) on the upper surface in electrical communication with the lower terminals ( 214 ), the lower connections ( 214 ) of the upper base substrate are electrically connected to the conductive bumps; and an upper semiconductor chip ( 230 ) attached to the upper package substrate ( 210 ), wherein the upper semiconductor chip ( 230 ) Has chip pads electrically connected to at least some of the upper terminals ( 214 ) of the upper package substrate ( 210 ) are connected. Package according to claim 34, wherein the upper surface of the potting material ( 150 ) coplanar with the upper surface of the lower semiconductor chip ( 130 ). Package according to claim 34, wherein the entire uppermost surface of the potting material ( 150 ) and the entire uppermost surface of the lower chip ( 130 ) are within 5 μm of a first plane. A package according to claim 34, wherein an upper surface of the potting material ( 150 ) flush with an upper surface of the lower semiconductor chip ( 130 ). The package of claim 34, wherein at least some of the conductive bumps are evenly spaced at a pitch of 0.4 mm or less. The package of claim 34, wherein the bottom chip ( 130 ) a first surface which the upper surface of the interposer ( 20 . 120 . 120a ), and has a second surface opposite the first surface, and wherein a distance from the second surface of the lower chip (FIG. 130 ) to the upper surface of the interposer ( 20 . 120 . 120a ) Is 70 μm or less. Semiconductor package ( 1 ), comprising: an upper semiconductor package ( 200 ); and a lower semiconductor package ( 100 ), wherein the upper semiconductor package ( 200 ) on the lower semiconductor package ( 100 ), the lower package comprising: an interposer ( 20 . 120 . 120a ), which has a lower surface, an upper surface, lower connections ( 123 ) on a lower surface, upper connections ( 124 ) at an upper surface and substrate vias ( 42 . 122 ) which extends through at least one substrate of the interposer ( 20 . 120 . 120a ) and electrically respective ones of the lower terminals ( 123 ) of the interposer ( 20 . 120 . 120a ) with one of the upper connections ( 124 ) of the interposer ( 20 . 120 . 120a ) connect; a lower semiconductor chip ( 130 ), which at the Interposer ( 20 . 120 . 120a ), wherein the lower semiconductor chip ( 130 ) Has chip pads electrically connected to at least some of the top terminals of the interposer ( 20 . 120 . 120a ), the lower chip having a thickness of 50 μm or less; conductive bumps attached to the top surface of the interposer ( 20 . 120 . 120a ) adjacent to the lower semiconductor chip ( 130 ) and are electrically connected to at least some of the top terminals of the interposer ( 20 . 120 . 120a ) are connected; wherein the upper semiconductor package ( 200 ) Comprises: an upper package substrate ( 210 ), which has a lower surface, an upper surface, lower connections ( 214 ) on the lower surface, upper connections ( 212 ) on the upper surface in electrical communication with the lower terminals ( 214 ), the lower connections ( 214 ) of the upper base substrate ( 210 ) are electrically connected to the conductive bumps; and an upper semiconductor chip ( 230 ) attached to the upper package substrate ( 210 ), wherein the upper semiconductor chip ( 230 ) Has chip pads electrically connected to at least some of the upper terminals ( 214 ) of the upper package substrate ( 210 ) are connected. A method of manufacturing comprising: attaching a plurality of first semiconductor chips to an upper surface of a wafer ( 10 ) in a face-down configuration, including connecting chip pads of the first chips to first conductive vias ( 42 . 122 ), which in the wafer ( 10 ) are formed; Forming conductive bumps on the wafer ( 10 ) to provide an electrical connection between the conductive bumps and second conductive vias ( 42 . 122 ), which in the wafer ( 10 ) are provided; Forming a potting material ( 150 ) over the plurality of first chips and conductive bumps; Etching the backsides of the first semiconductor chips ( 130 ) while the chips ( 130 ) on the wafer ( 10 ) remain attached; and stacking a respective second semiconductor chip ( 230 ) on each of the first semiconductor chips ( 130 ) comprising providing an electrical connection of pads of the respective second semiconductor chips ( 230 ) with appropriate conductive bumps. The method of claim 41, wherein the step of stacking a respective second semiconductor chip ( 230 ) Stacking a respective package including a corresponding second semiconductor chip ( 230 ) on each of the first semiconductor chips ( 130 ) having. The method of claim 42, wherein the step of stacking comprises bonding bumps to a bottom surface of the respective package with the respective conductive bumps. The method of claim 43, wherein the step of stacking comprises forming an air gap ( 180 ) between the upper surface of each first semiconductor chip ( 130 ) and the corresponding package which is placed on the first semiconductor chip ( 130 ) is stacked. The method of claim 41, wherein the etching step comprises chemical mechanical polishing. The method of claim 41, wherein the etching step comprises potting material ( 150 ) removed via the first semiconductor chip ( 130 ) is formed; The method of claim 41, further comprising: separating the wafers ( 10 ) to stack stacks of first and second semiconductor chips ( 130 . 230 ) to separate from each other. The method of claim 41, further comprising: the plurality of first semiconductor chips ( 130 ) on the wafer ( 10 ), a thinning of the wafer ( 10 by removing material from a bottom surface of the wafer ( 10 ), opposite the first surface. The method of claim 48, wherein the thinning step comprises bottom portions of the first and second conductive vias ( 42 . 122 ), which in the wafer ( 10 ) are exposed.

Images