DE102017122831B4 - Housing structures and training procedures - Google Patents

Abstract

A method comprising: attaching a first die (68) to a first side of a first component (96) using first electrical connectors (91); attaching a first side of a second die (88) to the first side of the first component (96) using second electrical connectors (78); attaching a dummy die (106) to the first side of the first component (96) in one scribe line area (94) of the first component (96), adhering a cap structure (110) to a second side of the second die (88) but not to the first die; and singulating the first component (96) and the dummy die (106) to form a package structure (200).

Description

BACKGROUND

Since the development of the integrated circuit (IC), the semiconductor industry has experienced sustained, rapid growth due to continued improvement in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has resulted in large part from repeated reductions in minimum feature size, allowing more components to be integrated into a given area.

This integration improvement is essentially two-dimensional (2D) in nature since the area occupied by the integrated components is essentially on the surface of the semiconductor wafer. The increased density and corresponding decrease in integrated circuit area has generally overtaken the ability to bond integrated circuit chips directly to a substrate. Interposers have been used to redistribute ball pads from areas of the chip to larger areas of the interposer. Furthermore, interposers have made possible a three-dimensional (3D) package containing multiple chips. Other cases have also been developed to integrate 3D aspects.

the U.S. 2011/0 026 232 A1 describes a method for manufacturing a semiconductor device in which a plurality of dice are arranged on a substrate. Dummy dies are in the area of scribe lines. Several chip planes are arranged on top of each other and the structure thus formed is covered with a wafer. the U.S. 2007/0126085 A1 shows a semiconductor structure in which a chip covers several adjacent stacks of chips.

character list

• Die 1 bis 15 sind Querschnittsansichten und Draufsichten in einem beispielhaften Verfahren zum Ausbilden einer Gehäusestruktur gemäß einigen Ausführungsformen.
• 16 zeigt eine Querschnittsansicht einer Gehäusestruktur gemäß einigen Ausführungsformen.
• 17 zeigt eine Querschnittsansicht einer Gehäusestruktur gemäß einigen Ausführungsformen.
• 18 zeigt eine Querschnittsansicht einer Gehäusestruktur gemäß einigen Ausführungsformen.
• Die 19 und 20 zeigen Querschnittsansichten einer Gehäusestruktur gemäß einigen Ausführungsformen.
• 21 zeigt eine Querschnittsansicht einer Gehäusestruktur gemäß einigen Ausführungsformen.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.

• the 1 until 15 12 are cross-sectional views and top views in an example method of forming a packaging structure, according to some embodiments.
• 16 12 shows a cross-sectional view of a package structure according to some embodiments.
• 17 12 shows a cross-sectional view of a package structure according to some embodiments.
• 18 12 shows a cross-sectional view of a package structure according to some embodiments.
• the 19 and 20 12 show cross-sectional views of a package structure according to some embodiments.
• 21 12 shows a cross-sectional view of a package structure according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples to implement various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, forming a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements between the first element and the second element can be formed, so that the first and the second element need not be in direct contact. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself compel a relationship between the various described embodiments and/or configurations.

Further, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein for ease of description to indicate the relationship of one element or facility to other elements( en) or device(s) as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in a different orientation) and the spatially relative terms used herein also interpreted accordingly.

Embodiments described herein may be described in a specific context, namely a package structure having dummy die structures adjacent to the active dies to reduce warpage of the package structure. This reduction in package structure deflection allows for a more reliable package structure by reducing the likelihood of cold solder joints between the active dies and the interposer. In some embodiments, the dummy dies are in the scribe line areas and cap structures cover some of the active dies while other active dies are not covered by cap structures. The dummy dies may allow for better control of the encapsulant content and thus reduce stress and deflection due to the coefficient of thermal expansion (CTE) mismatch. In some embodiments, the encapsulant may be omitted if the dummy dies in the scribe line areas and/or the cover structures provide sufficient support and protection for the package structure. In some embodiments, the active dies are stacks of one or more dies (logic die-stack and/or memory die-stack), where the top die of the die-stack is thicker than the other dies of the die-stack. In these embodiments, the dummy dies in the scribe line areas and the encapsulant can be omitted since thicker top dies of the die stack provide sufficient support and protection for the package structure.

Embodiments are described in relation to a specific context, namely a stacked die-interposer substrate package using chip-on-wafer-on-substrate (CoWoS) processing. However, other embodiments can also be applied to other housings, such as e.g. B. stacked die-die substrate package, and other processing. Embodiments described herein are examples to enable making or using the subject matter of this disclosure, and one skilled in the art will readily recognize modifications that can be made while remaining within the contemplated scope of the different embodiments. The same reference numbers and letters in the following figures refer to the same components. Although method embodiments can be described as being performed in a particular order, other method embodiments can be performed in any logical order.

1 12 generally depicts the formation of one or more dies 68. A substrate 60 includes one or more dies 68 during processing. The substrate 60, in one embodiment, is a wafer and may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a semiconductor multi-layer substrate or the like. The semiconductor material of the substrate 60 may be silicon, germanium, a compound semiconductor comprising silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates can also be used. The substrate 60 can be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, and the like can be formed in and/or on an active surface 62 of substrate 60 .

An interconnect structure 64 comprising one or more dielectric layers and associated metallization structures is formed on active surface 62 . The metallization structure(s) in the dielectric layer(s) can conduct electrical signals between the devices, e.g. by using vias and/or conductive traces, and may also include various electrical devices such as capacitors, resistors, inductors or the like. The various devices and metallization structures can be interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. Additionally, die connectors 66, such as conductive pillars (e.g., comprising a metal such as copper), are formed in and/or on interconnect structure 64 to provide external electrical connection to the circuits and devices. In some embodiments, die connectors 66 protrude from interconnect structure 64 to form a pillar structure to be used when bonding dies 68 to other structures. One of ordinary skill in the art will recognize that the above examples are for illustrative purposes. Other circuits can be used as needed for a given application.

In particular, an intermetallization dielectric (IMD) layer may be formed in interconnect structure 64 . The IMD layer can be made, for example, from a low-k dielectric material such as phosphorus silicate glass (PSG), borophosphorus silicate glass (BPSG), fluorosilicate glass (FSG), SiO _x C _y , spin-on glass, spin-on poly mers, silicon-carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable method known in the art, such as spin coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), high density plasma chemical vapor deposition (HDP) CVD) or the like can be formed. A metallization pattern may be formed in the IMD layer, for example using photolithographic techniques to deposit and pattern a photoresist material on the IMD layer to expose portions of the IMD layer that are to become the metallization pattern. An etch process, such as an anisotropic dry etch process, may be used to create depressions and/or openings in the IMD layer that correspond to the exposed portions of the IMD layer. The depressions and/or openings can be lined with a diffusion barrier and filled with a conductive material. The diffusion barrier layer may comprise one or more atomic layer deposition (ALD) deposited layers of TaN, Ta, TiN, Ti, CoW or the like and the conductive material may comprise copper, aluminum, tungsten, silver and combinations thereof or the like deposited by CVD, physical vapor deposition (PVD) or the like can be deposited. Excess diffusion barrier layer material and/or conductive material on the IMD layer may be removed, such as by using chemical mechanical polishing (CMP).

In 2 the substrate 60, which comprises the connection structure 64, is singulated into individual dies 68. Typically, the dies 68 include the same circuitry, such as devices and metallization structures, although the dies may include different circuitry. The separation can be done by sawing, cutting or the like.

The dies 68 may be logic dies (e.g., a main processing unit, a graphics processing unit, a system-on-chip, a microcontroller, etc.), memory dies (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), power management dies (e.g., a power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, microsystems (MEMS) dies, signal processing dies (e.g., a digital signal processing (DSP) die), front-end dies (e.g., an analog front-end (AFE) die), the like, or a combination from that. Additionally, in some embodiments, the dies 68 may be a different size (e.g., different height and/or area), and in other embodiments, the dies 68 may be the same size (e.g., the same height and/or area). .

3 shows the formation of a first side of one or more components 96. As in FIG 14 As shown, the one or more components 96 can be formed from the substrate 70 . The components 96 can be an interposer or other die. The substrate 70 can be a wafer. The substrate 70 may include a bulk semiconductor substrate, an SOI substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the substrate 70 may be silicon, germanium, a compound semiconductor comprising silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP and/or GalnAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates can also be used. The substrate 70 can be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, and the like may be formed in and/or on a first surface 72, which may also be referred to as the active surface of substrate 70. In embodiments where the components 96 are interposers, the components 96 generally do not include active devices, although the interposer may include passive devices formed in and/or on a first surface 72 and/or in a redistribution structure 76 .

Vias (TVs) 74 are formed to extend from the first surface 72 of the substrate 70 to the substrate 70 . TVs 74 are also sometimes referred to as substrate vias or silicon vias when substrate 70 is a silicon substrate. The TVs 74 may be formed by forming recesses in the substrate 70, such as by etching, milling, laser techniques, a combination thereof, and/or the like. A thin dielectric material can be formed in the recesses, such as by using an oxidation technique. A thin barrier layer may be conformally deposited over the front surface of the substrate 70 and in the openings, such as by CVD, ALD, PVD, thermal oxidation, a combination thereof, and/or the like. The barrier layer may comprise a nitride or an oxynitride such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, and/or the like. A conductive material can be deposited over the thin barrier layer and in the openings. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, a Combination thereof and / or the like are formed. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, and/or the like. Excess portions of the conductive material and the barrier layer are removed from the front side of the substrate 70 by CMP, for example. Thus, the TVs 74 may include a conductive material and a thin barrier layer between the conductive material and the substrate 70 .

A redistribution structure 76 is formed over the first surface 72 of the substrate 70 and is used to electrically connect the integrated circuit devices, if present, and/or the TVs 74 to each other and/or to external devices. The redistribution structure 76 may include one or more dielectric layer(s) and associated metallization structure(s) in the dielectric layer(s). The metallization structures may include vias and/or traces to connect any devices and/or TVs 74 to each other and/or to an external device. The metallization structures are sometimes referred to as redistribution lines (RDL). The dielectric layers can be silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-k dielectric material such as PSG, BPSG, _{FSG, SiOxCy ,} spin-on glass, spin-on polymers, silicon-carbon material, compounds thereof, composites thereof, combinations thereof, or the like. The dielectric layers can be deposited by any suitable method known in the art, such as spin coating, CVD, PECVD, HDP-CVD, or the like. A metallization pattern may be formed in the dielectric layer, for example using photolithographic techniques to deposit and pattern a photoresist material on the dielectric layer to expose portions of the dielectric layer that are to become the metallization pattern. An etch process, such as an anisotropic dry etch process, may be used to create depressions and/or openings in the dielectric layer that correspond to the exposed portions of the dielectric layer. The depressions and/or openings can be lined with a diffusion barrier and filled with a conductive material. The diffusion barrier layer may comprise one or more layers of TaN, Ta, TiN, Ti, CoW or the like deposited by ALD or the like and the conductive material may comprise copper, aluminum, tungsten, silver and combinations thereof or the like deposited by CVD, PVD or the like can be deposited. Any excess portions of the diffusion barrier layer and/or conductive material on the dielectric layer can be removed, such as by using a CMP.

Electrical connectors 77/78 are formed on the top surface of the redistribution structure 76 on conductive pads. In some embodiments, the conductive pads include under-bump metallurgies (UBMs). In the embodiment shown, the pads are formed in openings of the dielectric layers of the redistribution structure 76 . In another embodiment, the pads (UBMs) may extend through an opening of a dielectric layer of the redistribution structure 76 and also extend over the top surface of the redistribution structure 76 . As an example of forming the pads, a seed layer (not shown) is formed at least in the opening in the dielectric layer of the redistribution structure 76 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The structure of the photoresist corresponds to the pads. The pattern forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. Then the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by any suitable ashing or stripping method, for example using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, for example, by using an appropriate etching technique, such as wet or dry etching. The remaining portions of the seed layer and conductive material form the pads. In the embodiment where the pads are formed differently, more photoresist and patterning steps can be used.

In some embodiments, the electrical connectors 77/78 include a metal post 77 with a metal cap layer 78 that includes a solder cap 78 over the metal pillar 77. The electrical connectors 77/78 including the pillar 77 and the cap layer 78 are sometimes referred to as micro bumps 77/78. In some embodiments, the metal pillars 77 comprise a conductive material such as copper, aluminum, gold, nickel, palladium, the like, or a combination thereof, and may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars 77 may be solder-free and have substantially vertical sidewalls. In some embodiments, metal cap layer 78 is formed on top of metal pillar 77 . The metal cap layer 78 may include nickel, tin, tin-lead, gold, copper, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

In another embodiment, the electrical connectors 77/78 do not include the metal pillars and are solder balls and/or bumps such as solder. B. bumps formed by flip-chip (C4), Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) techniques or the like. In this embodiment, the electrical connectors 77/78 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In this embodiment, the electrical connectors 77/78 are formed by initially forming a layer of solder by such commonly used methods as evaporation, electroplating, printing, solder transfer, ball placement, or the like. After a layer of solder has been formed on the structure, reflow can be performed to shape the material into the desired bump shape.

In 4 For example, dies 68 and dies 88 are attached to the first side of components 96 by, for example, flip-chip bonding via electrical connectors 77/78 and metal pillars 79 on the dies to form conductive interconnects 91 . The metal pillars 79 may be similar to the metal pillars 77 and the description is not repeated here. Die 68 and die 88 may be placed on electrical connectors 77/78 using, for example, a pick and place tool. In some embodiments, the metal cap layers 78 are deposited on the metal pillars 77 (as in 3 shown), the metal pillars 79 of the dies 68 and the dies 88, or both.

The dies 88 may be formed through processing similar to that described above with respect to the dies 68 . In some embodiments, dies 88 include one or more memory dies, such as a stack of memory dies (e.g., DRAM dies, SRAM dies, High Bandwidth Memory (HBM) dies, Hybrid Memory Cube ( HMC-) This or the like). In embodiments of the stack of memory dies, a die 88 may include both memory dies and a memory controller, such as a stack of four or eight memory dies with a memory controller. Additionally, in some embodiments, the dies 88 may be a different size (e.g., different height and/or area), and in other embodiments, the dies 88 may be the same size (e.g., the same height and/or area). .

The dies 88 include a main body 80, an interconnect structure 84, and die connectors 86. The main body 80 of the dies 88 may include any number of dies, substrates, transistors, active devices, passive devices, or the like. In an embodiment, the main body 80 may comprise a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the main body 80 may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP and/or GalnAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates can also be used. The main body 80 can be doped or undoped. Devices such as transistors, capacitors, resistors, diodes and the like can be formed in and/or on an active surface.

An interconnect structure 84 comprising one or more dielectric layer(s) and associated metallization structure(s) is formed on the active surface. The metallization structure(s) in the dielectric layer(s) can conduct electrical signals between the devices, e.g. by using vias and/or conductive traces, and may also include various electrical devices such as capacitors, resistors, inductors or the like. The various devices and metallization structures can be interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. In addition, die connectors 86, such as conductive pillars (e.g., comprising a metal such as copper), are formed in and/or on the interconnect structure 84 to provide external electrical connection to the circuits and devices. In some embodiments, die connectors 86 protrude from interconnect structure 84 to form a pillar structure to be used when bonding dies 88 to other structures. One of ordinary skill in the art will recognize that the above examples are for illustrative purposes. Other circuits can be used as needed for a given application.

In particular, an IMD layer may be formed in interconnect structure 64 . The IMD layer can be made of, for example, a low-k dielectric material such as PSG, BPSG, FSG, _SiOxCy , spin-on glass, spin-on polymers, silicon-carbon material, compounds _thereof , composites thereof , combinations thereof, or the like, may be formed by any suitable method known in the art, such as spin coating, CVD, PECVD, HDP-CVD, or the like. A metallization pattern may be formed in the IMD layer, for example using photolithographic techniques to deposit and pattern a photoresist material on the IMD layer to expose portions of the IMD layer that are to become the metallization pattern. An etch process, such as an anisotropic dry etch process, may be used to create depressions and/or openings in the IMD layer that correspond to the exposed portions of the IMD layer. The depressions and/or openings can be lined with a diffusion barrier and filled with a conductive material. The diffusion barrier layer may comprise one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt-tungsten, the like, or a combination thereof deposited by ALD or the like. The conductive material of the metallization structure may include copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, PVD, or the like. Any excess diffusion barrier layer and/or conductive material on the IMD layer may be removed, such as by using a CMP.

In the embodiments where the die connectors 66 and 86 protrude from the interconnect structures 64 and 84, respectively, the metal pillars 79 can be omitted from the dies 68 and 86 since the protruding die connectors 66 and 86 act as pillars for the metal cap layers 78 can be used.

Conductive connections 91 electrically connect the circuits in dies 68 and dies 88 through interconnect structures 84 and 64, respectively, and die connectors 86 and 66, respectively, to redistribution structure 76 and TVs 74 in components 96.

In some embodiments, the electrical connectors 77/78 are coated with a flux (not shown), such as a no-residue flux, prior to bonding the electrical connectors 77/78. The electrical connectors 77/78 can be immersed in the flux or the flux can be ejected onto the electrical connectors 77/78. In another embodiment, the flux can be applied to the electrical connectors 79/78. In some embodiments, the electrical connectors 77/78 and/or 79/78 may have an epoxy flux (not shown) formed thereon prior to being reflowed, leaving at least a portion of the epoxy portion of the epoxy flux after the dies 68 and the dies 88 have been attached to the components 96. This remaining portion of epoxy can serve as an underfill to reduce stress and protect the connections resulting from reflow of the electrical connectors 77/78/79.

The bonding between dies 68 and 88 and components 96 may be solder bonding or direct metal-to-metal (such as copper-copper or tin-tin) bonding. In one embodiment, dies 68 and dies 88 are bonded to components 96 by a reflow process. During this reflow process, electrical connectors 77/78/79 make contact with die connectors 66 and 86, respectively, and the pads of redistribution structure 76 to physically and electrically connect dies 68 and dies 88 to components 96. After the bonding process, an IMC (not shown) may form at the interface of metal pillars 77 and 79 and metal cap layers 78 .

In 4 A first housing section 90 and a second housing section 92 for forming a first housing and a second housing are shown in the following figures. Score line areas 94 lie between adjacent housing areas. As in 4 As shown, one die 68 and multiple dies 88 are mounted in both the first housing portion 90 and the second housing portion 92 .

In some embodiments, the dies 68 are a system-on-chip (SOC) or graphics processing unit (GPU) and the second dies are memory dies used by the dies 68 be able. In one embodiment, dies 88 are stacked memory dies. For example, the stacked memory dies 88 may include low power (LP) DDR memory modules such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules.

In 5 An underfill material 100 is dispensed into the gaps between dies 68, dies 88, redistribution structure 76, and around conductive interconnects 91. FIG. In 5 10 and 12 below, all conductive connections 91 are shown as comprising a single structure, but as in FIG 4 As shown, each of the conductive connections 91 may comprise two metal pillars 77 and 79 with a metal layer 78 therebetween. The underfill material 100 may extend along the sidewall of dies 68 and dies 88 . The underfill material 100 may be any suitable material, such as a polymer, epoxy, mold underfill, or the like. Underfill material 100 may be formed by a capillary flow process after dies 68 and 88 are attached, or may be formed by a suitable deposition process before dies 68 and 88 are attached.

In the 6A and 6B Dummy dies 106 are adhered in the scribe line areas 94 adjacent to the dies 88 with an attachment structure 104 . the 6A and 6B 12 show two embodiments for the attachment structure 104. The dummy dies 106 disposed in or near the scribe line areas 94 may help reduce deflection during and after singulation of the packages (see FIG 14 ) into the first and second housing portions 90 and 92. One way the dummy dies 106 can help reduce deflection is to provide support for the package during the actual singulation process. Another way that the dummy dies 106 can prevent sagging is to reduce the coefficient of thermal expansion (CTE) mismatch between the components 96 and the subsequently formed encapsulant 112 (see FIG 8th ) since the dummy dies 106 have a similar CTE to the components 96 and they reduce the amount of encapsulant 112 needed in the package.

The dummy dies 106 are attached to the components 96 with the attachment structure 104 . In some embodiments, the attachment structure 104 consists of one or more micro-bumps that bond the dummy dies 106 to the components. In some embodiments, attachment structure 104 is an adhesive that adheres dummy dies 106 to components 96 . The dummy dies 106 may be silicon, a dielectric material, the like, or a combination thereof. In some embodiments, the dummy dies 106 are actually defective active dies that have been reused as dummy dies 106 . In some embodiments, the dummy dies 106 are bulk material and do not include any active or passive devices. In some embodiments, the top surfaces of dummy dies 106 are flush with the backsides of dies 68 .

In 6A An embodiment of the micro bump attachment structure 104 is shown. In this embodiment, micro bumps 104 are formed on bottom surfaces of dummy dies 106, top surfaces of components 96, or both. Micro-bumps 104 may be formed simultaneously with those micro-bumps that will bond dies 68 and 88 (e.g., electrical connectors 77/77/78). In particular, the structures 104A, 104B and 104C of the attachment structure 104 may be the same as the structures 77, 78 and 79, respectively, and the description of these structures will not be repeated here. The micro bumps 104 bond the dummy dies 106 to the components 96, such as the redistribution structure 76 in the figure. The micro bumps 104 of the dummy dies 106 along with the electrical connectors 77/78/79 of the dies 68 and 88 can be reflowed. The dummy dies 106 may be placed on the micro bumps 104 using, for example, a pick and place tool. The underfill material 100 may be cured before or after the dummy dies 106 are bonded.

In 6B One embodiment of the adhesive attachment structure 104 is shown. In this embodiment, adhesive 104 is on bottom surfaces of dummy dies 106 and adheres dummy dies 106 to components 96, such as redistribution structure 76 in the figure. Adhesive 104 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. Adhesive 104 may be applied to a bottom surface of dummy dies 106 or over the surface of redistribution structure 76 . The dummy dies 106 may be adhered to the redistribution structure 76 by the adhesive 104 using, for example, a pick and place tool. The underfill material 100 may be cured before or after the dummy dies 106 are bonded.

In 7 Cover structures 110 are glued to the backsides of dies 88. The cover structures 110 significantly reduce the stress of the dies 88 and can maintain the dies 88 during protect it from subsequent processing. In some embodiments, the dies 88 include a stack of one or more memory dies, and the cap structures 110 are thicker than each of the one or more memory dies of the dies 88. In some embodiments, the cap structures 110 have a thickness that is in the Direction perpendicular to a main surface of the substrate 70 in a range of about 50 microns to about 200 microns, for example about 100 microns.

In some embodiments, the top surfaces of the cover structures 110 are flush with the backsides of the dies 68 and the top surfaces of the dies 106. In some embodiments, the cover structures 110 are bonded with an adhesive 108. FIG. The cap structures 110 may be silicon, a dielectric material, or the like, or a combination thereof. The cap structures 110 may include the same material as the dummy dies 106 . In some embodiments, cap structures 110 are actually defective active dies that have been reused as cap structures 110 . In some embodiments, the cap structures 110 are bulk material and do not include any active or passive devices. The adhesive 108 is on the bottom surfaces of the cover structures 110 and adheres the cover structures 110 to the dies 88 . Adhesive 108 may be any suitable adhesive, epoxy, DAF, or the like. The cover structures 110 may be adhered to the dies 88 by the adhesive 108 using, for example, a pick and place tool.

In 8th an encapsulant 112 is formed on the various components. The encapsulant 112 may be a molding compound, an epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. A curing step is performed to cure the encapsulant 112, where the curing may be a thermal cure, an ultraviolet (UV) cure, or the like. In some embodiments, dies 68, dummy dies 106, and/or cap structures 110 are embedded in encapsulant 112 and after curing of encapsulant 112, a planarization step, such as grinding, may be performed to trim excess portions of encapsulant 112 remove the excess portions overlying the top surfaces of dies 68, dummy dies 106, and/or cap structures 110. Accordingly, the top surfaces of dies 68, dummy dies 106, and/or cap structures 110 are exposed and flush with a top surface of encapsulant 112.

the 9 until 12 show the formation of the second side of the components 96. In 9 becomes the structure of 8th inverted to prepare for forming the second side of the components 96. Although not shown, the structure may be supported on a carrier or support structure for the method of FIG 9 until 12 to be placed. As in 9 As shown, the substrate 70 and the redistribution structure 76 of the components 96 at this stage of processing have a combined thickness T1 in a range from about 750 µm to about 800 µm, for example about 775 µm. The dummy dies 106 (including the attachment structure 104 ) have a thickness T2 in a range from about 750 µm to about 800 µm, for example about 760 µm. In some embodiments, die 68 and/or 88 (including conductive interconnects 91 and cap structures 110 for die 88) have thickness T2.

In 10 For example, a thinning process is applied to the second side of the substrate 70 to thin the substrate 70 to a second surface 116 until the TVs 74 are exposed. The thinning process may include an etching process, a grinding process, the like, or a combination thereof. In some embodiments, after the thinning process, the substrate 70 and the redistribution structure 76 of the components 96 have a combined thickness T3 in a range from about 20 μm to about 180 μm, for example about 100 μm.

In 11 For example, a redistribution structure is formed on the second surface 116 of the substrate 70 and is used to electrically connect the TVs 74 to each other and/or to external devices. The redistribution structure includes one or more dielectric layers 117 and metallization structures 118 in the one or more dielectric layers 117. The metallization structures may include vias and/or conductive lines to connect the TVs 74 to each other and/or to an external device. The metallization structures 118 are sometimes referred to as redistribution lines (RDLs). The dielectric layers 117 may be silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-k dielectric material such as PSG, BPSG, _FSG , _SiOxCy , spin-on glass, spin-on polymers, silicon carbon material, composites thereof , composites thereof, combinations thereof, or the like. The dielectric layers 117 may be deposited by any suitable method known in the art, such as spin coating, CVD, PECVD, HDP-CVD, or the like. The metallization Patterns 118 may be formed in dielectric layer 117 using, for example, photolithographic techniques to deposit and pattern a photoresist material on dielectric layer 117 to expose portions of dielectric layer 117 that are to become metallization patterns 118 . An etch process, such as an anisotropic dry etch process, may be used to create depressions and/or openings in dielectric layer 117 corresponding to exposed portions of dielectric layer 117 . The depressions and/or openings can be lined with a diffusion barrier and filled with a conductive material. The diffusion barrier layer may comprise one or more layers of TaN, Ta, TiN, Ti, CoW or the like deposited by ALD or the like and the conductive material may comprise copper, aluminum, tungsten, silver and combinations thereof or the like deposited by CVD, PVD or the like can be deposited. Any excess portions of the diffusion barrier layer and/or conductive material on the dielectric layer can be removed, such as by using a CMP.

In 12 Electrical connectors 120 are also formed on the metallization structures 118 and electrically connected to the TVs 74 . The electrical connectors 120 are formed on the metallization structures 118 on the top surface of the redistribution structure. In some embodiments, the metallization structures 118 include UBMs. In the embodiment shown, the pads are formed in openings of the dielectric layers 117 of the redistribution structure. In another embodiment, the pads (UBMs) may extend through an opening of a dielectric layer 117 of the redistribution structure and also extend over the top surface of the redistribution structure.

As an example of forming the pads, a seed layer (not shown) is formed at least in the opening in one of the dielectric layers 117 of the redistribution structure. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The structure of the photoresist corresponds to the pads. The pattern forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. Then the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by any suitable ashing or stripping method, for example using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, for example, by using an appropriate etching technique, such as wet or dry etching. The remaining portions of the seed layer and conductive material form the pads. In the embodiment where the pads are formed differently, more photoresist and patterning steps can be used.

In some embodiments, the electrical connectors 120 are solder balls and/or bumps, such as ball grid array (BGA) balls, C4 micro bumps, ENIG formed bumps, ENEPIG formed bumps, or the like. The electrical connectors 120 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the electrical connectors 120 are formed by initially forming a layer of solder by such commonly used methods as evaporation, electroplating, printing, solder transfer, ball placement, or the like. After a layer of solder has been formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the electrical connectors 120 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars can be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the metal pillar connectors 120 . The metal cap layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

The electrical connectors 120 can be used to connect to an additional electrical to bond a component, which may be a semiconductor substrate, a packaging substrate, a printed circuit board (PCB), or the like (see 300 in 15 ).

13 shows a plan view of the housing structure in FIG 12 . 12 is a cross-sectional view along the line AA in 13 . As in 13 As shown, the dummy dies 106 lie along the score line areas 94 surrounding each of the packaging areas 90 and 92. FIG.

In some embodiments, the dummy dies 106 are affixed within the scribe line regions 94 and extend only along those scribe line regions 94 that are along a first direction (e.g., the vertical direction of FIG 13 ) lie. In some embodiments, the package structures may include more than two dies 88 (e.g., they may include four dies 88) and the package structures may include more dies 122 between adjacent dies 88 of the same region 90 and/or 92. The dummy dies 122 are similar to the dummy dies 106 and the description will not be repeated here.

Further, in some embodiments, the dummy dies 106 are fixed in the scribe line areas 94 and extend along the scribe line areas 94, which are along a first direction and a second direction (e.g., both the vertical and horizontal directions of FIG 13 ) lie, and are also located between adjacent dies 88 of the same area 90 and/or 92.

Even though 13 shows four regions of the wafer to form four package structures after singulation, the disclosure is not limited to this set of regions and package structures. In other embodiments, the disclosure may include more or fewer regions and housing structures.

In 14 For example, components 96 and dummy dies 106 are singulated between adjacent regions 90 and 92 along scribe line regions 94 to form component packages 200 including, among other things, die 68, component 96, dies 88, cap structures 110, and portions 106' of the dummy This 106 include. The separation can be done by sawing, cutting or the like. As described above, the dummy dies 106 help reduce the stress and deflection caused during and after the singulation process.

After the singulation process, the remaining portions 106' of the dummy dies 106 have sidewall surfaces that are flush with the lateral extents of the component package 200 (see, e.g., Figs 14 and 15 ).

15 12 shows the mounting of a component package 200 on a substrate 300. Electrical connectors 120 are aligned with bond pads of the substrate 300 and pressed against them. The electrical connectors 120 can be reflowed to create a bond between the substrate 300 and the component 96 . The substrate 300 may include a packaging substrate such as a mounting substrate having a core therein, a laminate substrate having a plurality of laminated dielectric films, a PCB, or the like. The substrate 300 may have electrical connectors (not shown), such as solder balls, opposite the component package to allow the substrate 300 to be attached to another device. An underfill material (not shown) may be dispensed between the component package 200 and the substrate 300 and surround the electrical connectors 120 . The underfill material can be any suitable material such as a polymer, epoxy, mold underfill or the like.

Additionally, one or more surface devices 140 may be bonded to the substrate 300 . The surface devices 140 may be used to provide additional functionality or programming to the component package 200 or the package as a whole. In one embodiment, the surface devices 140 may include surface mount devices (SMDs) or integrated passive devices (IPDs), which may include passive devices such as resistors, inductors, capacitors, jumpers, combinations thereof, or the like that may be connected to the component package 200 or other parts of the Housing used and to be connected to them. The surface devices 140 may be arranged on a first major surface of the substrate 300, an opposite major surface of the substrate 300, or both, according to various embodiments.

16 12 shows a cross-sectional view of a package structure according to some embodiments. The embodiment in 16 is similar to the embodiment in FIGS 1 until 15 , except that 16 no encapsulant 112 comprises. The dummy dies 106 and cap structures 110 may provide sufficient stress reduction and protection such that the encapsulant may be omitted. Details of this embodiment that are the same or similar to the previous embodiment will not be repeated here.

17 12 shows a cross-sectional view of a package structure according to some embodiments men. The embodiment in 16 is similar to the embodiment in FIGS 1 until 15 , except that the 17 includes a cap structure 132 over the entire package structure that is adhered to the die 68, the dies 88, and the dummy dies 106. FIG. Adhesive 130 and cover structure 132 may be made of similar materials as the adhesive and cover structure described above in the previous embodiment. Details of this embodiment that are the same or similar to the previous embodiment will not be repeated here.

In 17 For example, the cover structure 132 is attached to the underlying components by an adhesive 130 . In some embodiments, the cap structures 132 are placed after the encapsulant 112 is formed. Although not shown, the cover structures 110 may be provided on the dies 88, with the cover structure 132 overlying the cover structures 110 and the other components of the housing. In some embodiments, the cap structure 132 is wafer-sized and a cap structure is placed over all areas of the wafer (e.g., 90, 92, etc.) and singulated to form individual cap structures 132 in each of the package structure areas. In other embodiments, individual cap structures 132 are placed over each of the regions of the wafer (e.g., 90, 92, etc.) prior to singulation.

18 12 shows a cross-sectional view of a package structure according to some embodiments. The embodiment in 18 is similar to the embodiment in FIG 17 , except that 18 no encapsulant 112 comprises. The dummy dies 106 and cap structure 132 may provide sufficient stress reduction and protection that the encapsulant may be omitted. Details of this embodiment that are the same or similar to the previous embodiment will not be repeated here.

19 12 shows a cross-sectional view of a package structure according to some embodiments. The embodiment in 19 is similar to the embodiment in FIGS 1 until 15 , except that the case structure is 500 in 19 This includes 400A and 400B and does not include dummy dies. Details of this embodiment that are the same or similar to the previous embodiment will not be repeated here.

The 400A can be a logic die (e.g. a main processing unit, a graphics processing unit, a system-on-chip, a microcontroller, etc.), a power management die (e.g. an integrated power management Integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microsystems (MEMS) die, a signal processing die (eg, a digital signal processing (DSP) die ), a front-end die (e.g., an analog front-end (AFE) die), the like, or a combination thereof. Die 400A may include one or more logic dies. The die 400A can be placed and bonded on the component 96 similar to the dies 68 described above and the description will not be repeated here.

The dies 400B may be memory dies, such as DRAM dies, SRAM dies, HBM dies, High Bandwidth Memory (HBM) dies, Hybrid Memory Cube (HMC) dies, or the like. In some embodiments, a die 400B may include both memory dies and a memory controller, such as a stack of four or eight memory dies with a memory controller. The dies 400B may be placed and bonded on the component 96 similar to the dies 88 described above and the description will not be repeated here.

An example die 400B according to some embodiments is more detailed in FIG 20 shown. A main body 405 may include a plurality of stacked memory dies 408 and a top die 412 . The stacked memory dies 408 may all be identical dies, or the memory dies 408 may include dies of different types and/or structures. Each memory die 408 is connected to an overlying memory die 408 and/or an underlying memory die 408 by a connector 406 . Connectors 406 may be micro bumps or other suitable connectors. Memory dies 408 may include vias 410 connecting underlying connectors 406 to overlying connectors 406 . In one embodiment, memory dies 408 each have a thickness T4 in a range from about 20 μm to about 100 μm, for example about 60 μm.

In some embodiments, the main body 405 may include High Bandwidth Memory (HBM) and/or High Memory Cube (HMC) modules, which may include one or more memory dies 408 connected to a logic die 402 . The logic die 402 may include vias 404 connecting a conductive feature of a connection area (not shown) to an overlying connector 406 and memory dies 408 . In some embodiments, logic die 402 may be a memory controller. The connection area (not shown) may provide a conductive structure that allows for a pinout contact structure for the main body 405 that differs from the structure of the conductive connections 91, allowing for a larger one Flexibility in the arrangement of the conductive connections 91 allows. Conductive interconnects 91 may be located on a bottom side of dies 400B and may be used to physically and electrically connect dies 400B to components 96 . The conductive connections 91 may be electrically connected to the logic die 402 and/or the stacked memory dies 408 through the connection area. The conductive interconnects 91 may be formed using methods the same or similar to the methods described above for the conductive interconnects 91, and the description is not repeated here.

Top die 412 may be a similar die (in function and circuitry) to memory dies 408, except that top die 412 is thicker than memory dies 408. In some embodiments, top die 412 is a dummy Die 10 and 11 is similar to cap structures 110 described above. In some embodiments, top die 412 has a thickness T5 in a range from about 50 µm to about 200 µm, for example about 150 µm. In some embodiments, the top die 412 has a thickness T5 that is greater than about 120 μm. It has been found that a top die 412 of dies 400B having a thickness greater than about 120 μm increases the yield of the package structure 500 without requiring the dummy dies 106 and cap structures 110 and 132 of the previous embodiments.

As in 20 As shown, the main body 405 may be encapsulated in a molding material 414 . The molding material 414 may include a molding compound, a mold underfill, an epoxy, or a resin.

Even though 20 a die 400B with memory-this shows the logic-die 400A from 19 have a similar stacked structure with a thicker top die 412.

21 12 shows a cross-sectional view of a package structure according to some embodiments. The embodiment in 21 is similar to the embodiment in FIGS 19 and 20 , except that the case structure in 21 does not include the encapsulant 112. Details of this embodiment that are the same or similar to the previous embodiment will not be repeated here.

The disclosed embodiments include a package structure with dummy structures adjacent to active dies to reduce deflection of the package structure. This reduction in package structure deflection allows for a more reliable package structure by reducing the likelihood of cold solder joints between the active dies and the interposer. In some embodiments, the dummy dies are in the scribe line areas and cap structures cover some of the active dies while other active dies are not covered by cap structures. The dummy dies may allow for better control of the encapsulant content and thus reduce stress and deflection due to the coefficient of thermal expansion (CTE) mismatch. In some embodiments, the encapsulant may be omitted if the dummy dies in the scribe line areas and/or the cover structures provide sufficient support and protection for the package structure. In some embodiments, the active dies are stacks of one or more dies (logic die-stack and/or memory die-stack), where the top die of the die-stack is thicker than the other dies of the die-stack. In these embodiments, the dummy dies in the scribe line areas and the encapsulant can be omitted since thicker top dies of the die stack provide sufficient support and protection for the package structure.

One embodiment is a method comprising: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to the first side of the first component using second electrical connectors, attaching a dummy -Dies on the first side of the first component in a scribe line area of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and dummy dies to form a package structure.

Implementations may include one or more of the following features. The method where the first component is a third die. The method further comprising: attaching the package structure to a second substrate, wherein the first component is disposed between the first and second dies and the second substrate. The method where singulating includes sawing through the first component and the dummy die to form the package structure. The method wherein the first component is a bulk substrate comprising a redistribution structure, the first and second dies being attached to the redistribution structure. The method wherein the first die includes one or more logic dies and wherein the second die includes one or more memory dies. The method further comprising: forming vias extending through the first component corners, wherein the first and second dies are electrically connected to the vias; forming third electrical connectors on a second side of the first component, the second side opposite the first side, the third electrical connectors being electrically connected to the vias; attaching the housing structure to a second substrate using the third electrical connectors; and bonding a surface mounted device (SMD) to the second substrate. The process where the dummy die and cap structure are made of silicon.

One embodiment is a method, comprising: bonding a first die to a first side of a first structure using first electrical connectors; bonding a memory die to the first side of the first structure using second electrical connectors, the memory die being adjacent to the first die; attaching a second die to a backside of the memory die, the second die having a thickness greater than a thickness of the memory die; and singulating the first structure to form a package structure.

Implementations may include one or more of the following features. The method wherein a thickness of the second die is greater than or equal to 120 µm. The method where attaching the second die to the backside of the memory die comprises bonding the second die to the backside of the memory die, the second die being a memory die electrically connected to the memory die. The method where attaching the second die to the backside of the memory die comprises adhering the second die to the backside of the memory die with an adhesive layer, wherein the second die is bulk material and has no active or passive devices . The method further comprising: forming an underfill between the first side of the first structure and the first die and the memory die and surrounding the first electrical connectors and the second electrical connectors; and encapsulating the first die and the memory die with an encapsulant, wherein the encapsulant is contiguous with portions of the underfill. The method further comprising: adhering a plurality of dummy dies to the first side of the first structure in scribe line areas of the first structure, wherein singulating the first structure to form the plurality of package structures comprises singulating the plurality of dummy dies. The method further comprising: prior to bonding the first die to a first side of a first structure, forming vias in the first structure; forming a first redistribution structure on the vias, the first redistribution structure being the first side of the first structure, the first redistribution structure being electrically connected to the vias; thinning a second side of the first structure to expose the ends of the vias, the second side opposite the first side; forming a second redistribution structure on the second side of the first structure, thereby forming a first interposer, the second redistribution structure being electrically connected to the exposed ends of the vias; forming third electrical connectors on and electrically connected to the first redistribution structure; bonding the third electrical connectors to a first substrate; and bonding a surface mounted device (SMD) to the first substrate adjacent one of the third electrical connectors.

One embodiment is a structure, comprising: a first side of an interposer bonded to a package substrate; active sides of a first die and a second die bonded to a second side of the interposer, the second side opposite the first side; a dummy die attached to the second side of the interposer, the dummy die being adjacent to at least one of the first die and the second die; and a cover structure glued to the backside of the second die.

Implementations may include one or more of the following features. The structure where the dummy die is made of silicon. The structure where the second die includes one or more memory dies, wherein the cap structure is thicker than each of the one or more memory dies. The structure wherein the cover structure is further adhered to a backside of the first die and a top surface of the die.

Claims (20)

A method comprising: attaching a first die (68) to a first side of a first component (96) using first electrical connectors (91); attaching a first side of a second die (88) to the first side of the first component (96) using second electrical connectors (78); Attaching a dummy die (106) to the first side of the first component (96) in a scribe line area (94) of the first component (96), but not gluing a cap structure (110) to a second side of the second die (88). to the first die; and singulating the first component (96) and the dummy dies (106) to form a package structure (200). procedure after claim 1 , where the first component is a third die. procedure after claim 1 or 2 , further comprising: attaching the package structure (200) to a second substrate (300), wherein the first component (96) is disposed between the first die and the second die and the second substrate. The method of any preceding claim, wherein singulating includes sawing through the first component (96) and the dummy die (106) to form the package structure. The method of any preceding claim, wherein the first component is a bulk substrate (70) comprising a redistribution structure (76), the first die (68) and the second die (88) being attached to the redistribution structure. The method of any preceding claim, wherein the first die (68) includes one or more logic dies and wherein the second die (88) includes one or more memory dies. Method according to any one of the preceding claims, further comprising: forming vias (74) extending through the first component (96), the first die (68) and the second die (88) being electrically connected to the vias, forming third electrical connectors (120) on a second Side of the first component (96), the second side opposite the first side, the third electrical connectors (120) being electrically connected to the vias (74), attaching the package structure (200) to a second substrate (300) using the third electrical connectors (120); and bonding a surface mount device (140) to the second substrate. A method according to any one of the preceding claims, wherein the dummy die (106) and the cap structure (110; 134) are made of silicon. Method comprising: bonding a first die (68;440A) to a first side of a first structure (96) using first electrical connectors (78); bonding a memory die (88; 408s) to the first side of the first structure (96) using second electrical connectors (78), the memory die being adjacent to the first die; Attaching a second die (110; 412) to a backside of the memory die (88; 408s), the second die being aligned with the memory die in a semiconductor stack and having a thickness greater than a thickness of the memory die This is; and Singulating the first structure to form a housing structure. procedure after claim 9 , wherein a thickness of the second die is greater than or equal to 120 µm. procedure after claim 9 or 10 , wherein attaching the second die (110; 412) to the backside of the memory die (88; 408s) comprises bonding the second die to the backside of the memory die, the second die being a memory die that is electrically connected to the memory die. procedure after claim 9 or 10 wherein attaching the second die (110; 412) to the backside of the memory die (88; 408s) comprises adhering the second die to the backside of the memory die with an adhesive layer, the second die being a bulk material consists of no active or passive devices. Method according to any of the preceding claims 9 until 12 , further comprising: forming an underfill (100) between the first side of the first structure and the first die (68; 440A) and the memory die (88; 408s) and the first electrical connectors (78) and the second electrical connectors ( 78) surrounding; and encapsulating the first die and the memory die with an encapsulant (112), the encapsulant being contiguous with portions of the underfill. Method according to any of the preceding claims 9 until 13 , further comprising: adhering a plurality of dummy dies (106) to the first side of the first structure (96) in scribe line areas of the first structure, wherein singulating the first structure to form the package structure comprises singulating the plurality of dummy dies (106 ) includes. Method according to any of the preceding claims 9 until 14 , further comprising: prior to bonding the first die (68;440A) to a first side of a first structure (96), forming vias (74) in the first structure, forming a first redistribution structure (76) on the vias, wherein the first redistribution structure the first page of the first th structure (96), the first redistribution structure (76) being electrically connected to the vias (74); thinning a second side of the first structure (96) to expose ends of the vias, the second side opposite the first side; forming a second redistribution structure (117, 118) on the second side of the first structure, thereby forming a first interposer, the second redistribution structure (117, 118) being electrically connected to the exposed ends of the vias (74); forming third electrical connectors (120) on and electrically connected to the first redistribution structure; bonding the third electrical connectors (120) to a first substrate (300), and bonding a surface mount device (140) to the first substrate adjacent one of the third electrical connectors. Method according to any of the preceding claims 9 until 15 , where the first die comprises one or more logic dies. Structure comprising: a first side of an interposer (96) bonded to a package substrate (300); a first die 68 and a second die 88, active sides of the first die (68) and second die (88) being bonded to a second side of the interposer (96), the second side opposite the first side; a dummy die (106) attached to the second side of the interposer (96), the dummy die being adjacent to at least one of the first die and the second die; and a first cap structure (110, 412) adhered to a backside of the second die (88) and aligned with the second die in a semiconductor stack and having a thickness greater than a thickness of the second die. structure after Claim 17 , where the dummy die is made of silicon. structure after Claim 17 or 18 wherein the second die comprises one or more memory dies, the first cap structure (110, 412) being thicker than each of the one or more memory dies. Structure according to any of the preceding claims 17 until 19 wherein a second cap structure (132) is further adhered to a backside of the first die (68) and to a top surface of the first cap structure (110, 412).

Images