DE102004039834A1 - Method of insulating and electrically contacting components or chips arranged on a substrate by provided a metalized structured insulation layer - Google Patents

Method of insulating and electrically contacting components or chips arranged on a substrate by provided a metalized structured insulation layer Download PDF

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Publication number
DE102004039834A1
DE102004039834A1 DE102004039834A DE102004039834A DE102004039834A1 DE 102004039834 A1 DE102004039834 A1 DE 102004039834A1 DE 102004039834 A DE102004039834 A DE 102004039834A DE 102004039834 A DE102004039834 A DE 102004039834A DE 102004039834 A1 DE102004039834 A1 DE 102004039834A1
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Prior art keywords
substrate
component
insulating
structured
insulating layer
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DE102004039834A
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German (de)
Inventor
Michael Kaspar
Karl Weidner
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Siemens AG
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Siemens AG
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Priority to DE102004039834A priority Critical patent/DE102004039834A1/en
Priority to EP05857310A priority patent/EP1779420A1/en
Priority to PCT/EP2005/053551 priority patent/WO2006084509A1/en
Publication of DE102004039834A1 publication Critical patent/DE102004039834A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

The method involves applying a structured insulation layer (3) to the substrate (1) on which the components (2) are mounted using an ink jet printing process. The structured insulation layer is then metalized to provide conductive structures (4). Independent claims also cover a device made according to the method.

Description

Die vorliegende Erfindung betrifft ein Verfahren zur Isolierung und elektrischen Kontaktierung von auf einem Substrat angeordneten Bauelementen beispielsweise Chips oder LEDs (Licht emittierende Dioden), die Bereitstellung entsprechender Chip-Packages sowie eines entsprechenden Halbleitererzeugnisses.The The present invention relates to a process for isolation and electrical contacting of arranged on a substrate components For example, chips or LEDs (light emitting diodes), the Provision of appropriate chip packages and a corresponding Semiconductor product.

Auf herkömmliche Weise werden laserstrukturierte oder fotostrukturierte Isolierfolien oder Lacke verwendet.On conventional In this way, laser-structured or photo-structured insulating films are used or paints used.

Die Strukturierung von Isolierfolien erfolgt dabei in nachteiliger Weise erst nach dem Aufbringen der Isolierfolien. D.h. es ist ein zusätzlicher Prozessschritt erforderlich. Es kann außerdem beim Auftreten von fehlerhaften zu strukturierenden oder zu prozessierenden Bauelementen zu Fehlanpassungen kommen. Weiterhin sind zur Strukturierung aufwändige Masken erforderlich. Ebenso sind zusätzliche Reinigungs- und Entschichtungsschritte auszuführen, so dass die herkömmlichen Strukturierungsverfahren sehr kostenintensiv sind.The Structuring of insulating takes place in a disadvantageous way only after the application of the insulating films. That it is an additional one Process step required. It may also occur in the event of faulty come to be structured or processed components to mismatches. Furthermore, elaborate masks are required for structuring. Likewise are additional Perform cleaning and stripping steps, so that the conventional Structuring methods are very expensive.

Es ist damit Aufgabe der vorliegenden Erfindung die vorstehend genannten Nachteile zu vermeiden und ein kostengünstiges flexibles Chip-Package auf unterschiedlichen Substraten mit hoher Prozesssicherheit bereit zu stellen. Es soll eine Isolierung der Bauelemente und eine direkte Leiterstrukturierung mit geringem Abstand (Pitch) und flexiblem Layout bereitgestellt werden. Die dazu erforderlichen Daten können über AOI- Systeme (automatisch-optische Inspektions-Systeme) generiert werden.It is the object of the present invention, the above Avoid disadvantages and a cost-effective flexible chip package different substrates with high process reliability ready to deliver. It should be an insulation of the components and a direct Conductor structuring with a small pitch and flexible Layout be provided. The data required for this can be transmitted via AOI systems (automatic-optical Inspection systems) are generated.

Diese Aufgabe wird durch das in dem unabhängigen Hauptanspruch angegebene Verfahren bzw. das in dem Nebenanspruch angegebene Erzeugnis gelöst. Vorteilhafte Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.These The object is achieved by that specified in the independent main claim Process or the product specified in the independent claim. advantageous Embodiments emerge from the dependent claims.

Mit einem sogenannten Ink Jet Printing-Verfahren (Tintenstrahldruckverfahren) wird eine strukturierte Isolierschicht oder Funktionsschicht auf ein mit Bauelementen bestücktes Substrat aufgebracht. Durch das strukturierte Aufbringen können durch nachstehend beschriebene Folgeprozesse auf einfache Weise Leiterstrukturen erzeugt werden. Die Isolierschicht dient dabei insbesondere als elektrische, thermische, mechanische und/oder chemische Barriere beispielsweise gegen Umwelteinflüsse wie Feuchte oder gegen aggressive Prozessmedien.With a so-called ink jet printing process (inkjet printing process) becomes a structured insulating layer or functional layer a equipped with components Substrate applied. The structured application can be achieved by the following described follow-up processes generated in a simple way ladder structures become. The insulating layer serves in particular as electrical, thermal, mechanical and / or chemical barrier, for example against environmental influences such as humidity or against aggressive process media.

Im Folgenden werden Folgeprozesse zur Erzeugung von Leiterstrukturen beispielhaft beschrieben: Die Isolierschichten werden durch Direktstrukturierung (MID) oder andere Standardverfahren metallisiert, wobei dadurch Leiterstrukturen im feinen Raster hergestellt werden können. Auf diese Weise können Leiterstrukturen mit geringem Abstand zueinander bei einem flexiblen Layout bereitgestellt werden.in the Following are follow-up processes for the creation of ladder structures described by way of example: The insulating layers are formed by direct structuring Metallized (MID) or other standard methods, thereby Ladder structures in fine grid can be produced. On this way you can Conductor structures with a small distance from each other in a flexible Layout be provided.

Zur Erzeugung von Leiterzügen auf Isoliermaterial kann ein additives Verfahren analog der in der Moulded Interconnect Devices(MID)-Technik eingesetzten Laser-Direkt-Strukturierung verwendet werden. Das aufzubringende Isoliermaterial wird mittels eines eingebrachten Wirksystems auf der Basis anorga nische Verbindungen modifiziert. Nach dem Aufspritzen des Isoliermaterials über die zu verbindenden Strukturen durch Ink Jet-Coating erfolgt eine selektive Aktivierung der Oberfläche mit einem UV-Laser in Form eines Freilegens von Metallisierungskeimen über eine physio-chemische Reaktion. An diesen Keimen wird dann in einem darauf folgenden Metallisierungsprozess eine Metallabscheidung, beispielsweise eine Kupferabscheidung ausgelöst. Ebenso kann das modifizierte Isoliermaterial mit einem Spritzgussverfahren über die zu verbindenden Strukturen derart aufgebracht werden, dass die Kontaktöffnungen im Isoliermaterial bereits abgeformt sind (Potential mit Materialien wie PBT (Pocan von Beyer Polymers), LCP (WIAC, Zyvex)).to Generation of conductor tracks On insulating material, an additive method analogous to that in the Molded interconnect devices (MID) technique used laser direct structuring be used. The applied insulating material is by means of an introduced active system based on inorganic connections modified. After spraying the insulating over the To be connected structures by ink jet coating is a selective Activation of the surface with a UV laser in the form of exposing metallization via a physio-chemical reaction. These germs will then be in one following metallization a metal deposition, for example triggered a copper deposition. As well The modified insulating material can be injection molded over the structures to be connected are applied such that the contact openings already molded in the insulating material (potential with materials such as PBT (Pocan from Beyer Polymers), LCP (WIAC, Zyvex)).

Durch das vorliegende Verfahren können vorteilhaft unterschiedlich dicke Isolierschichten aufeinander und/oder nebeneinander erzeugt werden. Damit kann die Isolierung an gegebene Rahmenbedingungen des Chips bzw. Bauelements optimal angepasst werden.By the present method may be advantageous different thickness insulating layers on each other and / or next to each other be generated. This allows the insulation to given conditions of the chip or component are optimally adapted.

Es können weiterhin vorteilhaft unterschiedlich große und unterschiedlich geformte Öffnungen in der bzw. den Isolierschicht(en) erzeugt werden. Auf diese Weise können elektrische Kontaktierungen besonders einfach ausgebildet werden. Die Leiterstrukturen sind auf einfache Weise mit den Bauelementen verbindbar.It can Furthermore advantageously different sized and differently shaped openings in the or the insulating layer (s) are generated. In this way can electrical contacts are made particularly simple. The conductor structures can be easily connected to the components.

Es können zudem besonders vorteilhaft frei wählbare Isolierschichtdicken erzeugt werden. Damit kann die Isolierung an die Umgebungsbedingungen besonders einfach angepasst werden.It can In addition, particularly advantageous freely selectable insulating layer thicknesses be generated. This allows the insulation to the ambient conditions especially easy to be customized.

Gemäß einer weiteren bevorzugten Ausführungsart kann zur verbesserten Isolierung des Bauelements ein Abdichtrahmen ent lang der Bauelementekanten, insbesondere durch die strukturierte Isolierschicht, ausgebildet werden. Dies ist insbesondere beispielsweise bei Flip-Chip-Applikationen zum Schutz von darunter befindlichen Funktionsstrukturen vorteilhaft.According to one another preferred embodiment can for improved isolation of the device a sealing frame Ent long component edges, in particular by the structured Insulating layer to be formed. This is especially for example in flip-chip applications to protect from underneath Functional structures advantageous.

Es können zudem schräg ablaufende Bauelementekanten über Stufenbeschichtungen bereitgestellt werden.It can also be sloping construction Element edges over step coatings are provided.

Es ist weiterhin vorteilhaft, wenn speziell angepasste Abdeckungen, insbesondere durch die strukturierte Isolierschicht, erzeugt werden. Alternativ können auch zu der Isolierung zusätzliche Abdeckschichten vorgesehen sein.It is also advantageous when specially adapted covers, in particular by the structured insulating layer can be generated. Alternatively you can also additional to the insulation Covering be provided.

Gemäß dieser Anmeldung ist die Isolierschicht direkt auf einem Bauelement und/oder auf einem Substrat aufgebracht.According to this Registration is the insulating layer directly on a device and / or applied to a substrate.

Mittels der erfindungsgemäßen Ausführungsformen wird auf besonders vorteilhafte Weise eine nachträgliche Laserstrukturierung oder Fotostrukturierung der Isoliermaterialien vermieden. Es kann zudem eine einfache Direktmetallisierung durchgeführt werden. Zudem kann kostengünstig und mit hoher Genauigkeit ein Isolieren und Kontaktieren von Bauelementen bzw. Chips durchgeführt werden. Weiterhin kann eine Strukturierung nach AOI-(automatische optische Inspektions-) Daten (beispielsweise Daten über Chippositionen auf einem Substrat) erfolgen. Auf diese Weise werden beispielsweise fehlerhafte Bauteile nicht strukturiert bzw. prozessiert. Verschobene Bauteile können korrigiert strukturiert bzw. prozessiert werden. Das vorliegende Verfahren ermöglicht eine hohe Flexibilität, wobei keine Masken bereitgestellt werden müssen, so dass daraus ein hoher Einspareffekt folgt. Die Verfahren sind sehr flexibel und schnell durchführbar. Zudem sind Lacke mit z.B. durch Füllstoffe, Farbe oder Zusammensetzung angepassten Eigenschaften einsetzbar, womit sich daraus eine hohe Flexibilität und optimale Applikationsanpassungen ergeben. Weitere Kosteneinsparungen ergeben sich, da aufwändige Reinigungs- und Entschichtungsprozesse entfallen.through the embodiments of the invention In a particularly advantageous manner, a subsequent laser structuring or photo-structuring of the insulating materials avoided. It can In addition, a simple direct metallization can be performed. In addition, can be inexpensive and with high accuracy insulating and contacting of components or chips are performed. Furthermore, structuring according to AOI (automatic optical Inspection) data (for example, data about chip positions on a substrate) respectively. In this way, for example, defective components not structured or processed. Moved components can be corrected be structured or processed. The present method allows a high flexibility, whereby no masks need to be provided, making it a high Savings effect follows. The procedures are very flexible and fast feasible. moreover are paints with e.g. through fillers, Color or composition adapted properties can be used, resulting in high flexibility and optimal application adjustments result. Further cost savings arise as elaborate cleaning and stripping processes are eliminated.

Die vorliegende Erfindung wird anhand eines Ausführungsbeispiels in Verbindung mit einer 1 beschrieben. Es zeigt:The present invention is based on an embodiment in conjunction with a 1 described. It shows:

1 ein Ausführungbeispiel eines mittels eines Tinten-Strahl-Druck-Verfahrens ausgebildeten Erzeugnisses. 1 an embodiment of a product formed by means of an ink jet printing method.

Gemäß dem Ausführungsbeispiel wird auf einem Substrat 1 ein Bauelement 2 angeordnet. Eine an dem Substrat 1 und dem Bauelement 2 angeordnete Isolierschicht 3 wurde mittels eines Tinten-Strahl-Druck-Verfahrens auf dem mit dem Bauelement 2 bestückten Substrat 1 strukturiert aufgebracht. Entsprechend der Strukturierung werden durch Metallisierungen Leiterstrukturen 4 aufgebracht, die über Öffnungen 5 der Isolierschicht 3 mit dem Bauelement 2 verbindbar sind. Leiterstrukturen können ebenso mittels Galvanisierungsverfahren bereitgestellt werden.According to the embodiment is on a substrate 1 a component 2 arranged. One on the substrate 1 and the device 2 arranged insulating layer 3 was applied to the device by means of an ink-jet printing process 2 equipped substrate 1 structured applied. According to the structuring, metallization leads to conductor structures 4 applied, over openings 5 the insulating layer 3 with the component 2 are connectable. Conductor structures can also be provided by electroplating.

Claims (8)

Verfahren zur Isolierung und elektrischen Kontaktierung eines auf einem Substrat (1) angeordneten Bauelements (2) bzw. Chips, gekennzeichnet durch – Aufbringen einer strukturierten Isolierschicht (3) mittels eines Tinten-Strahl-Druck-Verfahrens auf dem mit den Bauelement (2) bestückten Substrat (1), und – Metallisieren der strukturierten Isolierschicht (3) zur Bereitstellung von Leiterstrukturen (4).Process for the isolation and electrical contacting of a material on a substrate ( 1 ) arranged component ( 2 ) or chips, characterized by - applying a structured insulating layer ( 3 ) by means of an ink jet printing process on the surface with the component ( 2 ) equipped substrate ( 1 ), and - metallizing the structured insulating layer ( 3 ) for the provision of ladder structures ( 4 ). Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass mehrere verschieden dicke Isolierschichten (3) bereitgestellt werden.A method according to claim 1, characterized in that several different thickness insulating layers ( 3 ) to be provided. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass in Isolierschichten (3) unterschiedliche Öffnungen (5) bereitgestellt werden.Method according to claim 1 or 2, characterized in that in insulating layers ( 3 ) different openings ( 5 ) to be provided. Verfahren nach einem oder mehreren der vorangehenden Ansprüche 1 bis 3, dadurch gekennzeichnet, dass die Isolierschichtdicken frei wählbar sind.Method according to one or more of the preceding claims 1 to 3, characterized in that the insulating layer thicknesses free are selectable. Verfahren nach einem oder mehreren der vorangehenden Ansprüche 1 bis 4, dadurch gekennzeichnet, dass Abdichtrahmen entlang der Bauelementkanten bereitgestellt werden.Method according to one or more of the preceding claims 1 to 4, characterized in that sealing frame along the Component edges are provided. Verfahren nach einem oder mehreren der vorangehenden Ansprüche 1 bis 5, dadurch gekennzeichnet, dass schräg verlaufende Bauelementkanten über Stufenbeschichtungen bereitgestellt werden.Method according to one or more of the preceding claims 1 to 5, characterized in that oblique component edges on step coatings to be provided. Verfahren nach einem oder mehreren der vorangehenden Ansprüche 1 bis 6, dadurch gekennzeichnet, dass Abdeckungen des Bauelements (2) bereitgestellt werden.Method according to one or more of the preceding claims 1 to 6, characterized in that covers of the component ( 2 ) to be provided. Erzeugnis mit – einem Substrat (1), – einem an dem Substrat (1) angeordneten Bauelement (2), – eine an dem Substrat (1) und dem Bauelement (2) angeordneten Isolierschicht (3), dadurch gekennzeichnet, dass – die Isolierschicht (3) mittels eines Tinten-Strahl-Druck-Verfahrens auf dem mit dem Bauelement (2) bestückten Substrat (1) strukturiert aufgebracht ist, und – zur Bereitstellung von Leiterstrukturen (4) metallisiert ist.Product with - a substrate ( 1 ), - one on the substrate ( 1 ) arranged component ( 2 ), - one on the substrate ( 1 ) and the component ( 2 ) arranged insulating layer ( 3 ), characterized in that - the insulating layer ( 3 ) by means of an ink jet printing process on the surface with the component ( 2 ) equipped substrate ( 1 ) is structured, and - to provide ladder structures ( 4 ) is metallized.
DE102004039834A 2004-08-17 2004-08-17 Method of insulating and electrically contacting components or chips arranged on a substrate by provided a metalized structured insulation layer Withdrawn DE102004039834A1 (en)

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Application Number Priority Date Filing Date Title
DE102004039834A DE102004039834A1 (en) 2004-08-17 2004-08-17 Method of insulating and electrically contacting components or chips arranged on a substrate by provided a metalized structured insulation layer
EP05857310A EP1779420A1 (en) 2004-08-17 2005-07-21 Economical assembly and connection technique by means of a printing method
PCT/EP2005/053551 WO2006084509A1 (en) 2004-08-17 2005-07-21 Economical assembly and connection technique by means of a printing method

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DE102004039834A DE102004039834A1 (en) 2004-08-17 2004-08-17 Method of insulating and electrically contacting components or chips arranged on a substrate by provided a metalized structured insulation layer

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Publication number Priority date Publication date Assignee Title
WO2007096017A1 (en) * 2006-02-20 2007-08-30 Siemens Aktiengesellschaft Method for producing planar insulating layers with breakthroughs at the correct position by means of laser cutting and devices produced accordingly
US8191243B2 (en) 2006-02-20 2012-06-05 Siemens Aktiengesellschaft Method for making contact with a contact surface on a substrate

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WO2006084509A1 (en) 2006-08-17

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