DD274923A1 - INTERNAL SELF-TEST AND REDUNDANCY PROGRAMMING PROCEDURE FOR MEMORY CIRCUITS AND ARRANGEMENT FOR CARRYING OUT THE METHOD - Google Patents

Abstract

The programming for memory circuits permits starting an internal self-tutoring of the memory, on application of an operational voltage and attaining an inner stability. According to the determined redundancy structure, an internal programming of redundancy bit decoders (6) or redundancy word coders (7) is carried out. The included associative memory cells (30) in the coders are allocated to bit (2.4), or word lines (2.5). During the redundancy programming, at the self-test start, a reset redundance validity FF (33) is adjusted. The positive end of the self-test releases blocked control inputs and possibly a signal at an output pin (MR). With a faultless memory matrix (2), an irreversible memory element (25) is programmed. ADVANTAGE - No atypical conditions on programming of redundant lines.

Description

Field of application of the invention

The invention relates to an internal self-test and redundancy programming method for memory circuits of maximum integration. It is used for automatic redundancy programming of the faulty memory circuits during commissioning of the memory or on external request.

Characteristic of the known state of the art

To shorten the tester test time, apart from the known m-b; t test mode, further different methods have been started. In the IEEE-International Test Conference 1987, a parallel test method is described that based on additional

internal assemblies on the tester. It dows a test time reduction proportional to N -, which

As the degree of integration increases, it involves a significant reduction in the required test time compared to conventional test methods.

Another way of reducing external test integrity is achieved by a full internal testing of the memory circuitry performed by an internal self-test processor. One concept for this is the IEEE-Int.

Test Conf. 1987, p. 45, in which error addresses are output from the memory circuit or an internal redundancy program is carried out by means of irreversibly programmable memory elements.

Disadvantages are the untypical operating conditions of increased voltages or currents in the programming of irreversible memory elements or the additional technology steps in the use of EEPROM cells.

Object of the invention

The object of the invention is to provide an internal self-test and redundancy programming method for memory circuits and the arrangement necessary for carrying out the method, which only requires the technology required for the manufacture of the memory circuit and generates no untypical operating conditions when programming redundant lines.

Explanation of the essence of the invention

The invention solves the problem in that tested by means of the internal self-test processor with t'etriebsbeginn the memory circuits and the faulty lines are replaced by redundant lines by means of appropriately programmed static memory cells.

The invention relates to an internal self-test and redundancy programming method for memory circuits, in which the internally stored self-test method is started after applying the operating voltage and achieving internal stability. Once started, the external control inputs, addresses and data inputs / outputs of the memory circuit are latched. Thereafter, an internal, required for performing the method self-test processor is first checked internally. Thereafter, the data paths of the memory circuit are checked and then the matrix is checked with the memory cells. The error addresses are stored in a register bank of the self-test processor and determined from the distribution of error addresses the optimal redundancy structure. After redundancy programming, the selected redundancy bit or word lines are subjected to the self-test.

According to the invention, an internal programming of redundancy Bitbzw. According to the determined redundancy structure. Word decoders containing erasable associative memory cells. These associative memory cells lose their information after the memory circuit is turned off again and are reprogrammed each time the power is turned on. The redundancy bit or word decoder are assigned in a known manner, the redundancy bit or word lines. Furthermore, in redundancy programming, a redundancy validity FF associated with the respective redundancy bit or word decoder is set with the writing of the error address in the associative memory cells, which was reset with the start of the method. Following the self-test procedure, the positive completion of the self-test procedure is indicated by a signal on an output pin and / or by the release of the locked control inputs, addresses and data in / data outputs. If the memory matrix is error-free, an irreversible memory element may be programmed. This is used to block the self-test when switching the memory circuit, since this redundancy programming is no longer necessary. This allows seizure types to be selected for fast operational readiness.

The arrangement for carrying out the method consists of a memory circuit with matrix, sensor amplifiers, bit and word decoders, a control logic, data input / output stages. The matrix contains redundancy bit or word decoder with associated redundancy bit or word lines in the usual organizational form. Furthermore, the memory circuit contains a Selbsttestprozesscr and an evaluation and start logic. The self-test processor includes microprogram memory, control logic, a microprogram instruction counter, an ALU, a register bank, and a tri-state bus driver stage. The register bank contains with a number of registers corresponding to the number of redundancy lines, with four redundant bit or word lines 2 (R _x .R _y ) = 32 registers. The evaluation and start-up logic includes a self-test state multiplexer and a start logic circuit linked to the periphery via an output pin. According to the invention, the processor control logic is connected to a control signal register via a control signal bus carrying the address signals to be replaced. The control signal register is connected to the redundancy bit or word decoders via a column control signal bus.

The redundancy bit or word decoder contains associative memory cells corresponding to the number of address lines required in the organization form.

Each associative memory cell includes an sRAM cell and a comparator controlled by the sRAM cell and the address signals on the address lines and connected to a redundancy selection line common to all associative memory cells of a redundancy bit and word decoder, respectively.

Each redundancy bit or word decoder is associated with a write signal decoder controlled by the associated column or row control signal bus, whose output side write line is connected to the gates of the selection transistors of the sRAM cells in the associative memory cells. Furthermore, each redundancy bit or word decoder is assigned a redundancy validity FF, whose reset input is connected to a control line in the column or row control signal bus and whose set input is connected to the write line.

This FF assumes the role of a mainfuse, and the associative memory cells take on the role of address fuses of traditionally programmed redundancy.

The output of the redundancy valid FF is a.i to a transistor which is located between the redundancy select line and ground and keeps the redundancy selector in the reset state of the FF constantly inactive.

Furthermore, the evaluation and start logic includes a state-multiplexer controlled open-drain transistor, a Rosetsignaltrigger for the external start of the self-test process and possibly other programming means.

Irι embodiment of the invention, the state multiplexer is connected via a control line with a Programmierschalturig is connected on the output side via a control line with an irreversible memory element isi. Df.bei the memory element is the output side connected to the start logic circuit. It is programmed with error-free matrix, i.

if no redundancy bit or word lines have to be connected in order to select memory circuits for fast operational readiness. In addition to the saving of test time, it is also advantageous to be able to repair long-term bit errors, since programming takes place each time the instrument is switched on.

embodiment

The invention is explained below with reference to an embodiment and six drawings. Showing:

1 shows the block diagram of a 1 MdRAM with a self-test processor for performing the internal self-test and

Redundancy programming method Fig. 2: the block diagram of the Seibattest processor

Fig. 3: the block diagram of the evaluation and start logic of the self-test processor Figure 4: a redundancy Bitdekoiler Fig. 5: a Redur danz word decoder Fig. 6: a schematic representation of the procedure.

The memory circuit 1 shown in Fig. 1 consists of the following blocks, which are linked within the dRAM in a known manner. A memory matrix 2 with bit lines 2.1 and word lines 2.2 and memory cell 2.3 in the intersections contains four redundancy bit lines 2.4 and four redundancy word lines 2.5.

The matrix 2, which may be organized in various forms, is associated with sensor amplifier 3, bit decoder 4 and word decoder 5 as well as redundancy bit decoder 6 and redundant word decoder 7. A control logic 8 with the external control signals RAS; C AS; WE and the address signals AO... A9 are connected to the bit decoders 4 and the redundancy bit decoders 6 via a column address bus CASB and to the word encoders 5 and the redundancy word decoders 7 via a row address bus RASB. A data input stage 9 and a data output stage 10 are connected to the sense amplifiers 3 via an internal data bus IDAB.

The control sequence in the dRAM is specified via not-known, known control lines. Furthermore, the memory circuit 1 includes a self-test processor 11 and an evaluation and start logic 12 of the self-test processor 11, which together with the redundancy bit decoders 6, the redundancy word decoders 7 and the redundancy bit lines 2.4 and redundancy word lines 2.5 for Implementation of the method necessary arrangement. FIG. 2 shows the block diagram of the self-test processor 11.

The self-test processor 11 includes a microprogram memory 13, a processor control logic 14 connected to the microprogram memory 13 and a microprogram instruction counter 15, and an ALU 16 having a word width of 10 bits, via a 10-bit wide ALU register bus ARB is connected to one of 32 registers 17.0 ... 17.31 to lObit existing register bank 17. The outputs of the registers are 17.29 ... 17.31 with a tri-state bus driver stage 18 for the row-column address bus and data bus RASB; CASB; IDAB connected.

Furthermore, the self-test processor 11 includes a control signal register 19 which is connected to the processor control logic 14 via a control signal bus PRST. .

Furthermore, the control signal register 19 is connected to the redundancy word decoders 7 via a column control signal bus PRSTC having the redundancy bit code Ti 6 Iod via a row control signal bus PRSTR. The processor control logic 14 is üb "a control line bus BIS connected to the evaluation and control logic 12 of the self-test processor 11 via the St e uerle itung EXE is the processor control logic 14 to the control logic 8 for locking the exte ^ ien Steuercignala RAS..; CAS; WE and the address signals AO ... A9 connected

 In Figure 3, the evaluation and control logic 12 of the self-test processor 11 is shown.

It includes a self-test state multiplexer 20 which is connected to the self-test processor 11 via the control line bus BIZ and to the control logic 8 via a control line bus DSTB.

The state multiplexer 20 is connected to the gate of an open-drain transistor 21, whose drain is connected to an output pin MR and a reset signal trigger 22.

The output of the externally started reset signal trigger is connected via a control line BIRST to a start logic circuit 23 and causes an external start of the self-test procedure. Furthermore, the state multiplexer 20 is connected via a control line PREN to a programming circuit 24, which is connected to an irreversible memory element 25 via a control line IPRST.

The memory element 25 is connected on the output side via a control line BLSTE and the control line bus DSTB via a control line POST to the Startlogikschpl'.ung 23, which is connected on the output side via a control line BIS to the control line bus BIZ.

As shown in Fig. 4, each of the redundancy bit decoder β consists of nine associative memory cells 30.0 ... 30.8. Each associative memory line 30.η contains an sRAM cell 31 with four transistors 31.1... 31.4 forming a memory FF and two selection transistors 31.5; 31.6 for writing the information in the sRAM cell 31. The selection transistors 31.5; 31.6 are between the associated address line AnCAS; A.η CAS and the corresponding output Q; Q of the RAM array 31 are arranged at their gates are connected to a write line WRR.

In addition, each associative memory cell 30 .eta. Contains a comparator 32 which contains two redundant redundancy selection lines RAL and ground assigned to all associative memory cells 30. 0... 30. 8 of two nMOS transistors 32. Their gates are thereby from the address lines A. η CAS; A .η CAS and outputs Q; Q of the sRAM cell 31 is driven.

A write signal decoder 33, to which the column control signal bus PRSTC is present, supplies the associated write line WRR at the output.

A redundancy validity FF 34 of four FF transistor 34.1 ... 34.4 contains between the outputs P; P and ground M two transistors 34.5; 34.6, the control line BRES of the column control signal bus PRSTC being applied to the transistor 34.5 and the write line WRR being applied to the transistor 34.6.

A transistor 34.7 on which the output P is applied is arranged between the redundancy selection RAL and ground M. A pMOS transistor 35.1 controlled by the output I and a precharging transistor 35.2 controlled by the precharge clock TBV are arranged between the operating voltage U _cc and the redundancy selection line RAL.

The redundancy selection line RAL and a dRAM internal control clock TBC constitute the inputs of an AND gate 36 with the redundancy bit line selection signal RBL as an output. Furthermore, the redundancy selection line RAL is connected to an inverter 37 whose output carries the deselect control signal DEBL for the bit decoder 4 of the memory matrix 2. FIG. 5 shows a redundancy word decoder 7 which contains 8 associative memory cells 40.0... 40. 7 consisting of an sRAM cell 41 and a comparator 42. This structure corresponds to that in the redundancy bit decoder 6. A write signal decoder 43, to which the lines control signal bus PRSTR is present, carries the associated write line WRR on the output side. A redundancy valid FF 44 with the transistors 44.1 ... 44.7 is controlled by the control line BRES of the row control signal bus PRSTR and the write line WRR and in turn controls the t ansistor 44.7, between the associated redundancy selection RAL and Mass M is arranged.

One controlled by the control line TSWL and the redundancy selection line RAL jj. NAND gate 45.1 controls a reload transistor 45.2, which is arranged between the supply voltage U _cc and the redundancy selection line RAL, and an inverter 45.3 whose output carries the deselect control signal DEWL for the word coder 5 of the memory matrix 2.

Furthermore, between the supply voltage U _a and the redundancy selection line RAL, a pMOS transistor 46.1, which is controlled by redundancy-validity FF 44, and a Vorladetransistor 46.2 controlled by the precharge TWV arranged. The redundancy selection line RAL is connected via an inverter 47 to an inverter 48 and to the gate of a driver transistor 49.1 between the output and ground. The inverter 48 is connected via a reversed barrier transistor 50 to the gate of a second driver transistor 49.2 between the supply voltage Ucc and the output, the output carrying the redundancy word line selection signal RWL. In Fig. 6 the process flow is shown schematically.

When the supply voltage U _CC is applied, the control logic 8 outputs the enable signal to the evaluation and start logic 12 after reaching internal stability via the control line POST of the control line bus DSTB. The memory circuit 1, which is not yet active, reports this state via the control line bus BIZ, State multiplexer 20, the transistor 21 and the output pin MR to the periphery.

Mm as the Mikroprogra gespeicher t e is started rfahren Ve of the activated control signal BIS. When activated, all external control signals RAS; CAS; WE, the address signals AO ... A9 and the data inputs / outputs DIN; DOUT locked. Access to the row / column address book RASB; CASB and to the data bus IDAB takes place exclusively for the self-test processor 11.

The first part of the self-test consists of the self-test process 11 self-test which consists of the microprogram memory 13 checksum, the ALU 16 test, the register bank 17 test, and the processor control logic 14 test. These tests are performed by the execution of a microprogram, i. by modifying the microprogram instruction counter 15 by the processor control logic, addressing a microinstruction in the microprogram memory 13 by the instruction counter 15, evaluating the read instruction word by the processor control logic 13, setting the resulting control signals to the ALU 16 and register bank 17, and preparing the next microinstruction again modifying the command counter 15.

In the next method step, the bit and word decoder 4; 5 by performing internal read-write cycles over the column / row address bus CASB; RASB and the IDAB data bus.

After successful completion of these method steps, the memory matrix 2 is checked in the next method step via read-write cycles and the bit error addresses are stored in the register bank 17 of the self-test processor 11. Due to the typical internal organization of a dRAMS, several memory cells are simultaneously read or written over the internal data bus. The test is carried out with a well-known memory test algorithm, z. B. the marching test.

If no bit errors occur during the test of the matrix, then this state is reported via the control line bus BIZ to the state multiplexer 20, which activates the programming circuit 24 via the now activated signal line PREN, whereby the irreversible memory element 25 is set via the control line IPRST.

With a restart possible via the output pin MR and the reset signal trigger (control line BIRST), the restart is blocked via the control line BISTE. These memory circuits "* Ί can thus be selected for special purposes, since no self-test at power-up, e.g. for use with immediate operational readiness.

In the following method step, the optimal use of the redundant part of the matrix 2 is calculated for a given error image and the calculated addresses have been transmitted via the column / row address bus CASB; RASB is applied to the redundancy bit / word decoder 6, 7 and via the column / row control signal bus PRSTC; PRSTR into the associated associative memory cells 30. »; 40.η enrolled. For this purpose, the corresponding write line WRR is activated and the selection transistors 31.5; 31.6 or 41.5; 41.6 the angewä hlten Assoz iativspeichurz economic 30.n; 4 0.η are opened. Thus, the on the associated address lines to CAS; A .n CAS or An RAS; A .n RAS applied error messages in the sRAM Ztille 31; 41 inscribed. Furthermore, in redundancy programming, the redundancy validity FF 34, which is reset at the beginning of the method or when restarting via the control line BRES, is reset. 44 via the transistors 34.6; 44.6 set. As a result, the transistor 34.7; 44.7 is disabled and the redundancy selection line RAL can assume active high potential. With writing of all error addresses, the faulty lines are redundant bit / word lines 2.4; 2.5 replaced. In the next method step, the programmed redundancy bit / word lines 2.4; 2.5 also tested according to the test algorithm.

If there are still errors, free redundancy bit / word lines 2.4; 2.5 are present, these are selected and also subjected to the test.

In the event of non-reparable errors, the memory circuit remains in the inactive state, however, the state multiplexer 20 is reset at the positive completion of the process by the self-test processor via the control line bus BIZ, whereby the open-droin transistor 21 blocks again and the signal at the output pin MR at externally checked Voltage becomes active.

Claims (3)

1. Internal self-test and redundancy programming method for memory circuits, in which, after applying the operating voltage and achieving internal stability, the internally stored self-test procedure is started, locking the external control inputs and addresses, and the data input data of the memory circuit, thereafter internally using a self-test processor is checked, the data paths of the memory circuit are checked and then the matrix is checked with the memory cells, after which the error addresses are stored in a register bank of the self-test processor and from the distribution of Feh'eradrossen for reparability the optimal Reduni'anzstruktur is determined and wherein after redundancy bit lines or word lines are subjected to the current test, characterized in that according to the determined redundancy structure, an internal programming of redundancy bit decoders (6) or of Redu ndanz word decoders (7), which contain erasable associative memory cells (30) and which are assigned to the redundancy bit lines (2.4) and the redundant word lines (2.5), respectively, in the case of redundancy programming, a redundancy validity reset at the beginning of the self-test. FF (34; 44) it is ensured that the positive loading of the self-test method is achieved by the release of the locked control inputs (R AS; CAS; WE; AO ... A9; DIN; DOUT) and possibly by a signal at an output pin (MR). takes place and that in an error-free memory matrix (2) an irreversible memory element (25) is optionally programmed. 2. Arrangement for carrying out the self-test and redundancy programming method according to claim 1, wherein the arrangement consists of a Speicherschaltkruis with a matrix, sensor amplifiers, bit and Wortdel Odern, control logic, data input / data output stages, the matrix redundancy bit or In addition, the memory circuit includes a self-test processor and an evaluation and start logic, wherein the self-test processor microprogram memory, a control logic, a microprogram instruction counter, an arithmetic logical processing unit, a register bank with a the number of registers corresponding to the number of redundancy lines and a tristate bus driver stage, and wherein the evaluation and start logic includes a self-test state multiplexer and a start logic circuit associated with the peripheral, characterized in that the processor control logic (14) via a control signal bus (PRST), which leads to the address signals to be replaced, is connected to a control signal register (19) that the control signal register (19) via a column-line control signal bus (PRSTC; PRSTR) is connected to the redundancy bit or word decoders (6; 7) such that the redundancy bit and word decoders (6; 7) are associative memory cells (3O.n; 40.n) each consisting of an sRAM cell (31) and a comparator (32) e, according to the number of address lines (An, A.n) required in the organization form, that each redundancy bit or word decoder (6; 7) has an associated column The output side write line (WRR) is connected to the gates of the selection transistors (31.5, 31.6) and (41.5, 41.6) in the associative memory cells (3O.n; 4O.n) that each redundancy bit resp. Word processor (6; 7) is associated with a redundancy valid FF (34; 44) whose reset input is connected to a control line (BRES) in the column row control signal bus (PRSTC; PRSJR) and whose set input is connected to the write line WRR and whose Output (P) at the gate of a between a known redundancy selection line (RAL) in the redundancy bit or word decoder (6; 7) and ground (M) arranged transistor abuts that the evaluation and start logic one from the state multiplexer (20) controlled open-drain transistor (21) and a reset signal trigger (22) and possibly further programming means contains. 3. Arrangement according to claim 1, characterized in that the state multiplexer (20) via a control line (PREN) with a programming circuit (24) is connected on the output side via a control line (IPRST) with an irreversible memory element (25) and that the memory element (25) is connected on the output side to the start logic circuit (12). For this 6 pages drawings